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C2EPKcPNS_10ConfigItemEPS0__ZN10config4cpp16ConfigScopeEntryD2Ev_ZN10config4cpp16ConfigScopeEntry7setItemEPNS_10ConfigItemE_ZN10config4cpp6MBChar3addEc_ZNK10config4cpp6MBChar6lengthEv_ZNK10config4cpp6MBChar7isEmptyEv_ZNK10config4cpp6MBChar6isFullEv_ZNK10config4cpp6MBChar5c_strEv_ZN10config4cpp6MBChar5resetEv_ZN10config4cpp13ConfigurationC2Ev_ZTVN10config4cpp13ConfigurationE_ZN10config4cpp13ConfigurationC1Ev_ZN10config4cpp13ConfigurationD2Ev_ZN10config4cpp13ConfigurationD1Ev_ZN10config4cpp13ConfigurationD0Ev_ZN10config4cpp17ConfigurationImplC1Ev_ZN10config4cpp13Configuration7destroyEv_ZN10config4cpp13Configuration8mbstrlenEPKc_ZN10config4cpp6MBCharC1Evmbrtowc_ZN10config4cpp6MBCharD1Evmbstowcs_ZN10config4cpp13Configuration20patternMatchInternalEPKwiiS2_ii_ZTIN10config4cpp13ConfigurationE_ZTSN10config4cpp13ConfigurationE_ZN10config4cpp22ConfigurationExceptionC2EPKc_ZN10config4cpp22ConfigurationExceptionC2ERKS0__ZN10config4cpp22ConfigurationExceptionC1ERKS0__ZN10config4cpp22ConfigurationExceptionD2Ev_ZN10config4cpp13Configuration5parseEPKc_ZNK10config4cpp11ConfigScope20listFullyScopedNamesENS_13Configuration4TypeEbRKNS_12StringVectorERS3__ZNK10config4cpp11ConfigScope22listLocallyScopedNamesENS_13Configuration4TypeEbRKNS_12StringVectorERS3__ZNK10config4cpp17ConfigurationImpl8fileNameEv_ZN10config4cpp17ConfigurationImplC2Ev_ZTVN10config4cpp17ConfigurationImplE_ZN10config4cpp28DefaultSecurityConfiguration9singletonE_ZN10config4cpp17ConfigurationImplD2Ev_ZN10config4cpp17ConfigurationImplD1Ev_ZN10config4cpp17ConfigurationImplD0Ev_ZN10config4cpp17ConfigurationImpl24setFallbackConfigurationEPNS_13ConfigurationE_ZN10config4cpp17ConfigurationImpl24setFallbackConfigurationENS_13Configuration10SourceTypeEPKcS4__ZN10config4cpp17ConfigurationImpl24getFallbackConfigurationEv_ZN10config4cpp17ConfigurationImpl24setSecurityConfigurationEPNS_13ConfigurationEbPKc_ZN10config4cpp17ConfigurationImpl24setSecurityConfigurationEPKcS2__ZN10config4cpp17ConfigurationImpl24getSecurityConfigurationERPKNS_13ConfigurationERPKc_ZN10config4cpp17ConfigurationImpl5parseENS_13Configuration10SourceTypeEPKcS4__ZNK10config4cpp17ConfigurationImpl4typeEPKcS2__ZN10config4cpp12StringVectoraSERKS0__ZNK10config4cpp17ConfigurationImpl9listValueEPKcS2_RPS2_RiRNS_13Configuration4TypeE_ZNK10config4cpp12StringVector7c_arrayERPPKcRi_ZN10config4cpp17ConfigurationImpl12insertStringEPKcS2_S2__ZN10config4cpp25splitScopedNameIntoVectorEPKcRNS_12StringVectorE_ZN10config4cpp17ConfigurationImpl17ensureScopeExistsERKNS_12StringVectorEiiRPNS_11ConfigScopeE_ZN10config4cpp17ConfigurationImpl17ensureScopeExistsEPKcS2__ZN10config4cpp17ConfigurationImpl10insertListEPKcS2_PS2_i_ZN10config4cpp17ConfigurationImpl10insertListEPKcS2_PS2__ZN10config4cpp17ConfigurationImpl10insertListEPKcS2_RKNS_12StringVectorE_ZN10config4cpp17ConfigurationImpl10insertListEPKcRKNS_12StringVectorE_ZN10config4cpp17ConfigurationImpl6removeEPKcS2__ZN10config4cpp17ConfigurationImpl5emptyEv_ZNK10config4cpp17ConfigurationImpl12lookupHelperEPNS_11ConfigScopeERKNS_12StringVectorE_ZNK10config4cpp17ConfigurationImpl4dumpERNS_12StringBufferEb_ZNK10config4cpp17ConfigurationImpl4dumpERNS_12StringBufferEbPKcS4__ZNK10config4cpp17ConfigurationImpl20listFullyScopedNamesEPKcS2_NS_13Configuration4TypeEbRNS_12StringVectorE_ZNK10config4cpp17ConfigurationImpl20listFullyScopedNamesEPKcS2_NS_13Configuration4TypeEbS2_RNS_12StringVectorE_ZNK10config4cpp17ConfigurationImpl20listFullyScopedNamesEPKcS2_NS_13Configuration4TypeEbRKNS_12StringVectorERS5__ZNK10config4cpp17ConfigurationImpl22listLocallyScopedNamesEPKcS2_NS_13Configuration4TypeEbS2_RNS_12StringVectorE_ZNK10config4cpp17ConfigurationImpl22listLocallyScopedNamesEPKcS2_NS_13Configuration4TypeEbRNS_12StringVectorE_ZNK10config4cpp17ConfigurationImpl22listLocallyScopedNamesEPKcS2_NS_13Configuration4TypeEbRKNS_12StringVectorERS5__ZNK10config4cpp17ConfigurationImpl12lookupStringEPKcS2_S2__ZNK10config4cpp17ConfigurationImpl12lookupStringEPKcS2__ZNK10config4cpp17ConfigurationImpl10lookupListEPKcS2_RPS2_RiS3_i_ZNK10config4cpp17ConfigurationImpl10lookupListEPKcS2_RPS2_Ri_ZNK10config4cpp17ConfigurationImpl10lookupListEPKcS2_RNS_12StringVectorERKS3__ZNK10config4cpp17ConfigurationImpl10lookupListEPKcS2_RNS_12StringVectorE_ZNK10config4cpp17ConfigurationImpl10lookupEnumEPKcS2_S2_PKNS_16EnumNameAndValueEiS2__ZNK10config4cpp17ConfigurationImpl10lookupEnumEPKcS2_S2_PKNS_16EnumNameAndValueEii_ZNK10config4cpp17ConfigurationImpl10lookupEnumEPKcS2_S2_PKNS_16EnumNameAndValueEi_ZNK10config4cpp17ConfigurationImpl7enumValEPKcPKNS_16EnumNameAndValueEiRi_ZN10config4cpp13countBoolInfoE_ZNK10config4cpp17ConfigurationImpl13lookupBooleanEPKcS2_b_ZNK10config4cpp17ConfigurationImpl13lookupBooleanEPKcS2__ZNK10config4cpp17ConfigurationImpl9lookupIntEPKcS2_i_ZNK10config4cpp17ConfigurationImpl9lookupIntEPKcS2__ZNK10config4cpp17ConfigurationImpl12lookupUint32EPKcS2__ZNK10config4cpp17ConfigurationImpl12lookupUint64EPKcS2__ZNK10config4cpp17ConfigurationImpl5isIntEPKc_ZNK10config4cpp17ConfigurationImpl11stringToI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t8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE14_M_insert_nodeEPSt18_Rb_tree_node_baseSG_PSt13_Rb_tree_nodeIS8_E_ZNSt4pairISt17_Rb_tree_iteratorIS_IKSsSt8functionIFP17abstract_device_tRS1_EEEEbEC1IS9_bLb1EEEOT_OT0__ZNSt17_Rb_tree_iteratorISt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEEEC1EPSt18_Rb_tree_node_base_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE14_M_lower_boundEPSt13_Rb_tree_nodeIS4_EPSt18_Rb_tree_node_baseRS1__ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE11_M_get_nodeEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE17_M_construct_nodeIJRKSt21piecewise_construct_tSt5tupleIJRS1_EESF_IJEEEEEvPSt13_Rb_tree_nodeIS4_EDpOT__ZNKSt23_Rb_tree_const_iteratorISt4pairIKmP17abstract_device_tEE13_M_const_castEv_ZNKSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE4sizeEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE12_M_rightmostEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE6_S_keyEPKSt18_Rb_tree_node_base_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE24_M_get_insert_unique_posERS1__ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE11_M_leftmostEv_ZNSt17_Rb_tree_iteratorISt4pairIKmP17abstract_device_tEEmmEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE8_S_rightEPSt18_Rb_tree_node_base_ZNSt17_Rb_tree_iteratorISt4pairIKmP17abstract_device_tEEppEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE8_S_valueEPKSt13_Rb_tree_nodeIS4_E_ZNKSt10_Select1stISt4pairIKmP17abstract_device_tEEclERKS4__ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE15_M_destroy_nodeEPSt13_Rb_tree_nodeIS4_E_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE11_M_put_nodeEPSt13_Rb_tree_nodeIS4_E_ZNSt17_Rb_tree_iteratorISt4pairIKmP17abstract_device_tEEC2EPSt18_Rb_tree_node_base_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE7_S_leftEPSt18_Rb_tree_node_base_ZN9__gnu_cxx16__aligned_membufISt4pairIKmP17abstract_device_tEE7_M_addrEv_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE15_M_destroy_nodeEPSt13_Rb_tree_nodeIS8_E_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE11_M_put_nodeEPSt13_Rb_tree_nodeIS8_E_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE6_M_endEv_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE14_M_lower_boundEPSt13_Rb_tree_nodeIS8_EPSt18_Rb_tree_node_baseS5__ZN9__gnu_cxx16__aligned_membufISt4pairIKSsSt8functionIFP17abstract_device_tRS2_EEEE6_M_ptrEv_ZNKSs7compareERKSs_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE11_M_get_nodeEv_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE17_M_construct_nodeIJRSsRS7_EEEvPSt13_Rb_tree_nodeIS8_EDpOT__ZNSt4pairIPSt18_Rb_tree_node_baseS1_EC2IRPSt13_Rb_tree_nodeIS_IKSsSt8functionIFP17abstract_device_tRS5_EEEERS1_Lb1EEEOT_OT0__ZSt7forwardIRPSt13_Rb_tree_nodeISt4pairIKSsSt8functionIFP17abstract_device_tRS2_EEEEEOT_RNSt16remove_referenceISD_E4typeE_ZNSt4pairIPSt18_Rb_tree_node_baseS1_EC1IRPSt13_Rb_tree_nodeIS_IKSsSt8functionIFP17abstract_device_tRS5_EEEERS1_Lb1EEEOT_OT0__ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE5beginEv_ZNSt17_Rb_tree_iteratorISt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEEEmmEv_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE6_S_keyEPKSt18_Rb_tree_node_base_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE8_S_valueEPKSt13_Rb_tree_nodeIS8_E_ZNKSt10_Select1stISt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEEEclERKS8__ZSt7forwardISt17_Rb_tree_iteratorISt4pairIKSsSt8functionIFP17abstract_device_tRS2_EEEEEOT_RNSt16remove_referenceISB_E4typeE_ZNSt4pairISt17_Rb_tree_iteratorIS_IKSsSt8functionIFP17abstract_device_tRS1_EEEEbEC2IS9_bLb1EEEOT_OT0__ZSt7forwardIbEOT_RNSt16remove_referenceIS0_E4typeE_ZNSt17_Rb_tree_iteratorISt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEEEC2EPSt18_Rb_tree_node_base_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE21_M_get_Node_allocatorEv_ZNSt16allocator_traitsISaISt13_Rb_tree_nodeISt4pairIKmP17abstract_device_tEEEE8allocateERS7_m_ZNSt16allocator_traitsISaISt13_Rb_tree_nodeISt4pairIKmP17abstract_device_tEEEE9constructIS5_JRKSt21piecewise_construct_tSt5tupleIJRS2_EESD_IJEEEEEvRS7_PT_DpOT0__ZNSt8_Rb_treeImSt4pairIKmP17abst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@XA}tSA{ƨ_C@@@@?jT@@C_@@T@A@@_  _{ '@HE@Ҡ@@@I @@@7@A!HE@!@A?@T @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RR@qT@,D_엠/@ C>/@//@ Cy@cC|@ 엠/@+@7@SA[BcC{Ǩ_{ '@HE@Ҡ@@@ @@@72@A!HE@!@A?@Ty @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RMR@qTҒ@,D엠/@ C/@/@y CO@cC}|@엠/@+@7@SA[BcC{Ǩ_{S@@TQ@@\G엡@@엠OO@*@@엠O@GT T"엠/-/@/@@@@ ?@Ft엠++@+@@@@ ?@XA^vSA{ƨ_{S@@T@@\G3엡@@(엠OO@*@@T엠O@GT Tp엠//@/@@@@ ?@FZ엠+ҫ+@+@@@@ ?$@XA xSA{ƨ_C@@@@?kjT@@C_@@T@A@@_  _{ @@@R @@ '@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RR@qT$@,Dr엠g@q@T@,D_엠/@ C>/@//@ Cy@cC 엠/@+@~7@SA[BcC{Ǩ_{ @@@ @@*@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!R]R@qTҢ ,D엠g@q@Tҏ ,D엠/@ C/@/@v CL@cC|엠/@+@7@SA[BcC{Ǩ_{S@@TO@@\G엡@@엠''@@@엠'@GT T 엠/+/@/@@@@ ?@Fr엠++@+@@@@ ?@XA\}tSA{ƨ_{S@@T@@\G1엡@@엠''@@@엠'@GT Tn엠/ҿ/@/@@@@ ?@FX엠+ҩ+@+@@@@ ?"@XAvSA{ƨ_@@T@A@@_  _{ ' HE@Ҡ@@@Y @@.@7@!!HE@!@A?@T @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RR@qT! ,Do엠/@ CN/@?/@ C@cC|@엠/@+@7@SA[BcC{Ǩ_{ ' HE@Ҡ@@@ @@@7@!!HE@!@A?@T @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!R]R@qTҢ ,D엠/@ C/@/@ C _@cC}|@엠/@+@7@SA[BcC{Ǩ_{S@@Ta@-@\G엡@@엠OO@*@@엠O@GT T2엠/=/@/@@@@ ?@F엠+'+@+@@@@ ?@XAnSA{ƨ_{S@@T@@\GC엡@@8엠OO@*@@d엠O@GT T엠//@/@@@@ ?.@Fj엠+һ+@+@@@@ ?4@XA/#&SA{ƨ_C@@@@?kbT@@C_@@T@A@@_  _{  HE@Ҡ@@@] @@2@Q@!!HE@!@A?@T @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RR@qT% ,Ds엠g@q@T ,D`엠/@ C?/@0/@ Cz@cC 엠/@+@o7@SA[BcC{Ǩ_{  HE@Ҡ@@@ @@@@!!HE@!@A?@T{ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!ROR@qTҔ ,D엠g@q@Tҁ ,D엠/@q C/@/@h C>@cC||엠/@+@7@SA[BcC{Ǩ_{S@@TA@ \G엡@@엠''@@@엠'@GT T엠//@/@@@@ ?z Fd엠++@+@@@@ ? XAN{orfSA{ƨ_{S@@T@ \G#엡@@엠''@@@엠'@GT T`엠/ұ/@/@@@@ ? FJ엠+қ+@+@@@@ ? XAqhSA{ƨ_@@T@A@@_  _{ ' HE@Ҡ@@@K @@ @7@!!HE@!@A?@T @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RR@qT ,Da엠/@ C@/@1/@ C{@cC|@ 엠/@+@7@SA[BcC{Ǩ_{ ' HE@Ҡ@@@ @@@7@!!HE@!@A?@T{ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!ROR@qTҔ ,D엠/@ C/@/@{ CQ@cC}|@엠/@+@7@SA[BcC{Ǩ_{S@@TS@ \G엡@@엠OO@*@@엠O@GT T$엠///@/@@@@ ? Fv엠++@+@@@@ ? XA`xSA{ƨ_{S@@T@ \G5엡@@*엠OO@*@@V엠O@GT Tr엠//@/@@@@ ? F \엠+ҭ+@+@@@@ ?& XA! zSA{ƨ_C@@@@?kjT@@C_@@T@A@@_  _{ @@@T @@ )f@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RR@qT& ,Dt엠g@q@T ,Da엠/@ C@/@1/@ C{@cC엠/@+@~7@SA[BcC{Ǩ_{ @@@ @@@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!R_R@qTҤ ,D엠g@q@Tґ ,D엠/@ C/@/@x CN@cC|엠/@+@7@SA[BcC{Ǩ_{S@@TQ@ \G엡@@엠''@@@엠'@GT T"엠/-/@/@@@@ ? Ft엠++@+@@@@ ? XA^vSA{ƨ_{S@@T@ \G3엡@@엠''@@@엠'@GT Tp엠//@/@@@@ ? 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ś[[ڔQ+(ٳ'z8TfAX\$~sީqK3?#Db;uj= bڸC 7 RzRCK,΁2^_B?;5I~t۝Xv%RӮS;uD(m,{tPd弦a}J]J62w\Mľڬ:|\ 5$KB.̈Po ̼$ 믿ۘ6A_paw̫BzՔֶil7$GGŧ,eX= _Nm (which is %zu)%Y-%m-%d %H:%M:%S[*** LOG ERROR #%04zu ***] [%s] [%s] %s Rethrowing unknown exception in loggerPMAM %s:%d: assertion failed: %sinvalid fill character '{'invalid fillcannot switch from manual to automatic argument indexinginvalid number of digitsvalue is negative0123456789ABCDEFnumber is too bigformat specifier requires numeric argumentformat specifier requires signed argumentinvalid digit count00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899empty bufferexponent out of rangewidth/precision is not integercompile-time checks for named arguments require C++20 supportinvalid format stringcannot switch from automatic to manual argument indexingmissing precision specifierprecision not allowed for this argument typenaninfINFNANnegative widthwidth is not integernegative precisionprecision is not integer{} [{}({})]{:02}unmatched '}' in format stringinvalid type specifierunknown format specifiermissing '}' in format stringstring pointer is nullinvalid format specifier for chartruefalsenegative valueunaligned bigintsriscv_plugin.ccargument not foundn is too largek is out of rangeshifting error detected0123456789abcdefRISCV plugin: hwts ISR called DESTROY RISCV PLUGIN RISCV plugin trace: 0x%x CREATE RISCV PLUGIN SPR_PCSPR_BLK_IDSPR_STATUSSPR_CTRLSPR_PARA_BASESPR_DATA_MAIN_BASESPR_DATA_UB_BASESPR_DATA_SIZESPR_LPCNTSPR_BLOCKDIMSPR_FMATRIXSPR_Condition_FlagSPR_DEQSCALESPR_LRELU_ALPHASPR_PADDINGSPR_L2_vaddr_baseSPR_L0_SET_VALUESPR_CORE_IDSPR_VMS4_SRSPR_L2_IN_MAINSPR_RPN_COR_IRSPR_ARCH_VERSPR_SMMU_TAG_VERSPR_L1_3D_SIZESPR_AIPP_SPR_0SPR_AIPP_SPR_1SPR_AIPP_SPR_2SPR_AIPP_SPR_3SPR_AIPP_SPR_4SPR_AIPP_SPR_5SPR_AIPP_SPR_6SPR_AIPP_SPR_7SPR_AIPP_SPR_8SPR_AIPP_SPR_9SPR_AIPP_SPR_10SPR_AIPP_SPR_11SPR_AIPP_SPR_12SPR_AIPP_SPR_13SPR_AIPP_SPR_14SPR_AIPP_SPR_15SPR_AIPP_SPR_16SPR_AIPP_SPR_17SPR_AIPP_SPR_18SPR_AIPP_SPR_19SPR_AIPP_SPR_20SPR_AIPP_SPR_21SPR_AIPP_SPR_22SPR_AIPP_SPR_23SPR_AIPP_SPR_24SPR_DATA_EXP_0SPR_DATA_EXP_1SPR_DATA_EXP_2SPR_DATA_EXP_3SPR_LOW_PRE_TBLSPR_SMASK_INDEXSPR_K_NUMSPR_RPN_OFFSETSPR_FCOL2IMGSPR_RSVD_CNTSPR_TIDSPR_CONDSPR_PNT_COESPR_VPIPESPR_MAX_MIN_CNTSPR_MASK1SPR_MASK2SPR_MASK3SPR_MASK4SPR_MASK5SPR_MASK6SPR_MASK7SPR_MASK8SPR_UNZIP_INDEX_BASESPR_UNZIP_INDEX_LENSPR_CMP_MASK1SPR_CMP_MASK2SPR_CMP_MASK3SPR_CMP_MASK4SPR_CMP_MASK5SPR_CMP_MASK6SPR_CMP_MASK7SPR_CMP_MASK8SPR_CONVSPR_SMMU_STREAMIDSPR_RUN_STALLSPR_SMMU_SUBSTREAMIDSPR_MEMMAP_0SPR_MEMMAP_1SPR_MEMMAP_2SPR_MEMMAP_3SPR_MEMMAP_4SPR_MEMMAP_5SPR_MEMMAP_6SPR_MEMMAP_7SPR_MEMMAP_8SPR_MEMMAP_9SPR_MEMMAP_10SPR_MEMMAP_11SPR_MEMMAP_12SPR_MEMMAP_13SPR_MEMMAP_14SPR_MEMMAP_15SPR_MEMMAP_16SPR_MEMMAP_17SPR_MEMMAP_18SPR_MEMMAP_19SPR_MEMMAP_20SPR_MEMMAP_21SPR_MEMMAP_22SPR_MEMMAP_23SPR_MEMMAP_24SPR_MEMMAP_25SPR_MEMMAP_26SPR_MEMMAP_27SPR_MEMMAP_28SPR_MEMMAP_29SPR_MEMMAP_30SPR_MEMMAP_31SPR_MEMMAP_32SPR_MEMMAP_33SPR_MEMMAP_34SPR_MEMMAP_35SPR_MEMMAP_36SPR_MEMMAP_37SPR_MEMMAP_38SPR_MEMMAP_39SPR_MEMMAP_40SPR_MEMMAP_41SPR_MEMMAP_42SPR_MEMMAP_43SPR_MEMMAP_44SPR_MEMMAP_45SPR_MEMMAP_46SPR_MEMMAP_47SPR_MEMMAP_48SPR_MEMMAP_49SPR_MEMMAP_50SPR_MEMMAP_51SPR_MEMMAP_52SPR_MEMMAP_53SPR_MEMMAP_54SPR_MEMMAP_55SPR_MEMMAP_56SPR_MEMMAP_57SPR_MEMMAP_58SPR_MEMMAP_59SPR_MEMMAP_60SPR_MEMMAP_61SPR_MEMMAP_62SPR_MEMMAP_63SPR_LITERAL_SRC_BASESPR_LITERAL_DST_BASESPR_LITERAL_SIZESPR_L2_PHYS_ADDR_BASESPR_MTE_CTRLSPR_BIU_CTRL8SPR_L2_SIZESPR_L2_PAGE_SIZESPR_CCU_STALL_ENSPR_L2_REMAP_CFG0SPR_L2_REMAP_CFG1SPR_L2_REMAP_CFG2SPR_L2_REMAP_CFG3SPR_L2_REMAP_CFG4SPR_L2_REMAP_CFG5SPR_L2_REMAP_CFG6SPR_L2_REMAP_CFG7SPR_L2_REMAP_PADDR_BASESPR_CUBE_RESERVED_REG01SPR_L3D_RPTJanuaryFebruaryMarchAprilMayJuneJulyAugustSeptemberOctoberNovemberDecemberJanFebMarAprJunJulAugSeptOctNovDecSundayMondayTuesdayWednesdayThursdayFridaySaturdaySunMonTueWedThuFriSatIWOdebuginfowarningcriticaloffN13ascend_spdlog5sinks4sinkEN13ascend_spdlog5sinks14ansicolor_sinkINS_7details13console_mutexEEEN13ascend_spdlog5sinks21ansicolor_stdout_sinkINS_7details13console_mutexEEESt23_Sp_counted_ptr_inplaceIN13ascend_spdlog5sinks21ansicolor_stdout_sinkINS0_7details13console_mutexEEESaIS5_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17VirtualBusPortTbsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEthreadRunModelgetHwtsgetCorehwtsWriteRegisterWithAddrhwtsWrite32bitRegisterWithAddrhwtsReadRegisterWithAddrhwtsRead32bitRegisterWithAddrbusDirectReadbusDirectWritegetBusgetHwtsvwriteBinaryFilestartAICRiscvModelstartAIVRiscvModelmodelInit@ -+   *Z9stopModelEUlRKSt10shared_ptrIN13ascend_spdlog6loggerEEE_%+COLORTERMTERMmodel_api_ca.ccERROR[%s] %s:%d %s argv is null [%s] %s:%d %s g_hwts run errors [%s] %s:%d %s g_hwtsv run errors [%s] %s:%d %s core run errors [%s] %s:%d %s chip idx %u is too big [%s] %s:%d %s param is too big [%s] %s:%d %s core id %u is too big [%s] %s:%d %s registerValue ptr is null [%s] %s:%d %s ptr from outside is null [%s] %s:%d %s memory is null [%s] %s:%d %s infile is null [%s] %s:%d %s totalsize is too big, while totalsize = %lu, it should less than %lu %s open failed! [%s] %s:%d %s chip num %u is too big, while NUM_CHIP is %u [%s] %s:%d %s pc_addr is null [%s] %s:%d %s size array is null [%s] %s:%d %s Memery alloc failed %uhwtsriscvfw_aic_.elf[%s] %s:%d %s mem alloc failed hwtsvriscvfw_aiv_[%s] %s:%d %s fileName is null [%s] %s:%d %s Virtual Bus Port Tbs init failed [%s] %s:%d %s init failed [%s] %s:%d %s init errors =============================================================================== >>>> <<<< >>>> CA Model Init Suc <<<< Error: Model is already running and cannot be started. ansicolorconsolecygwingnomekonsolektermlinuxmsysputtyrxvtscreenvt100xtermalacrittyvt10215SlaveAccessPort8BasicBIUSt23_Sp_counted_ptr_inplaceI14BIUSlaveRDPortSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14BIUSlaveWRPortSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15BIUMasterRDPortSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15BIUMasterWRPortSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9MtePacketSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12BIUAccessReqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEproAtomicData@ readwriteDcacheReqwriteReqreadReqinitwrite            @                           @                        -+   basic_biu.ccmap::at[%s] %s:%d %s memcpy_s failed, error num: %d [%s] %s:%d %s MakeShared mem alloc failed Icache_rd_portDcache_rd_portMte_rd_portDcache_wr_portMte_wr_portBIU_rd_portBIU_wr_portWRRDN10config4cpp22ConfigurationExceptionE9BasicCoreinitinit_VdropCounterconfigureget_config_file@             @                           @                                                       9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" 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B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+   *ZN9BasicCore13ChangeLogPathESsbEUlSt10shared_ptrIN13ascend_spdlog6loggerEEE_basic_core.cc scalar_psq_ or tbs is nullenum_platform_typeplatform_typedavinciplatform_smmu_onl2_sizesystem_cache_sizebiu.port_numbiu.icache_portbiu.lsu_portbiu.dcache_portbiu.read_queue_sizebiu.write_queue_sizebiu.total_queue_sizebiu.high_priority_read_portbiu.high_priority_write_portbiu.enable_memmapbiu.ipu_port_widthbiu.mte_data_sizebiu.mte_port_widthbiu.mte_read_port_numbiu.mte_write_port_numbiu.bus_port_widthbiu.read_bus_port_widthbiu.write_bus_port_widthbiu.bus_read_port_numbiu.bus_write_port_numbiu.read_buffer_depthbiu.write_buffer_depthbiu.ifu_read_queue_sizebiu.dcache_port_widthbiu.dcache_read_queue_sizebiu.dcache_write_queue_sizebiu.addr_interleave_unitbiu.mem_entry_numbiu.physical_mem_entry_numbiu.is_chi_bus_infbiu.biu_esl_req_switchbuffer.aic_buffer_ini_valueddr.min_read_latencyddr.read_latency_diverddr.min_write_latencyddr.write_latency_diverl2.min_read_latencyl2.read_latency_diverl2.min_write_latencyl2.write_latency_diverddr.bandwidth_limitddr.max_credit_numl2.bandwidth_limitl2.read_bandwidth_limitl2.write_bandwidth_limitl2.max_credit_numsys.base_addrsys.min_read_latencysys.read_latency_diversys.min_write_latencysys.write_latency_diversys.bandwidth_limitsys.read_bandwidth_limitsys.write_bandwidth_limitsys.max_credit_numpsq.buffer_sizepsq.fetch_sizepsq.dispatch_sizeissue_queue.sizeissue_queue.cube_issue_queue_sizeissue_queue.vec_issue_queue_sizeissue_queue.vec_issue_queue_numissue_queue.vec_issue_ib_enableissue_queue.vec_issue_ib_sizeissue_queue.mte1_issue_queue_sizeissue_queue.mte1_issue_queue_ostd_numissue_queue.mte2_issue_queue_sizeissue_queue.mte2_issue_queue_ostd_numissue_queue.mte3_issue_queue_sizeissue_queue.mte3_issue_queue_ostd_numissue_queue.mte4_issue_queue_sizeissue_queue.mte4_issue_queue_ostd_numissue_queue.mte5_issue_queue_sizeissue_queue.mte5_issue_queue_ostd_numissue_queue.scalar_issue_queue_sizeissue_queue.event_queue_sizeissue_queue.event_queue_numissue_queue.ostd_numissue_queue.cube_issue_queue_ostd_numissue_queue.vec_issue_queue_ostd_numissue_queue.vec_issue_queue_conflictvector.scatter_portsvector.dma_versionvector.double_ctrlvector.ub_rd_wr_modevector.instr_fusionvector.new_versionvector.vcmpv_ctrlvector.fp16_inf_procub.addr_shiftub.buffer_sizeub.buffer_line_sizeub.buffer_bank_countub.vector_access_widthub.scalar_access_widthub.lsu_write_port_numub.scalar_rd_ub_latencyl1.buffer_sizel1.buffer_bg_numl1.buffer_line_sizel1.buffer_bank_countl1.core_access_widthl1.round_robbin_switchl1.bank_cnt_per_bgl1.l1_ecc_enscalar_buffer.base_addressscalar_buffer.sizescalar_buffer.ld_instr_ostdscalar_buffer.st_instr_ostdscalar_buffer.ld_st_separate_req_portscalar_buffer.ld_st_hazard_check_unitscalar_buffer.scalar_buffer_ecc_enmte.l1_read_bus_widthmte.l12l0c_max_bus_widthmte.biu_write_bus_widthmte.unibuf_write_bus_widthmte.unzip_engine_nummte.l0_write_delaymte.l1_read_delaymte.l1_write_delaymte.unibuf_write_delaymte.biu_mte_rob_slot_nummte.biu_mte_max_trans_sizemte.biu_mte_read_tagsmte.biu_mte_write_tagsmte.biu_mte_read_ostdmte.biu_mte_write_ostdmte.default_repeat_timemte.max_biu_if_trans_sizemte.max_rd_tagfifo_sizemte.lsu_biu_align_sizemte.biu_cmdgen_delaymte.reoder_buffer_switchmte.max_crdt_ue_3dmte.max_crdt_l1_ue_2dmte.max_crdt_biu_ue_2dmte.max_crdt_l1_ue_dmamte.max_crdt_biu_ue_dmamte.max_crdt_ue_unzipmte.max_crdt_ue_fmcmte.max_crdt_ue_fmdmte.max_crdt_ue_aippmte.max_crdt_ue_ksparsemte.max_crdt_ue_winogradmte.max_crdt_ue_depthwisemte.cmd_iq_arb_delay_timemte.cmd_arb_dispatch_delay_timemte.l1_read_rob_delaymte.ub_read_rob_delaymte.uzp_read_rob_delaymte.fmd_read_rob_delaymte.write_rob_delaymte.ktable_read_rob_delaymte.fmc_pad_valuemte.fmcd_engine_nummte.fmcd_head_sizemte.fmcd_mask_sizemte.fmcd_ubread_widthmte.fmcd_seg_sizemte.cube_sizemte.fmc_wdata_sizemte.fmc_write_bus_widthmte.max_fmc_uop_crdtmte.max_fmc_wheader_nummte.max_fetch_head_nummte.fmd_mte_wdata_delaymte.fmcd_header_len_unitmte.fmcd_interleave_sizemte.fmc_rdata_fifo_depthmte.min_h_resmte.max_h_resmte.byte_per_pixel_in_l1mte.y_dat_buf_sizemte.uv_dat_buf_sizemte.rgb_dat_buf_sizemte.uv_upsample_buf_sizemte.sync_buf_sizemte.csc_buf_sizemte.dtc_buf_sizemte.cpadding_buf_sizemte.pixels_per_transmte.img_dat_channelsmte.aipp_dat_buf_bubblemte.aipp_max_dtc_latmte.aipp_dtc_u8_fp16_latmte.aipp_dtc_u8_s8_latmte.pixels_per_batchmte.dma_uc_rd_sizemte.dma_dc_rd_sizemte.dma_buf_size_dcmte.dma_buf_size_ucmte.dma_pl0_ping_buf_addr_ucmte.dma_pl0_pong_buf_addr_ucmte.dma_pl1_ping_buf_addr_dcmte.dma_pl1_pong_buf_addr_dcmte.dma_pl0_ping_buf_addr_dcmte.dma_pl0_pong_buf_addr_dcmte.aipp_input_buf_bandwidthmte.unibuf_read_bus_widthmte.unibuf_trans_sizemte.winograd_c0_sizemte.read_colum_nummte.depthwise_c0_sizemte.data_fifo_nummte.max_crdt_fifo_depthmte.img2col_c0_sizemte.max_l1_uop_crdtmte.l1_to_l0_delaymte.l1_to_ub_delaymte.l1_to_ub_delay_2mte.max_ub_uop_crdtmte.ub_to_l1_req_delaymte.rtl_delaymte.unzip_pkt_sizemte.unzip_head_sizemte.unzip_dict_sizemte.unzip_low_sparse_dict_sizemte.unzip_str_dict_sizemte.unzip_out_lenmte.unzip_seg_sizemte.unzip_buffer_sizemte.unzip_entry_sizemte.max_fetch_idx_nummte.max_uzp_uop_crdtmte.unzip_delay_timemte.unzip_bypass_delay_timemte.unzip_buffer_depthmte.unzip_write_band_widthmte.ue_2d_delaymte.ue_3d_delaymte.ue_dma_delaymte.ue_smask_delaymte.biu_to_l1_bus_widthmte.biu_to_l0a_bus_widthmte.biu_to_l0b_bus_widthmte.biu_to_ub_bus_widthmte.biu_to_fmd_bus_widthmte.ub_to_biu_bus_widthmte.ub_to_l1_bus_widthmte.ub_to_smask_bus_widthmte.l1_to_l0a_bus_widthmte.l1_to_l0b_bus_widthmte.l1_to_l0c_bus_widthmte.l1_to_brc_bus_widthmte.l1_to_ub_bus_widthmte.winograd_l0a_bus_widthmte.winograd_l0b_bus_widthmte.depthwise_bus_widthmte.fmd_to_l1_bus_widthmte.fmd_to_ub_bus_widthmte.dma_scatter_modemte.dma_batch_modemte.winograd_new_versionmte.depthwise_early_startmte.l1_3d_size_roundmte.load_3d_v2_new_versionmte.aipp_bandwidth_limitmte.set2d_l1_bandwidthmte.set2d_l0a_bandwidthmte.set2d_l0b_bandwidthmte.layout_modedcache.dc_cross_line_numdcache.dc_set_sizedcache.dc_way_sizedcache.dc_line_sizedcache.dc_line_numdcache.dc_sizedcache.dc_max_read_otsd_numdcache.dc_max_write_otsd_numdcache.dc_idx_addr_lsbdcache.dc_idx_addr_maskdcache.dc_tag_addr_lsbdcache.dc_tag_addr_maskdcache.dc_wreq_wb_ctrlicache.ic_addr_widthicache.ic_asso_numicache.ic_sizeicache.ic_line_sizeicache.ic_entry_numicache.ic_line_numicache.ic_prefetch_numicache.ic_max_otsd_numicache.ic_max_preload_numicache.invalid_cache_line_numicache.ic_idx_addr_lsbicache.ic_idx_addr_maskicache.ic_tag_addr_lsbicache.ic_tag_addr_maskl0.ab_buffer_sizel0.ab_buffer_line_sizel0.a_buffer_sizel0.b_buffer_sizel0.a_buffer_line_sizel0.b_buffer_line_sizel0.ab_buffer_bank_countl0.ab_cube_access_widthl0.ab_lsu_access_widthl0.c_buffer_sizel0.c_buffer_line_sizel0.c_buffer_bank_countl0.c_cube_access_widthl0.c_vector_write_access_widthl0.c_vector_read_access_widthl0.c_buffer_line_size_cal0.c_buffer_bank_count_cal0.a_buffer_auto_pingpong_enl0.b_buffer_auto_pingpong_enl0.c_buffer_auto_pingpong_encube.cube_dummy_cycle_numbercube.cube_spec_npecube.cube_spec_cube_sizecube.global_sync_pulse_phase_typecube.vdrop_tickcube.n_frac_sizecube.m_frac_sizecube.support_small_channel_cube.early_trigger_set_flagcube.wino_cs_encube.dp_conv_cs_encube.mmad_offset_cs_encube.inf_nan_tr_version_endump.file_print_leveldump.screen_print_leveldump.flush_leveldump.dump_instr_maskdump.dump_cube_statusdump.dump_vector_statusdump.dump_scalar_statusdump.dump_ccu_statusdump.dump_dmac_statusdump.dump_mte_rob_statusdump.dump_mte_biu_stalldump.dump_mte_biu_reqdump.dump_mte_biu_respdump.dump_mte_rob_usagedump.dump_unzip_statusdump.dump_fmd_statusdump.dump_fmc_statusdump.dump_mte_statusdump.dump_buffer_wr_statusdump.dump_buffer_rd_statusdump.dump_biu_statusdump.dump_biu_resultdump.dump_biu_indump.dump_popped_instr_maskdump.dump_ub_statusdump.dump_issque_statusdump.dump_icache_statusdump.dump_buffer_op_timedump.dump_dcache_statusdump.dump_buffer_pingpong_statusdump.dump_reg_statusdump.dump_switchdump.dump_scalar_switchdump.dump_l0a_rd_statusdump.dump_l0a_wr_statusdump.dump_l0b_rd_statusdump.dump_l0b_wr_statusdump.dump_l0c_rd_statusdump.dump_l0c_wr_statusdump.dump_ub_rd_statusdump.dump_ub_wr_statusdump.dump_l1_rd_statusdump.dump_l1_wr_status[ERROR]: Failed to read in options from spec file. Exception: %s davinci_vec_core.spec[%s] %s:%d %s Core=%u, core_type=%u, spec_file=%s exec#file#[%s] %s:%d %s set config failed [%s] %s:%d %s Core config file not found. [%s] %s:%d %s Failed to parse config file %s: %s! DVC_PLATFORM_LINUXDVC_PLATFORM_ESL@ -+   BasicCrossBarBasicCrossBar13BasicCrossBarSt23_Sp_counted_ptr_inplaceI13WritePortMaskSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEbasic_cross_bar.cc[%s] %s:%d %s mem alloc size out of range 15BasicCrossBarGP@ -+   basic_cross_bar_group.ccvector::_M_default_append@ -+   17BasicL0ABCrossBarbasic_l0_ab_cross_bar.ccvector::_M_fill_insertL0_AB_BufferL0_A_BufferL0_A_WINO_BufferL0_B_BufferL0_B_WINO_BufferL0_A_CrossBarL0_B_CrossBarL0_B_WINO_CrossBar{0:s} get_frac_index: error! BUFFER WRAP AROUNDset_buffer_w_req : tick: {0:d}, addr:0x{1:x}, size:0x{2:x}, start_index:{3:d}, end_index:{4:d}, port: {5:d}, buffer:{6:s}.set_buffer_r_req : tick: {0:d}, addr:0x{1:x}, size:0x{2:x}, start_index:{3:d}, end_index:{4:d}, port: {5:d}, buffer:{6:s}.set_req_complete : tick: {0:d}, addr:0x{1:x}, size:0x{2:x}, port: {3:d}, name:{4:s}.@ -+   16BasicL0CCrossBarbasic_l0_c_cross_bar.ccL0_C_BufferBasic_BufferL0_C_Crossbarvec_r_request : tick: {0:d}, addr:{1:d}, size:{2:d}, port:{3:d}, request_id:{4:d}.update_cube_rd_bank_mask_mini : tick: {0:d}, cube_bank_line_mask:{1:x}, list_size: 0x{2:x}.set_vec_r_request : tick: {0:d}, addr:{1:d}, start_index:{2:d}, end_index:{3:d}.set_cube_w_request : tick: {0:d}, addr:{1:d}, start_index:{2:d}, end_index:{3:d}.set_vec_r_complete : tick: {0:d}, addr:{1:d}, size:{2:d}.run_req_type : tick: {0:d}, cube_bank_line_mask:{1:x}, vec_bank_line_mask:{2:x}, bank_conflicit:{3:x}.set_cube_w_complete : tick: {0:d}, addr:{1:d}, size:{2:d}.15BasicL1CrossBar@ BasicL1CrossBar-+   basic_l1_cross_bar.ccL1_BUFFERL1Buffervector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)error req numERROR PORT: {0:d}18BasicSystemControlwrite@ -+   basic_system_control.ccaddr 2 spr error12BIUBasicPort14BIUSlaveRDPort15BIUMasterRDPort14BIUSlaveWRPort15BIUMasterWRPortN3fmt2v96detail9formatbufISt15basic_streambufIcSt11char_traitsIcEEEE@ -+   ca_biu_element.cctick: {0:d}. update_req_info addr: {1:x}, size: {2:x}, scache_ctrl_bit: {3:d}tick: {0:d}. {1:s}{2:d} axi_send_req 0x{3:x}.tick: {0:d}. {1:s}: {2:d} send_req 0x{3:x}tick: {0:d}. {1:s}{2:d} chi_send_req 0x{3:x}.tick: {0:d}. {1:s}{2:d} complete_req 0x{3:x}.tick: {0:d}. {1:s}{2:d} axi send_data 0x{3:x}.tick: {0:d}. {1:s}{2:d} chi_get_req 0x{3:x}.tick: {0:d}. {1:s}: {2:d} get_req 0x{3:x}tick: {0:d}. {1:s}{2:d} send_req 0x{3:x}.tick: {0:d}. {1:s}{2:d} send_data 0x{3:x}.tick: {0:d}. {1:s}{2:d} axi_get_data 0x{3:x}.tick: {0:d}. {1:s}{2:d} axi up_data_to_slv 0x{3:x} to slv {4:x}.tick: {0:d}. {1:s}{2:d} req_rsp_to_slv 0x{3:x} to slv {4:x}.tick: {0:d}. {1:s}{2:d} axi update_data_rsp 0x{3:x} to slv {4:x}.tick: {0:d}. {1:s}{2:d} axi data_rsp 0x{3:x}.tick: {0:d}. {1:s}{2:d} chi_req_rsp 0x{3:x}.tick: {0:d}. {1:s}: {2:d} complete_req 0x{3:x}6CaCoreSt23_Sp_counted_ptr_inplaceI7BarSyncSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ build            @                           @                                                       9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+   ca_core.ccscalar_isq_arbitervector_isq_arbitervector_v2_isq_arbitercube_isq_arbitermte1_isq_arbitermte2_isq_arbitermte3_isq_arbitermte4_isq_arbitermte5_isq_arbiterL0_A_WINO_CrossBar[%s] %s:%d %s new biu failed 14CAL0UBCrossBarSt23_Sp_counted_ptr_inplaceI7UB_PARASaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5UBUopSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15UBAccessRequestSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEreadwriteinitinit@ readwriteCAL0UBCrossBarCAL0UBCrossBar                               9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+   gen_scalar_uopgen_1_vector_mte_uopreadreadscatterReadscatterReadwritewritescatterWritescatterWritescatterWriteByteMaskinit[%s] %s:%d %s ubpara is nullptr [%s] %s:%d %s vector max scatter num_ is zero [%s] %s:%d %s mem alloc size out of range! [%s] %s:%d %s memset_s failed [%s] %s:%d %s memcpy failed, errno_t: %d. ca_l0_ub_cross_bar.cc[%s] %s:%d %s mask size is zero [%s] %s:%d %s malloc failed memcpy_s error !L0_UB_Buffertick: {0:d}, buf start addr: 0x{1:x}, address: 0x{2:x}tick: {0:d}, gen_uop req_id: {1:d}, uop_id: {2:d}, bank_id: {3:d}, bank_grp: {4:d}, port_id: {5:d}, addr: {6:x}, 32B_addr: {7:x}.tick: {0:d}, port: {1:x}, delay: {2:d}.tick: {0:d}, check_vec_perf_dble,port_id: {1:d}, address: 0x{2:x}.tick: {0:d}, directWrite port: {1:d}, size: 0x{2:x}, addr: 0x{3:x}tick: {0:d}, directRead port: {1:d}, size: 0x{2:x}, addr: 0x{3:x}tick: {0:d}, generate_req_id: {1:x}[%s] %s:%d %s UB Access Request init failed tick: {2:d}, MTE_{0:s}_BANK_CONFLICT at bank: 0x{1:x}tick: {1:d}, SCALAR_RD_BANK_CONFLICT at Address: 0x{0:x}tick: {1:d}, done_req_id: {0:x}tick: {6:d}, PROCESS_DATA req_id: {5:x}, at port: 0x{0:x}, address: 0x{1:x}, size: 0x{2:x}, access_type: {3:s}, scatter_number: 0x{4:x}tick: {0:d}, vec_part_info_not_match req_id: {1:d}, uop_id: {2:d}, bank_id: {3:d}, port_id: {4:d}, part_id: {5:x}.tick: {2:d}, VECTOR_{0:s}_BANK_CONFLICT at bank: {1:d}tick: {1:d}, SCALAR_WR_BANK_CONFLICT at Address: 0x{0:x}tick: {0:d}, check_wr_latency start_addr: {1:x}, 32B_addr: {2:x},size: {3:d}, bank_grp: {4:d}, port_grp: {5:d}.tick: {0:d}, blk_grp: {1:d}, bank_cf_lt: {2:d}.tick: {0:d}, wr_latency: {1:d}.tick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}. ERR:line_size_aligned tick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}. ERR:is_same_line_type tick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}. ERR:is_addr_continstick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}. ERR:is_line_size_alignedtick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}.8BasicCCUSt23_Sp_counted_ptr_inplaceI11BasicBufferSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ build            @                           @                        -+   basic_ccu.ccSCALAR_BUFFER10CaDispatch@ isWritePortConflict            @                           @                        -+   rsI1HzdCheckrsI0HzdCheckca_dispatch.ccDEBUG[%s] %s:%d %s Tick: %d, %s, Write Reg X%d: operation time %d. tick {0:d}: isa: {1:s} ST_UB_OUTSTANDING_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} scalar wait_flag stalling LD_ST Instruction. pc: {2:x}tick {0:d}: isa: {1:s} LD4_RETURN_BUFFER_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} Scalar_Buffer_Pipe_Resources_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} Scalar_Buffer_Single_Port_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} LD_UB_OUTSTANDING_Hazard. pc: {2:x}[%s] %s:%d %s Tick: %d, Load after Store Hazard. [%s] %s:%d %s Tick: %d, Store after Load Hazard. tick {0:d}: isa: {1:s} dCache_before_DCCI_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} dCache_after_DCCI_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} dCache_resource_Hazard - Dcache Back Pressue. pc: {2:x}tick {0:d}: isa: {1:s} Scalar_Div_Resources_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} write_port_conflict. pc: {2:x}[%s] %s:%d %s Tick: %d, LdSt Resources conflict. 11CaSequencerSt23_Sp_counted_ptr_inplaceI10instBinarySaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@             @                           @                        -+   get_predict_pcput_icache_data_to_instr_bufinitca_sequencer.cctick: {0:d}, set branch xn: 0x{1:x}[%s] %s:%d %s fetch_size_ is smaller than fetch_start_position * ISA_MAX_BYTES [%s] %s:%d %s MakeShared alloc failed [%s] %s:%d %s memcpy failed [%s] %s:%d %s inst binary initialize failed tick: {0:d}, fill addr: 0x{1:x} to IB: {2:d}WAITING_FOR_ICACHE_INSTR11PrfMapTable14ReserveStationSt23_Sp_counted_ptr_inplaceI10depth_wiseSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEset_occupyassign_physical_index@ push-+   physical_reg.cc[%s] %s:%d %s Physical register %d is already occupied [%s] %s:%d %s No more physical registers available tick: {0:d}, write physical gpr reg: {1:d}, value: {2:x}12EventQueue32checkEventsEmpty@ -+   event_queue32.cc[%s] %s:%d %s unmatched setevent: src_pipe: %s, dest_pipe: %s, event_id: %d. 5ldvad10vtranspose16vmovemask_xd_cmp16vmovemask_cmp_xn12rpn_cor_diag11SubDispatchSt23_Sp_counted_ptr_inplaceI10PhyRegFileSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11PrfMapTableSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14ReserveStationSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEget_mte_issq_id @ getGPRWriteCyclegetGPRReadCyclecheckBarAllBeforeMovXdStatusgetScalarGPRWriteCyclegetFlowCtrlGPRWriteCyclegetScalarGPRReadCyclegetVectorGPRCyclegetCubeGPRReadCyclegetLsuGPRReadCyclegetFlowCtrlGPRReadCycleSubDispatch            @                           @                        -+   flowctrlSetEventResHzdCheckscalarResHzdCheckincCallStackCountercheckIllegalInstrvec_instr_set_q_idtick: {2:d} get_dst_reg_map: {3:s} x{0:d} <--> p{1:d}tick: {2:d} get_src_reg_map inc p count: {3:s} x{0:d} <--> p{1:d}tick: {2:d} get_src_reg_map: {3:s} x{0:d} <--> p{1:d}tick: {1:d} src_reg_value dec p count: {2:s} p{0:d}tick: {1:d} src_reg_value: {2:s} p{0:d}sub_dispatch.cc[%s] %s:%d %s DMAC_MOV_SRC_TO_DST. src L0C buffer is not a DMA instruction. This should be implemented in vector. [%s] %s:%d %s DMAC_MOV_SRC_TO_DST. src_ID is invalid. [%s] %s:%d %s SET_2D. dst_ID is invalid. [%s] %s:%d %s Invalid DMA inst name. FLOWCTRLunknown instr type:[%s] %s:%d %s Invalid Opcode Type. WARNING[%s] %s:%d %s it's suggested to add bar.all before mov xd, status instr. [%s] %s:%d %s Invalid OP1. [%s] %s:%d %s Invalid OP. VEC DUAL ISSQUE ARBITERMTE1 ISSUEMTE2 ISSUEMTE3 ISSUEMTE4 ISSUEMTE5 ISSUECUBE ISSUEVEC ISSUEVEC0 ISSUEVEC1 ISSUEVEC0 IB ISSUEVEC1 IB ISSUESCALAR ISSUEtick {0:d}: isa: {1:s} DMAC_L1_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} DMAC_L2_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} DMAC_L3_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} DMAC_L4_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} DMAC_L5_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} SCALAR_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} scalar_issue_queue_at_barrier. pc: {2:x}tick {0:d}: isa: {1:s} VECTOR_EVENT_QUEUE0_FULL. pc: {2:x}tick {0:d}: isa: {1:s} VECTOR_EVENT_QUEUE1_FULL. pc: {2:x}tick {0:d}: isa: {1:s} CUBE_EVENT_QUEUE_FULL. pc: {2:x}[%s] %s:%d %s ALL_PIPE should exist only in FLOWCTR_BAR unknown flowctrl pipetick {0:d}: isa: {1:s} DMAC_L1_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} DMAC_L2_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} DMAC_L3_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} DMAC_L4_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} DMAC_L5_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} VECTOR_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} CUBE_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: d1 scalar bar wait: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte1 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte2 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte3 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte4 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte5 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to vector issque 0 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to vector issque 1 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to cube instr: {1:s}, pc: {2:x}.tick {0:d}: discard mte1 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte1 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard mte2 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte2 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard mte3 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte3 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard mte4 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte4 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard mte5 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte5 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard vector issque 0 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: vector issque 0 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard vector issque 1 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: vector issque 1 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard cube barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: cube barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: push scalar ub I1 isa: {1:s} to queue, pc: {2:x}.tick {0:d}: push scalar ub I1 isa: {1:s} to queue hazard, pc: {2:x}.tick {0:d}: push scalar buffer I1 isa: {1:s} to queue, pc: {2:x}.tick {0:d}: push scalar buffer I1 isa: {1:s} to queue hazard, pc: {2:x}.tick {0:d}: push scalar ddr isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push scalar ddr isa: {1:s} to I1 Hazard, pc: {2:x}.tick {0:d}: push scalar ddr isa: {1:s} to I1 src reg Hazard, pc: {2:x}.tick {0:d}: d1 scalar exe scalar_set: {1:s}, pc: {2:x}.error execute.tick {0:d}: isa: {1:s} SCALAR_ISSUE_QUEUE_FULL. pc: {2:x}[%s] %s:%d %s Tick: %d, %s, SCALAR_ISSUE_QUEUE%d_FULL. tick {0:d}: d1 jumpc exe hazard: {1:s}.tick {0:d}: d1 jumpcmp exe hazard: {1:s}.unknown flowctrl opcode nametick {0:d}: push isa: {1:s} mte_mov_xd_spr_barrier. tick {0:d}: push isa: {1:s} scalar_mov_xd_spr_barrier. tick {0:d}: d1 condition_flag rs_hazard: {1:s}.[%s] %s:%d %s call stack overflow, nested call number %d is larger than threshold: %d. CCU: {0:s}: ccu_call_depth_ovrflw. Nested calls more than T+1. pc: {1:x}CCU: {0:s}: ccu_addr_err. Scalar ld/st addr overflow/unalign error. pc: {1:x}CCU: {0:s}: ccu_illegal_instr. Instruction Binary is wrong: pc: {1:x}, binary: {2:x}.[%s] %s:%d %s Do not support writing spr: %d. Instr: pc: %lx, binary: %x. [%s] %s:%d %s Do not support reading spr: %d. Instr: pc: %lx, binary: %x. tick {0:d}: d1 push scalar wait_flag isa to I0 rs hazard, pc: {1:x}.tick {0:d}: push scalar temp ldst isa: {1:s} to sbuf I1, pc: {2:x}.tick {0:d}: push scalar temp ldst isa: {1:s} to ub I1, pc: {2:x}.tick {0:d}: push scalar rs isa: {1:s} to I1, to scalar {2:d}, pc: {3:x}.tick {0:d}: push scalar rs isa: {1:s} to I1 Hazard, to scalar:{2:d}, pc: {3:x}. Condition: is_all_src_reg_valid(): {4:d}, canDispatchRsI0(*it, i): {5:d}.tick {0:d}: push scalar ldst isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push scalar ldst isa: {1:s} to I1 Hazard, pc: {2:x}. ub_I1_.size: {3:d}, sbuf_I1_.size: {4:d}tick {0:d}: push mte1 isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push mte1 isa: {1:s} to I1 hazard, pc: {2:x}. all_reg_valid: {3:d}tick {0:d}: Update register: Buf_type_:0x{1:x} P-reg:0x{2:x} P-value:0x{3:x} reg_port_use:0x{4:x} reg_value_map_.size:0x{5:x} execute_d1 tick {0:d}: ISA: {1:s}, condition_stall_flag_ hazard.SCALARtick {0:d}: mov_special_xn isa: {1:s} src reg hazard, pc: {2:x}.tick {0:d}: d1 push scalar wait_flag isa to I0 rs: {1:s}, pc: {2:x}.tick {0:d}: d1 discard isa when push to I0 rs: {1:s}, pc: {2:x}. Not support bar.s instr !!!tick {0:d}: d1 push isa to I0 rs: {1:s}, pc: {2:x}.[%s] %s:%d %s vpipe_value: %d. num_vec_isq_: %d. pc: %lx, binary: %x. tick {0:d}: rs busy, d1 drop isa : {1:s}, pc: {2:x}.tick {0:d}: d1 rs_hazard: {1:s}.execute_d1 tick {0:d}: ISA: {1:s}, spr_single_issue_flag_ hazard.execute_d1 tick {0:d}: ISA: {1:s} type: {2:x}. pc: {3:x} tick {0:d}: d1 hazard, no more physical register to allocate. ISA: {1:s} pc: {2:x}.tick {0:d}: d1 flowctrl src_hazard: {1:s}.tick {0:d}, {1:s} QUEUE FULL, isa: {2:s}, pc: {3:x}.tick {0:d}: push mte5 isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push mte5 isa: {1:s} to I1 hazard, pc: {2:x}. all_reg_valid: {3:d}tick {0:d}: push mte4 isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push mte4 isa: {1:s} to I1 hazard, pc: {2:x}. all_reg_valid: {3:d}tick {0:d}: push mte2 isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push mte2 isa: {1:s} to I1 hazard, pc: {2:x}. all_reg_valid: {3:d}tick {0:d}: push vector isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push vector isa: {1:s} to I1 hazard, pc: {2:x}. all_reg_valid: {3:d}tick {0:d}: push cube isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push cube isa: {1:s} to I1 hazard, pc: {2:x}. all_reg_valid: {3:d}tick {0:d}: push mte3 isa: {1:s} to I1, pc: {2:x}.tick {0:d}: push mte3 isa: {1:s} to I1 hazard, pc: {2:x}. all_reg_valid: {3:d}tick {0:d}: push scalar ddr I1 isa: {1:s} to queue, pc: {2:x}.tick {0:d}: push scalar I1 isa: {1:s} to queue, to scalar {2:d}, pc: {3:x}.tick {0:d}: push cube isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte4 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte2 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte1 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte5 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte3 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push vector isa: {1:s} to queue {2:d}, pc: {3:x}. event_id: {4:d}12SubSequencerSt23_Sp_counted_ptr_inplaceI3ISASaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11error_instrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEstart@ fillinitSubSequencer            @                           @                        -+   fetchpass2dispatchsub_sequencer.ccthis->icache_ is nullthis->biu_ is null[%s] %s:%d %s req is nullptr tick: {0:d}, clear_ifu_read_req_queuetick: {0:d}, set_is_branchtick: {0:d}, clear_is_branchtick: {0:d}, fetch addr: 0x{1:x}, buf_ptr: 0x{2:x}CCU: {0:s}: ccu_cnt_err. loopend detected without loop instr. pc: {1:x}CCU: {0:s}: ccu_loop_cnt_error. loop count == 0 when execute loopend instruction. pc: {1:x}scalar_psq: Instruction Address 0x. pass 2 psq2dispath_queue.parseConfigFilesetupIndependentOptionsdvcConfig.cc[%s] %s:%d %s create config failed, file name is %s [ERROR]: Failed to parse config file %s! %s [%s] %s:%d %s parseConfigFile failed, file name is %s [%s] %s:%d %s readinOptionsFromCfg failed 9CubeIssueSt23_Sp_counted_ptr_inplaceI7CubeISASaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ -+   popcube_issque.cc8LsuIssue@ -+   lsu_issque.ccLSU ISSUE11ScalarIssueSt23_Sp_counted_ptr_inplaceI9ScalarISASaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ -+   popscalar_issque.cc16VecIssQueArbiter@ -+   vector_arbiter.cctick: {0:d}, vector isq_ib_: {1:d}, front_isq_counter_: {2:d} [{0:08d}]({1:s}): vec arb pop instr_id: {2:d}, isa: {3:s}, pc: {4:x}, from vec queue 0[{0:08d}]({1:s}): vec arb pop instr_id: {2:d}, isa: {3:s}, pc: {4:x}, from vec queue 1[{0:08d}]({1:s}): get_next_instr, isa: {2:s}, pc: {3:x}[{0:08d}]({1:s}): retire instr_id: {2:d}, thread_id: {3:d}[{0:08d}]({1:s}): get_instr_after_next instr_id: {2:d}, isa: {3:s}, pc: {4:x}11VectorIssueSt23_Sp_counted_ptr_inplaceI9VectorISASaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ -+   popget_isavector_issque.ccVECTOR ISSUE17VirtualBusPortTbsaicpu_kickstartdirectReaddirectWritebus_memory_dup@ initinitinit            @                           @                                                       9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+   virtual_bus_slave_port.cc[%s] %s:%d %s AICPU core %ld will run %ld cycle [%s] %s:%d %s AIC or AIV request at address 0x%lx [%s] %s:%d %s AICPU request at address 0x%lx [%s] %s:%d %s Write value to hwts0 register 0x%lx, value 0x%lx [%s] %s:%d %s Write value to hwts0 register 0x%lx, incorrect size %d [%s] %s:%d %s Write value to hwts1 register 0x%lx, value 0x%lx [%s] %s:%d %s Write value to hwts1 register 0x%lx, incorrect size %d bus write: smmu_master_id: 0x smmu_flag: 0xbus read: smmu_master_id: 0x8AsyncRAMSt23_Sp_counted_ptr_inplaceI6SC_DDRSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEdirect_readdirect_writeinit_with_seedinit_without_seedreadwritetickasync_ram.cc[%s] %s:%d %s read error DDR latency random seed = [%s] %s:%d %s write error 7BarSync@ -+   bar_sync.cc10EventQueue@ -+   event_queue.cc17IssueQueueArbiter@ -+   isq_arbiter.cc[{0:08d}]({1:s}): emplace instr_id: {2:d}, isq_id: {3:d}[{0:08d}]({1:s}): retire instr_id: {2:d}, isq_id: {3:d}10IssueQueue@ resume-+   issue_queue.ccVECTORCUBEL1L2L3ALLL4L5VECTOR_V2TypeVECTOR Repeat0MTE1 Repeat0MTE2 Repeat0MTE3 Repeat0MTE4 Repeat0MTE5 Repeat0CUBE Repeat0SCALAR Repeat0undefine pipe Repeat0[%s] %s:%d %s ERROR: issue_queue.cc: wait_event_inst == nullptr tick: {0:d} isa: {1:s}, pc: {2:x} has vector issque single-port ram hazardtick: {2:d} issq trigger l0c_set_flag {0:s} l0c_opt_id: {1:d} triggerPipe: {3:s}tick: {3:d} issq_exe_set_flag {0:s} l0c_opt_front_id: {1:d} triggerPipe: {2:s}, reorder_q_id: {3:d}tick: {0:d} isa: {1:s}, pc: {2:x} has update set flag table hazardN13ascend_spdlog5sinks16stdout_sink_baseINS_7details17console_nullmutexEEEN13ascend_spdlog5sinks11stdout_sinkINS_7details17console_nullmutexEEEN13ascend_spdlog5sinks9base_sinkINS_7details10null_mutexEEEN13ascend_spdlog5sinks15basic_file_sinkINS_7details10null_mutexEEESt23_Sp_counted_ptr_inplaceIN13ascend_spdlog5sinks11stdout_sinkINS0_7details17console_nullmutexEEESaIS5_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN13ascend_spdlog5sinks15basic_file_sinkINS0_7details10null_mutexEEESaIS5_ELN9__gnu_cxx12_Lock_policyE2EEerror : @ -+   /initial_aicore_logabFailed opening file for writingFailed writing to file Failed flush to file {}{}log.ccSCALAR_PIPEVECTOR_PIPECUBE_PIPEDMAC_L1_PIPEDMAC_L2_PIPEDMAC_L3_PIPEUNKNOWNAddress {0:08x} = [{1:02x}]Address {0:08x} = [{1:04x}]memcpy_s error!Address {0:08x} = [{1:08x}] Address {2:08x} = [{3:08x}] Address {4:08x} = [{5:08x}] Address {6:08x} = [{7:08x}]Address {0:08x} = [{1:08x}] Address {2:08x} = [{3:08x}] Address {4:08x} = [{5:08x}]Address {0:08x} = [{1:08x}] Address {2:08x} = [{3:08x}]Address {0:08x} = [{1:08x}][{0:08d}](PC: 0x{1:08x})@{2:s} : (Binary: 0x{3:08x}) {4:s}/core_.dump.1.dump.2.dump[%l] %v16MasterAccessPort@ -+   master_access_port.cc3RAMclearreadwriteiniValRAMiniValRAMram.cc[%s] %s:%d %s memset_s error %d [%s] %s:%d %s memcpy_s error %d [%s] %s:%d %s read address: 0x%lx is larger than ddr size: 0x%lx [%s] %s:%d %s write address: 0x%lx is larger than ddr size: 0x%lx read_in_pagewrite_in_page//------------------------------------------------------------------ N/Asc_buf.cc[%s] %s:%d %s addr is not same page of addr end 7CubeISA4mmad19cube_mov_special_xn15depth_wise_convdecodedecodedecodeexecute@ -+   cube_isa.cc[%s] %s:%d %s Xn_val = %lx address align error! [%s] %s:%d %s Xm_val = %lx address align error! [%s] %s:%d %s Xd_val = %lx address align error! [%s] %s:%d %s special errors [%s] %s:%d %s xn errors [%s] %s:%d %s special encode errors [%s] %s:%d %s instruction execute errors %s(type:%d,xd:0x%x,xn:0x%x,xm:0x%x,xt:0x%x,M:%d,K:%d,N:%d,xd_val:0x%lx, xn_val:0x%lx,xm_val:0x%lx,xt_val:0x%lx, c_init_ctrl:0x%x, sparsity:0x%x, w_offset:0x%x, fm_offset:0x%x, small_K:0x%x, sMask_addr:0x%x, winograd:0x%x)instr ID is: %d%s(%s= 0x%lx, x[%ld]= 0x%lx)instr ID is: %d%s(type:%d,xd:0x%x,xn:0x%x,xm:0x%x,xt:0x%x,H:%d,W:%d,xd_val:0x%lx,xn_val:0x%lx,xm_val:0x%lx,xt_val:0x%lx, sMask_addr:%d, fm_offset:%d, w_offset:%d, padding_ctrl:%d, h:%d)instr ID is: %dmmadcube_mov_special_xndepth_wise_conv11FlowCtrlISA4jump5jumpc5jumpr7preload4call7bar_set8bar_wait5callr4adrp13end_execution3ret4trap4loop7endloop7barrier9set_event10wait_event3nop10break_inst8nop_pipe11error_instr7jumpcmpdecodedecodeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserialize@ decode-+   flowctrl_isa.cc[%s] %s:%d %s set_event data type is wrong. %sx (dest_address:0x%lx)[%s] %s:%d %s sprintf_s failed, return value: %d. %si(dest_address:0x%lx)%s (dest_address:0x%lx)%sx (dest_address:0x%lx, conditional_flag:%lx)%si (dest_address:0x%lx, conditional_flag:%lx)%sx (preload address: 0x%lx)%sx (event_id:0x%lx)%si(event_id:0x%lx)%s%s (loop_cnt: %ld)%s (loop count: %ld)%s(pipe_type: %s)%s(pipe_type: %s, tigger_pipe: %s, event_id: %d)%s (dest_address:0x%lx, conditional_flag:%lx)ERROR: data type is wrong.ERROR: loop date_type_ is undefined.ERROR: jump data type is wrong.ERROR: call data type is wrong.ERROR: jumpc data type is wrong.jumpjumprjumpcpreloadcallbar_setbar_waitcallradrpend_executionrettraploopendloopbarrierset_eventwait_eventjumpcmpnopbreak_instnop_pipeerror_instr[%s] %s:%d %s cmp_dtype errors [%s] %s:%d %s cmp_optype errors [%s] %s:%d %s imm10 errors [%s] %s:%d %s imm5 errors [%s] %s:%d %s xn_4_1 errors [%s] %s:%d %s xn_0_0 errors [%s] %s:%d %s xd errors [%s] %s:%d %s xm errors [%s] %s:%d %s jump_type errors [%s] %s:%d %s cmp_type errors ERROR: jumpcmp data type is wrong.* "$((  extractget_scalar_opcode_type@ -+   get_vector_opcode_typeget_dmac_opcode_typeinitializeSt23enable_shared_from_thisI3ISAE3ISA6vmovev3vci4vadd8vadd_vad12vaddreluconv8vaddrelu4vsub8vsub_vad12vsubreluconv8vsubrelu4vmax8vmax_vad4vmin8vmin_vad4vmul8vmul_vad4vmla8vmla_vad5vmadd9vmadd_vad6vlrelu9vmaddrelu13vmaddrelu_vad4vexp8vexp_vad6vrsqrt10vrsqrt_vad5vsqrt9vsqrt_vad5vrelu9vrelu_vad4vrec8vrec_vad3vln8vrln_vad4vabs8vabs_vad4vdiv8vdiv_vad5vcadd5vcmax5vcmin6vcgmax6vcgmin6vcgadd13vncwhconv_vad8v4dtrans5vaxpy9vaxpy_vad5vadds9vadds_vad5vmuls9vmuls_vad5vmaxs9vmaxs_vad5vmins9vmins_vad4vcmp8vcmp_vad5vcmpv4vsel8vsel_vad5vconv9vconv_vad8vmov_vad6vcpadd4vand3vor4vnot11vadddeqrelu8vmulconv12vmulconv_vad5vrpac4viou5vaadd5vbs164vms48vextract8vcontact8vmergech7rpn_cor8vscsplit8vscmerge9vcshuffle8vscatter8vpadding7vgather4vshr4vshl6vcmpvs7vreduce3vdp3vbi4vcbdSt23_Sp_counted_ptr_inplaceI17copy_bufC2unifiedSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20copy_unifBuf2unifBufSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17copy_unifBuf2bufCSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12brc_ub_2_dstSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7col2imgSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vexp_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10vrsqrt_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vrelu_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vrec_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vrln_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vabs_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vsqrt_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vconv_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vadd_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vsub_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vmax_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vmin_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vmul_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vmla_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vdiv_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vmadd_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13vmaddrelu_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vaxpy_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vadds_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vmuls_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vmaxs_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vmins_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vcmp_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vsel_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12l0c_lock_setSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16l0c_lock_releaseSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12vmulconv_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6movevaSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vscmergeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vscsplitSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vcshuffleSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7vgatherSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vpaddingSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6vcmpvsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7vreduceSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3vdpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3vbiSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vshrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vshlSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vscatterSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8movemaskSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5ldvadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vcbdSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6vmovevSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3vciSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vexpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6vrsqrtSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vreluSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vrecSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3vlnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vabsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vcaddSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vcmaxSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vcminSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6vcgmaxSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6vcgminSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6vcgaddSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13vncwhconv_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vmov_vadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6vcpaddSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vnotSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vrpacSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vbs16SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vms4SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vextractSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vcontactSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vmergechSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12rpn_cor_diagSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10vtransposeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8v4dtransSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vsqrtSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vconvSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vaddSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vsubSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vmaxSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vminSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vmulSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vmlaSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vdivSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vmaddSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6vlreluSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9vmaddreluSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vaxpySaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vaddsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vmulsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vmaxsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vminsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vcmpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vcmpvSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3vorSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vandSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4vselSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4viouSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5vaaddSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7rpn_corSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16vmovemask_xd_cmpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16vmovemask_cmp_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21vector_mov_special_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11vadddeqreluSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vmulconvSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vaddreluSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8vsubreluSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12vaddreluconvSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12vsubreluconvSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4mmadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15depth_wise_convSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI19cube_mov_special_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18load_src_to_dst_2dSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10set_dst_2dSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21load_out_to_dst_unzipSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21decompress_out_to_dstSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20set_rawheader_to_outSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17decompress_headerSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11unzip_indexSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20load_out_to_l1_imageSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18compress_ub_to_outSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI23load_l1_to_l0b_winogradSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI23load_l1_to_l0a_winogradSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16load_l1_to_l0_3dSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14mov_src_to_dstSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18mte_mov_special_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18mte_mov_xd_specialSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18load_src_to_l0b_b2SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17load_src_to_smaskSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13brc_l1_to_l0cSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_addSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_subSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_mulSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_maddSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_absSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_divSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_modSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_sqrtSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_negSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_maxSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_minSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_cmpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_cmpnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_selSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_andSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9scalar_orSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_xorSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_notSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_shlSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_shrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_clzSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12scalar_sbcntSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_sffSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_sflbitsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_convSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_sbitsetSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_mov_xd_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20scalar_mov_xd_imme16SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21scalar_movk_xd_imme16SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21scalar_mov_xd_specialSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21scalar_mov_special_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9scalar_ldSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9scalar_stSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_ld4SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_st4SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_signextSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_zeroextSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13scalar_ld_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13scalar_st_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_ld4_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_st4_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13scalar_ld_ddrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13scalar_st_ddrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17scalar_dc_preloadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13scalar_insertSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17scalar_insert_extSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_add_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_mul_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_sub_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI23scalar_dc_preload_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_ldpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_stpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_cmp_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17scalar_ld_ddr_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17scalar_st_ddr_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_stiSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_sti_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12scalar_movx8SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20scalar_mov_spr_imm16SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_dcciSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4jumpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5jumpcSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5jumprSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7preloadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4callSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7bar_setSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8bar_waitSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5callrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4adrpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13end_executionSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3retSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4trapSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4loopSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7endloopSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7barrierSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9set_eventSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10wait_eventSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3nopSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8nop_pipeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7jumpcmpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEvrsqrt_vadvtransposevadddeqrelurpn_cor_diagvaddreluconvvmulconv_vadvsubreluconvvmaddrelu_vadvncwhconv_vadvmovemask_cmp_xnvmovemask_xd_cmpvbivcivdpvlnvorvabsvaddvandvcbdvcmpvdivvexpviouvmaxvminvmlavms4vmulvnotvrecvselvshlvshrvsubldvadvaaddvaddsvaxpyvbs16vcaddvcmaxvcminvcmpvvconvvmaddvmaxsvminsvmulsvreluvrpacvsqrtvcgaddvcgmaxvcgminvcmpvsvcpaddvlreluvmovevvrsqrtrpn_corvgathervreducev4dtransvabs_vadvadd_vadvaddreluvcmp_vadvcontactvdiv_vadvexp_vadvextractvmax_vadvmergechvmin_vadvmla_vadvmov_vadvmul_vadvmulconvvpaddingvrec_vadvrln_vadvscattervscmergevscsplitvsel_vadvsub_vadvsubreluvadds_vadvaxpy_vadvconv_vadvcshufflevmadd_vadvmaddreluvmaxs_vadvmins_vadvmuls_vadvrelu_vadvsqrt_vadisa.cc[%s] %s:%d %s memcpy_s error %d. [%s] %s:%d %s not supporting this op1 = 0x%x. [%s] %s:%d %s not supporting this encoding: %x, op1 = 0x%x. [%s] %s:%d %s invalid instruction type. UNKNOWN_REGISTER6MteISA18mte_mov_special_xn18mte_mov_xd_special18load_src_to_dst_2d16load_l1_to_l0_3d14mov_src_to_dst20load_out_to_l1_image18compress_ub_to_out21decompress_out_to_dst20set_rawheader_to_out17decompress_header21load_out_to_dst_unzip11unzip_index10set_dst_2d18load_src_to_l0b_b217load_src_to_smask23load_l1_to_l0b_winograd23load_l1_to_l0a_winograd10depth_wise13brc_l1_to_l0cdecodedecodeexecuteexecuteserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserialize@             @                           @                        -+   mte_isa.cc%s( x[%ld]= 0x%lx, %s= 0x%lx,)%s(%s= 0x%lx, x[%ld]= 0x%lx)load_l1_to_l0a_2d%s(xd:%d, xn:%d, xm:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, srcIDValue:%d, dTypeValue:%d, destIDValue:%d, transposeValue:%d)load_out_to_l0a_2dload_ub_to_l0a_2dload_l1_to_l0b_2dload_out_to_l0b_2dload_ub_to_l0b_2dload_out_to_l1_2dload_src_to_dst_2dmov_ub_to_ub%s(xd:%d, xn:%d, xm:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, srcIDValue:%d, destIDValue:%d, reluValue:%d, padValue:%d)mov_out_to_ubmov_l1_to_ubmov_ub_to_l1mov_out_to_l1mov_ub_to_outmov_l1_to_l0c16mov_l1_to_l0c32mov_l1_to_l0c16vmov_l1_to_l0c32vmov_l1_to_l0c32scmov_src_to_dstset_rawheader_to_out%s(xd:%d, xm:%d, xdValue:0x%lx, xmValue:0x%lx)unzip_index%s(xn:%d, xm:%d, xnValue:0x%lx, xmValue:0x%lx)decompress_headerload_src_to_l0b_b2%s(xd:%d, xn:%d, xm:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx)load_out_to_l1_image%s(xd:%d, xs:%d, xt:%d, xdValue:0x%lx, xsValue:0x%lx, xtValue:0x%lx, dTypeValue:%d)load_l1_to_l0b_winograd%s(xd:%d, xn:%d, xm:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, dTypeValue:%d)brc_l1_to_l0c%s(xd:%d, xn:%d, xm:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, reluValue:%d, destIDValue:%d)%s(xd:%d, xn:%d, xm:%d, xt:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, xtValue:0x%lx, dTypeValue:%d)compress_ub_to_outload_l1_to_l0a_winogradload_src_to_smaskload_ub_to_smask%s(xd:%d, xn:%d, xt:%d, xdValue:0x%lx, xnValue:0x%lx, xtValue:0x%lx, srcIDValue:%d)decompress_out_to_ub%s(xd:%d, xn:%d, xm:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, destIDValue:%d)decompress_out_to_l1decompress_out_to_dstload_out_to_l0a_unzipload_out_to_l0b_unzipload_out_to_l1_unzip%s(xd:%d, xn:%d, xdValue:0x%lx, xnValue:0x%lx, destIDValue:%d)set_l0a_2d%s(xd:%d, xm:%d, xdValue:0x%lx, xmValue:0x%lx, destIDValue:%d)set_l0b_2dset_l1_2dset_dst_2dload_l1_to_l0a_3dload_l1_to_l0b_3dload_l1_to_ub_3dload_l1_to_dst_3d%s(xd:%d, xn:%d, xm:%d, xt:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, xtValue:0x%lx, sizeValue:%d, dTypeValue:%d, dst:%d, cSizeValue:%d, Fmatrix:0x%lx)_v2%s(xd:%d, xn:%d, xm:%d, xt:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, xtValue:0x%lx, sizeValue:%d, dTypeValue:%d, dst:%d, Transpose:%d, Fmatrix:0x%lx)mte_mov_xd_specialmte_mov_special_xnload_l1_to_l0_3dload_out_to_dst_unzipdepth_wise[ERROR]: ccu_addr_err: mte: addr: 0x{0:08x}, instr: {1:s}, id: {2:d}executeexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecutedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodeexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecuteexecutedecodeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserialize@ -+ executeexecuteexecuteexecuteexecuteexecute  9ScalarISA10scalar_add10scalar_sub10scalar_mul11scalar_madd10scalar_abs10scalar_div10scalar_mod11scalar_sqrt10scalar_neg10scalar_max10scalar_min10scalar_cmp11scalar_cmpn10scalar_sel10scalar_and9scalar_or10scalar_xor10scalar_not10scalar_shl10scalar_shr12scalar_sbcnt10scalar_sff10scalar_clz11scalar_conv14scalar_sflbits14scalar_sbitset16scalar_mov_xd_xn20scalar_mov_xd_imme1621scalar_movk_xd_imme1621scalar_mov_xd_special21scalar_mov_special_xn9scalar_ld9scalar_st14scalar_signext14scalar_zeroext13scalar_ld_imm13scalar_st_imm10scalar_ld410scalar_st414scalar_ld4_imm14scalar_st4_imm13scalar_insert17scalar_insert_ext13scalar_ld_ddr13scalar_st_ddr16scalar_add_imm1216scalar_mul_imm1216scalar_sub_imm1210scalar_ldp10scalar_stp16scalar_cmp_imm1217scalar_ld_ddr_imm17scalar_st_ddr_imm10scalar_sti14scalar_sti_imm12scalar_movx820scalar_mov_spr_imm1611scalar_dcci17scalar_dc_preload23scalar_dc_preload_imm12scalar_isa.cc[%s] %s:%d %s imme16 errors [%s] %s:%d %s dType errors [%s] %s:%d %s OP errors [%s] %s:%d %s datasource errors [%s] %s:%d %s imm6 errors [%s] %s:%d %s sbcnt errors [%s] %s:%d %s sff errors [%s] %s:%d %s bitSet errors [%s] %s:%d %s uimm2 errors [%s] %s:%d %s postValue errors [%s] %s:%d %s imm12 errors [%s] %s:%d %s imm6_5_4 errors [%s] %s:%d %s imm6_3_0 errors [%s] %s:%d %s uimm8 errors [%s] %s:%d %s ext errors [%s] %s:%d %s position_5 errors [%s] %s:%d %s position_4_0 errors [%s] %s:%d %s imm16 errors [%s] %s:%d %s xi errors [%s] %s:%d %s xj errors [%s] %s:%d %s immType errors [%s] %s:%d %s imm12_11_7 errors [%s] %s:%d %s imm12_6_0 errors [%s] %s:%d %s special excute errors xd errors%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx )%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, xn:0x%lx)%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, OP:0x%lx, conditionFlag:0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, OP:0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx,)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx )%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, datasource:= 0x%lx, imm6:= 0x%lx )%s(dType:0x%lx, x[%ld]= 0x%lx,x[%ld]= 0x%lx , datasource:= 0x%lx, imm6:= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx,x[%ld]= 0x%lx, sbcnt:0x%lx)%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx, sff:0x%lx)%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx, bitSet:0x%lx)%s( x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(x[%ld]= 0x%lx, imme16:0x%lx )%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, post = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm12= 0x%lx, post = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, 0x%lx, 0x%lx, 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm12= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, 0x%lx, 0x%lx, 0x%lx, x[%ld]= 0x%lx, imm12= 0x%lx)%s( x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm6 = 0x%lx, imm5 = 0x%lx)%s( x[%ld]= 0x%lx, x[%ld]= 0x%lx, ext = 0x%lx, position = 0x%lx, uimm8 = 0x%lx)%s( x[%ld]= 0x%lx, imm16 = 0x%lx)%s( %s = 0x%lx, imm16 = 0x%lx)%s(x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm12 = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm6= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, post = 0x%lx, immType = 0x%lx, immTypeValue = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, post = 0x%lx, immType = 0x%lx, immTypeValue = 0x%lx, imm12 = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, imm12 = 0x%lx, OP:0x%lx, conditionFlag:0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx)%s(x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(x[%ld]= 0x%lx, imm12= 0x%lx)scalar_addscalar_subscalar_mulscalar_maddscalar_absscalar_divscalar_modscalar_sqrtscalar_negscalar_maxscalar_minscalar_cmpscalar_cmpnscalar_selscalar_andscalar_orscalar_xorscalar_notscalar_shlscalar_shrscalar_sbcntscalar_sffscalar_clzscalar_sflbitsscalar_sbitsetscalar_mov_xd_xnscalar_mov_xd_imme16scalar_movk_xd_imme16scalar_mov_xd_specialscalar_mov_special_xnscalar_ldscalar_stscalar_signextscalar_zeroextscalar_ld_immscalar_st_immscalar_ld4scalar_st4scalar_ld4_immscalar_st4_immscalar_convscalar_insertscalar_insert_extscalar_movx8scalar_mov_spr_imm16scalar_add_imm12scalar_sub_imm12scalar_mul_imm12scalar_ldpscalar_stpscalar_stiscalar_sti_immscalar_cmp_imm12scalar_ld_ddrscalar_st_ddrscalar_ld_ddr_immscalar_st_ddr_immscalar_dcciscalar_dc_preloadscalar_dc_preload_imm12[%s] %s:%d %s unexpected stage for scalar_st. [%s] %s:%d %s unexpected stage for scalar_ld. [%s] %s:%d %s unexpected stage for scalar_sti_imm. 9VectorISA21vector_mov_xd_special21vector_mov_special_xn17copy_bufC2unified17copy_unifBuf2bufC20copy_unifBuf2unifBuf12brc_ub_2_dst6moveva8movemask14vector_op_2src14vector_op_1src18vector_vad_op_2src18vector_vad_op_1src19vector_auxiliary_op21vector_opticalflow_op14vector_obj_det7col2img12l0c_lock_set16l0c_lock_releasedecodedecodedecodedecodedecodedecodedecodeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializedecode@                                9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+   decodevector_isa.cc[%s] %s:%d %s MOV number of burst can't be 0 [%s] %s:%d %s vector_isa.cc: dest_addr = 0x%x is not 16 Byte aligned. [%s] %s:%d %s vector_isa.cc: dest_addr = 0x%x is not 32 Byte aligned. [%s] %s:%d %s vector_isa.cc: src_addr = 0x%x is not 32 Byte aligned. [%s] %s:%d %s vector_isa.cc: src1_addr = 0x%x is not 32 Byte aligned. [%s] %s:%d %s dest_addr = %lx address align error! %s(num_block:%d, num_burst : %d, burst : %d, dest_addr : 0x % x, src_addr : 0x % x, stride : %d, dst_stride : %d, conv : %d, srcID3: %d, srcID1: %d)%s(num_block:%d, num_burst : %d, burst : %d, num_block_remain:%d, dest_addr:0x%x, src_addr:0x%x, stride:%d, dst_stride:%d, conv:%d , dstID:%d%s(num_block:%d, num_burst : %d, burst : %d, dest_addr:0x%x, src_addr:0x%x, stride:%d, dst_stride:%d, conv:%d%s(num_block:%d, num_burst:%d, burst:%d, dest_addr:0x%x, src_addr:0x%x, stride:%d, dst_stride:%d, conv:%d, dstID:%d)%s(num_block:%d, Vad:%d, src_addr:0x%x, src1_addr:0x%x, element_id:%d)%s(num_block:%d, mask:%d, X%d:0x%lx)%s(op0:%d, op1:%d, op2:%d, type:%d, dest_addr:0x%x, src_addr:0x%x, dst_stride:%d, src_stride:%d, reg:%d, h0:%d)%s(op0:%d, op1:%d, op2:%d, type:%d, dest_addr:0x%x, src_addr:0x%x, dst_stride:%d, src_stride:%d, reg:%d, h0:%d, repeat:%d)%s(op0:%d, op1:%d, op2:%d, type/convType %d, repeat:%d, dest_addr:0x%x, src1_addr:0x%x, src_addr:0x%x, dst_stride:%d, src_stride:%d, dst_rep_stride:%d, src_rep_stride:%d, reg:%d, h0:%d)%s(op0:%d, op1:%d, op2:%d, convType %d, repeat:%d, dest_addr:0x%x, src_addr:0x%x, dst_stride:%d, src_stride:%d, dst_rep_stride:%d, src_rep_stride:%d, reg:%d, h0:%d)%s(op0:%d, op1:%d, op2:%d, conv_depth_type:%d, repeat:%d, dest_addr:0x%x, src_addr:0x%x, dst_stride:%d, src_stride:%d, dst_rep_stride:%d, src_rep_stride:%d, reg:%d.)%s(op0:%d, op1:%d, op2:%d, type/convType %d, repeat:%d, dest_addr:0x%x, src_addr:0x%x, dst_stride:%d, src_stride:%d, dst_rep_stride:%d, src_rep_stride:%d, reg:%d, h0:%d)%s(op0:%d, op1:%d, op2:%d, type:%d, repeat:%d, dest_addr:0x%x, src_addr:0x%x, src1_addr:0x%x, dst_stride:0x%x, src_stride:%d, src1_stride:%d, dst_rep_stride:0x%x, src_rep_stride:%d, src1_rep_stride:%d, reg:%d, h0:%d)%s(op0:%d, op1:%d, op2:%d, type/convType:%d, repeat:%d, Vad:%d, Van:%d, src1_addr:0x%x, Vad_stride:%d, Van_stride:%d, reg:%d, h:%d)%s(op0:%d, op1:%d, op2:%d, type/convType:%d, repeat:%d, Vad:%d, Van:%d, Vad_stride:%d, Van_stride:%d, reg:%d, h:%d)%s(op0:%d, op1:%d, op2:%d, type:%d, repeat:%d, Vad:%d, Vam:%d, Van:%d, Vad_stride:%d, Vam_stride:%d, Van_stride:%d, reg:%d, h0:%d)%s(op0 %d op1 %d type %d repeat:%d, Van: %d, dest_addr:0x%x, xt_val: %lx, M: %d, N: %d)%s(op0 %d op1 %d type %d repeat:%d, src_addr:0x%x, Vad: %d, xt_val: %lx, M: %d, N: %d)%s(op0 %d op1 %d type %d repeat:%d, Van: %d,, Vad: %d, xt_val: %lx, Van_stride: %d, Vad_stride: %d, M: %d, N: %d)%s(op0 %d op1 %d type %d repeat:%d, src_addr:0x%x, src1_addr:0x%x, dest_addr:0x%x, src_stride:%d, src1_stride:%d, dst_stride:%d, reg_type:%d, h0:%d)col2img%s(xd:%d, xn:%d, xm:%d, xt:%d, xdValue:0x%lx, xnValue:0x%lx, xmValue:0x%lx, xtValue:0x%lx)%s(op0 %d op1 %d type %d repeat:%d, xn_val: %lx, dest_addr:0x%x, xt_val: %lx)%s(op0 %d op1 %d type %d repeat:%d, Van: %d, dest_addr:0x%x, xt_val: %lx, M: %d, N: %d, Nd: %d)%s(op0 %d op1 %d type %d repeat:%d, src_addr:0x%x, Vad: %d, xt_val: %lx, M: %d, N: %d, Nd: %d)vector_mov_xd_specialvector_mov_special_xn[%s] %s:%d %s Xn address is not 32B aligned = 0x%lx. [%s] %s:%d %s Xm address is not 32B aligned = 0x%lx. [%s] %s:%d %s Xd address is not 32B aligned = 0x%lx. [%s] %s:%d %s Xn address is not 4B aligned = 0x%lx. [%s] %s:%d %s Xm address is not 2B i.e. fp16 aligned = 0x%lx. [%s] %s:%d %s Xd address is not 2B i.e. fp16 aligned = 0x%lx. copy_bufC2unifiedcopy_unifBuf2bufCcopy_unifBuf2unifBufbrc_ub_2_dstmovevamovemaskvector_op_1srcvector_op_2srcvector_vad_op_1srcvector_vad_op_2srcvector_opticalflow_opvector_obj_detvector_auxiliary_opl0c_lock_setl0c_lock_release{:s}:{:d}:{:s} Could not recognize the isa encoding for type! {:s}:{:d}:{:s} Could not recognize the isa encoding! {:s}:{:d}:{:s} B8, M is not multiple of 4! {:s}:{:d}:{:s} B8, M is not even number! {:s}:{:d}:{:s} fp16, M is not even number! {:s}:{:d}:{:s} fp16 dosen't support N=32 ! 11BasicBuffercheckReadWriteBytesParagetAccessMask@ readreadwritewritereadByteswriteBytesreadByteswriteBytesBasicBuffer-+   basic_buffer.cc[%s] %s:%d %s tick: %d. %s Address errors: the address or size is too big. start addr = 0x%x, size = 0x%x. [%s] %s:%d %s %s readBytes: the start address value over buffer size bound. address = 0x%x [%s] %s:%d %s %s getAccessMask errors. [%s] %s:%d %s %s read errors [%s] %s:%d %s %s write errors [%s] %s:%d %s %s readBytes: the address value :%d is too big [%s] %s:%d %s BasicBuffer::readBytes Size not match ERROR [%s] %s:%d %s %s writeBytes: the start address value over buffer size bound, address = 0x%x [%s] %s:%d %s %s writeBytes: the address value :%d is too big [%s] %s:%d %s bank_size is 0 that leads to division by zero. 8BasicDDR11BasicICacheSt23_Sp_counted_ptr_inplaceI7WRR_ArbSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6RR_ArbSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5ICReqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEread_cache_ram@ refill-+   readpreload_tspreload_ccucheck_ll_rsplookup_tagBasicICachebasic_icache.ccunknown typeNONEPRELOADPREFETCHREADunknown statusIDLEHITMISSFETCHINGCOMPLETEDPRELOAD_TSPRELOAD_CCU---------------------------------------------------------------------req_id_: addr_: size_: dest: buf_id: type: status: ll_req_id: -------------------- [{0:08d}]: icache READ request, id is 0x{1:x}, size is 0x{2:08x}, address is 0x{3:x}-------------------- [{0:08d}]: icache PRELOAD_TS request fail, addr: 0x{1:x}, preload_fifo_ size: 0x{2:x}, num: 0x{3:x}-------------------- [{0:08d}]: icache PRELOAD_TS request, addr: 0x{1:x}, num: 0x{2:x}, cacheline_nums: 0x{3:x}, req_id: 0x{4:x}-------------------- [{0:08d}]: icache PRELOAD_CCU request fail, addr: 0x{1:x}, preload_fifo_ size: 0x{2:x}-------------------- [{0:08d}]: icache PRELOAD_CCU request, addr: 0x{1:x}, num: 0x{2:x}, cacheline_nums: 0x{3:x}, req_id: 0x{4:x}[{0:08d}]: ccu end_instr flush icache clean_req_lst, preload_req id is 0x{1:x}[{0:08d}]: ccu end_instr flush icache clean_req_lst, normal_req id is 0x{1:x}[{0:08d}]: ccu miss_predict flush icache pipeline, normal_req id is 0x{1:x}[{0:08d}]: ccu miss_predict flush icache cmbf, normal_req id is 0x{1:x}[{0:08d}]: icache get_wrr_req: {1:s}, req_id_: 0x{2:x}[{0:08d}]: icache get_wrr_req: {1:s}, preload_type: {2:s}, req_id_: 0x{3:x}[{0:08d}]: icache refill acknowledge, req_id_: 0x{1:x}, ll_req_id_ is 0x{2:08x}, address is 0x{3:x}, buf_id is 0x{4:x}SIZE ERROR, tick: {0:d}, addr: 0x{1:x},size_: 0x{2:x},[{0:08d}]: icache refill request has same addr in CMBF, req_type:{1:08x}, req_id_: 0x{2:x}, ll_req_id_ is 0x{3:08x}, address is 0x{4:x}[{0:08d}]: icache refill request ostd hazard, req_type:{1:08x}, req_id_: 0x{2:x}, ll_req_id_ is 0x{3:08x}, address is 0x{4:x}, buf_id is 0x{5:x}[{0:08d}]: icache refill request, req_type:{1:08x}, req_id_ is 0x{2:x}, ll_req_id_ is 0x{3:08x}, address is 0x{4:x}, buf_id is 0x{5:x}[{0:08d}]: icache preload generate req num: 0x{1:x}, total_num: 0x{2:x}, req_id_: 0x{3:x}[{0:08d}]: icache preload fifo generate req done, req_id_: 0x{1:x}[{0:08d}]: icache read address is 0x{1:x}, size is 0x{2:08x}, status is {3:s}[{0:08d}]: icache replay stall[{0:08d}]: icache prefetch data is 0x{1:x}, id is 0x{2:x}[{0:08d}]: icache preload lookup_tag address is 0x{1:x}, id is 0x{2:x}, size is 0x{3:08x}, status is {4:s}[SP_ARB]: Requests are: [RR_ARB]: Requests are: [RR_ARB]: Last arb is: : [WRR_ARB]: Requests are: [WRR_ARB]: Weights are: [WRR_ARB]: Scores are: [WRR_ARB]: Weights sum is: 8CADCacheSt23_Sp_counted_ptr_inplaceI5DCReqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@             @                           @                        -+   invalid_allinvalid_clean_allclean_allclean_vainvalid_clean_vainvalid_varefillcheck_ll_read_rspread_cache_ramwrite_cache_raminvalid_req_creatwriteDatawriteback_cache_ramreadwritewriteback_req_creatca_dcache.ccstatus0: status1: aligned_addr_0: aligned_addr_1: addr_ofst_0: addr_ofst_1: aligned_size_0: aligned_size_1: hit_pos_0: hit_pos_1: buf_id_0: buf_id_1: ll_req_id_0: ll_req_id_1: ll_req_status_0: ll_req_status_1: refill_line_0: refill_line_1: cross_line_: tick: {0:d}, clean_req_lst push req_id: {1:d} to ccu_ack_refill_buf_------------------------ tick: {0:d}, invalid_all creat req, req_id: {1:d} ------------------------------------------------ tick: {0:d}, invalid_clean_all creat req, req_id: {1:d} ------------------------------------------------ tick: {0:d}, clean_all creat req, req_id: {1:d} ------------------------------------------------ tick: {0:d}, ccu ack to refill buf req_id: {1:d} ------------------------------------------------ tick: {0:d}, completed req_id: {1:d} ------------------------------------------------ tick: {0:d}, clean_va creat req, req_id: {1:d}, ddr_addr: 0x{2:x} ------------------------------------------------ tick: {0:d}, invalid_clean_va creat req, req_id: {1:d}, ddr_addr: 0x{2:x} ------------------------------------------------ tick: {0:d},invalid_va creat req, req_id: {1:d}, ddr_addr: 0x{2:x} ------------------------tick: {0:d}, refill, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, invalid_cache_ram_va, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, invalid_cache_ram, CMOING req complete, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, invalid_cache_ram, INVALIDING req complete, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, M4:complete_writeback, wbreq_id: {1:d} suc , req_type:{2:d}, req_sta:{3:d}tick: {0:d}, M4:check_ll_read_rsp, req_id: {1:d} suc , req_type:{2:d}, req_sta:{3:d}tick: {0:d}, M2:read-hit, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}, req_addr: 0x{4:x}tick: {0:d}, M2:write-hit, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}, req_addr: 0x{4:x}tick: {0:d}, M1:lookup_tag:cmo_all hit, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, size error: 0x{1:x}, addr: 0x{2:x}tick: {0:d}, M1:lookup_tag: req_id: {1:d} hit, set_idx: {2:d}, tag_addr: {3:x}, hit_pos: {4:d}tick: {0:d}, M1:lookup_tag:cmo_va hit, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}, req_addr: 0x{4:x}tick: {0:d}, M1:lookup_tag:cmo_va miss, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}, req_addr: 0x{4:x}tick: {0:d}, M1:lookup_tag: req_id: {1:d} misstick: {0:d}, M1:lookup_tag, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}, req_addr: 0x{4:x}, aligned_addr: 0x{5:x}, addr_ofst:{6:d},aligned_size:{7:d}tick: {0:d}, M3:send_ll_read_req, req_id: {1:d}, ll_port read suc, fetch_buf_id:{2:d}tick: {0:d}, M3:send_ll_read_req, req_id: {1:d}, ll_port read failtick: {0:d}, M3:send_ll_read_req, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, invalid_cacheline_req_creat, set_idx: {1:d}, tag_pos: {2:d}, wb_req_id: {3:d}, wb_req_type:{4:d}, wb_req_sta:{5:d}tick: {0:d}, invalid_cache_ram_all, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, M3:check_write_REQ_RSP success, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}tick: {0:d}, M3:check_write_DATA_RSP success, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}, buf_id:{6:d}tick: {0:d}, M3:send_write_DATA success, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}, buf_id:{6:d}tick: {0:d}, M3:send_write_DATA fail, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}, buf_id:{6:d}tick: {0:d}, M3:send_write_REQ success, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}tick: {0:d}, M3:send_write_REQ id fail, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}tick: {0:d}, M3:send_write_REQ fail, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}tick: {0:d}, writeback_cache_ram, wb_req_id: {1:d}, ll_port write suc, flush_buf_id: {2:d}tick: {0:d}, writeback_cache_ram, wb_req_id: {1:d}, ll_port write failtick: {0:d}, writeback_cache_ram, wb_req_id: {1:d}, set_idx: {2:d}, tag_pos: {3:d}, wb_req_type:{4:d}, wb_req_sta:{5:d}, wb_req_addr: 0x{6:x}tick: {0:d}, M0:check_conflict address stall, req_type:{1:d}, addr:0x{2:x}, size:{3:d}tick: {0:d}, M0:check_conflict write_port stall, req_type:{1:d}, addr:0x{2:x}, size:{3:d}tick: {0:d}, M0:check_conflict read_otsd_num stall, req_type:{1:d}, addr:0x{2:x}, size:{3:d}tick: {0:d}, M0:check_conflict write_cache_ram stall, req_type:{1:d}, addr:0x{2:x}, size:{3:d}tick: {0:d}, M0:check_conflict write_otsd_num stall, req_type:{1:d}, addr:0x{2:x}, size:{3:d}tick: {0:d}, M0:check_conflict wb_hit_buf stall, req_type:{1:d}, addr:0x{2:x}, size:{3:d}tick: {0:d}, M0:check_conflict pass, req_type:{1:d}, addr:0x{2:x}, size:{3:x}------------------------ tick: {0:d},read creat req, req_id: {1:d}, ddr_addr: 0x{2:x}, read size: 0x{3:x}, ldbuf_ptr: 0x{4:x} ------------------------------------------------ tick: {0:d},write creat req, req_id: {1:d}, ddr_addr: 0x{2:x}, write size: 0x{3:x}, st_bufptr: 0x{4:x} ------------------------tick: {0:d}, writeback_cacheline_req_creat, wb_req_id: {1:d}, flush_buf_id: {2:d}tick: {0:d}, writeback_cacheline_req_creat, wb_req_id: {1:d}, set_idx: {2:d}, tag_pos: {3:d}, wb_req_type:{4:d}, wb_req_sta:{5:d}, wb_req_addr: 0x{6:x}tick: {0:d}, writeback_cacheline_req_creat, wb_req_id: {1:d}, ll_port write suc, flush_buf_id: {2:d}tick: {0:d}, writeback_cacheline_req_creat, wb_req_id: {1:d}, ll_port write fail, flush_buf_id: {2:d}tick: {0:d}, writeback_cacheline_req_creat, wb_req_id: {1:d}, ll_port write failtick: {0:d}, clean_cache_ram_all, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, clean_cache_ram_va, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, invalid_clean_cache_ram_va, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, get_victim, find invalid cacheline, victim_pos: {1:d}tick: {0:d}, get_victim, lru valid cacheline, victim_pos: {1:d}tick: {0:d}, get_victim, lru valid cacheline, dirty replace, victim_pos: {1:d}tick: {0:d}, invalid_clean_cache_ram_all, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}8CAICacheupdatePredictor@ getInstrSet-+   ca_icache.ccvector::_M_realloc_insert[%s] %s:%d %s ca_icache, branch_res value error [%s] %s:%d %s ca_icache, instr number doesn't match! .A8PMU_ITEM12pmu_status_t13pmu_counter_t12pmu_number_t11pmu_ratio_t8pmu_bw_t3PMUSt23_Sp_counted_ptr_inplaceIN9DvcConfig3CfgESaIS1_ELN9__gnu_cxx12_Lock_policyE2EEupdatecalc_bwgetCurrentPathgetOmgPathconst toml::Value* toml::Value::findChild(const string&) constset_config_file@ getEnvPath-+   %d-%d-%d%nInvalid token%d:%d:%lf%n%c%d:%dstring didn't start with '"'string didn't endstring has unknown escape sequencestring didn't start with '''?string didn't end with ''''' ?string didn't end with '''?Unknown key formatUnknown ident: is()pmu.cc./[%s] %s:%d %s cannot open::current dir! rb/etc/HiAI_install.infoInstall_Path_Param[%s] %s:%d %s hiai_install_file is too long! /runtime/bincannot open::OMG diropen:: OMG dir open {0:s} config_aicore_trace.toml/model/ca_model/etc/[%s] %s:%d %s AICore trace config: %s LD_LIBRARY_PATH[%s] %s:%d %s env LD_LIBRARY_PATH has not set! [%s] %s:%d %s dup_path LD_LIBRARY_PATH failed! open::LD_LIBRARY_PATH nullboolunknowndoublearraytablebw_setting.window_size[error] cfg_ path is unqualified.type must be table to do get(key). was not found.key int64_t was requested but type error: this value is bw_setting.stride_sizevector.vec_instr_execvector.vec_instr_pop_statusvector.vec_instr_pop_cyclevector.vec_instr_retire_statusvector.vec_instr_retire_cyclescalar.scalar_instr_execscalar.scalar_instr_popscalar.scalar_instr_pop_cyclescalar.scalar_instr_retirescalar.scalar_instr_retire_cyclecube.cube_instr_execmte.mte1_instr_execmte.mte2_instr_execmte.mte3_instr_execmte.mte4_instr_execmte.mte5_instr_execmte.mte1_instr_popmte.mte2_instr_popmte.mte3_instr_popmte.mte4_instr_popmte.mte5_instr_popmte.mte1_instr_retiremte.mte2_instr_retiremte.mte3_instr_retiremte.mte4_instr_retiremte.mte5_instr_retirevector.vec_busy_statusvector.vec_busy_cyclevector.vec_mac_busy_statusvector.vec_mac_usage_cyclesvector.vec_excute_statusvector.vec_excute_cyclesvector.vec_efficiencyvector.vec_l0c_ub_cyclesscalar.scalar_busy_statusscalar.scalar_busy_cyclesscalar.scalar_mac_usage_statusscalar.scalar_mac_usage_cyclescube.cube_busy_statuscube.cube_busy_cyclecube.cube_mac_busy_statuscube.cube_mac_busy_cyclecube.cube_efficiencymte.mte1_busy_statusmte.mte2_busy_statusmte.mte3_busy_statusmte.mte4_busy_statusmte.mte5_busy_statusmte.mte1_busy_cyclemte.mte2_busy_cyclemte.mte3_busy_cyclemte.mte4_busy_cyclemte.mte5_busy_cyclecube.cube_instr_popcube.cube_instr_retiremte.l0c_write_bandwidthmte.l0c_write_cyclemte.l2_buf_read_reqmte.l2_buf_write_reqmte.ddr_read_reqmte.ddr_write_reqvector.ub_read_bandwidthvector.ub_write_bandwidthvector.ub_read_statusvector.ub_write_statuscube.l0a_read_bandwidthmte.l0a_write_bandwidthcube.l0a_read_cyclesmte.l0a_write_cyclecube.l0b_read_bandwidthmte.l0b_write_bandwidthcube.l0b_read_cyclesmte.l0b_write_cyclevector.vec_2_l0c_read_bandwidthcube.cube2l0c_read_bandwidthvector.vec_2_l0c_write_bandwidthcube.cube2l0c_write_bandwidthvector.vec_2_l0c_read_statuscube.cube2l0c_read_cyclesvector.vec_2_l0c_write_statuscube.cube2l0c_write_cyclesmte.l1_read_bandwidthmte.l1_write_bandwidthmte.l1_read_cyclemte.l1_write_cyclemte.l1_rd_wr_bank_conflict_cyclemte.l1_wr_wr_bank_conflict_cyclescalar.scalar2ub_read_statusscalar.scalar2ub_write_statusscalar.total_scalar2ub_statusscalar.scalar2ub_read_reqscalar.scalar2ub_write_reqscalar.total_scalar2ub_reqscalar.scalar2sb_read_statusscalar.scalar2sb_write_statusscalar.total_scalar2sb_statusscalar.scalar2sb_read_reqscalar.scalar2sb_write_reqscalar.total_scalar2sb_reqscalar.scalar2ub_read_cyclesscalar.scalar2ub_write_cyclesscalar.total_scalar2ub_cyclesscalar.total_scalar2sb_cyclesmte.mte3_ub_read_bandwidthmte.mte3_ub_write_bandwidthmte.mte3_ub_read_cyclemte.mte3_ub_write_cyclevector.vec_2_ub_read_bandwidthvector.vec_2_ub_write_bandwidthvector.vec_2_ub_read_statusvector.vec_2_ub_write_statuscube.cube_fp16_execcube.cube_int8_execvector.vec_fp32_execvector.vec_fp16_128lane_execvector.vec_fp16_64lane_execvector.vec_fp16_32lane_execvector.vec_int32_execvector.vec_misc_execscalar.flow_ctrl_execscalar.loop_execifu.icache_reqifu.icache_missifu.icache_preloadifu.icache_predict_pcifu.psq_ostd_full_statusscalar.scalar_waitflag_cyclesscalar.cube_waitflag_cyclesscalar.vec_waitflag_cyclesscalar.vec_v2_waitflag_cyclesscalar.mte1_waitflag_cyclesscalar.mte2_waitflag_cyclesscalar.mte3_waitflag_cyclesscalar.mte4_waitflag_cyclesscalar.mte5_waitflag_cyclesscalar.indir_jump_instrscalar.mispredicted_instrscalar.scalar_div_execscalar.scalar_div_statusscalar.scalar_div_cyclesscalar.scalar_mult_execscalar.scalar_madd_execvector.rd_bankgroup_stall_statusvector.rd_bankgroup_stall_cyclesvector.wr_bankgroup_stall_statusvector.wr_bankgroup_stall_cyclesvector.vec_l0c_rd_stall_statusvector.vec_l0c_rd_stal_cyclesvector.vec_l0c_wr_stall_statusvector.vec_l0c_wr_stall_cyclesvector.vec_resc_conflict_statusvector.vec_resc_conflict_cyclesscalar.mte1_iq_full_statusscalar.mte1_iq_full_cyclesscalar.mte2_iq_full_statusscalar.mte2_iq_full_cyclesscalar.mte3_iq_full_statusscalar.mte3_iq_full_cyclesscalar.mte4_iq_full_statusscalar.mte4_iq_full_cyclesscalar.mte5_iq_full_statusscalar.mte5_iq_full_cyclesscalar.cube_iq_full_statusscalar.cube_iq_full_cyclesscalar.vec_iq_full_statusscalar.vec_iq_full_cyclesscalar.ccu_wait_instr_statusscalar.ccu_wait_instr_cyclesscalar.ccu_pipe_stall_statusscalar.single_issue_cyclesscalar.dual_issue_cyclesscalar.scalar_only_cyclescube.cube_l0c_stallbiu.biu_read_port0_latencybiu.biu_read_port1_latencybiu.biu_write_port0_latencybiu.biu_write_port1_latencybiu.biu_read_outstandingbiu.biu_write_outstandingbiu.biu_read_l2_bandwidthbiu.biu_write_l2_bandwidthbiu.biu_read_ddr_bandwidthbiu.biu_write_ddr_bandwidthscalar.mte1_iq_instr_numscalar.mte2_iq_instr_numscalar.mte3_iq_instr_numscalar.mte4_iq_instr_numscalar.mte5_iq_instr_numscalar.cube_iq_instr_numscalar.vec_iq_instr_nummte.fmc_work_cyclemte.fmc_idle_cyclemte.fmd_work_cyclemte.fmd_idle_cyclemte.mte_fmc_input_vldmte.mte_fmc_output_vldmte.mte_fmd_input_vldmte.mte_fmd_output_vldbiu.biu_busy_cyclemte.unzip instr event18sc_trace_file_baseopen_fpconst toml::Value* toml::Value::findChild(const string&) const@ -+   sc_trace_file_base.ccint[%s] %s:%d %s File path %s do not exist. _wave.vcdw[%s] %s:%d %s open file %s failed [%s] %s:%d %s Update file [%s] authority failed. %b %d, %Y %H:%M:%SProject.vcd_versionlog.flush_level14vcd_trace_file9vcd_trace14vcd_bool_trace18vcd_uint32_t_trace18vcd_uint64_t_trace15vcd_float_trace16vcd_double_traceprint_variable_declaration_linecompose_data_linewrite_commentobtain_namesummary_log@ -+   r%.16g %s'' has 0 bits$var %s % 3d %s %s $end sc_vcd_trace.cc$var %s % 3d %s %s [%d:0] $end [%s] %s:%d %s copy data from vcd_name to compdata failed, errno_t: %d. b%s %sbbasic_string::substr%s: __pos (which is %zu) > this->size() (which is %zu)$scope module %s $end $upscope $end vcd[%s] %s:%d %s fp is nullptr $comment $end #%c%c%c%c%c_summary_log============================================================================== kernal total ticks : %u system total ticks : %u Trace_Name | Total_Num %-44s| %lu+++++++++++++++++++++ core: %d, tick: %d, kernal %d done +++++++++++++++++++++ AiCore$date %s $end vcd_version : $version %s%d $end 1 tick$timescale %s $end $enddefinitions $end all initial values are dumped below at time : tick = $dumpvars $end wirerealconst toml::Value* toml::Value::findChild(const string&) const@ add_trace_listinitial-+   trace.ccsystem.tickmem_bandwidth.tracearithmatic_throughput.traceflow_control.tracescalar_pipeline.tracestall_conditions.tracehistogram.traceinstructions.tracecontd_tri.scalar_busy_cycleProject.pathtick_tri.start_trace_ticktick_tri.end_trace_ticktick_tri.gap_trace_tickaicore_trace_enable.tracesummary_log_enable.enable4Dumpconst toml::Value* toml::Value::findChild(const string&) const@ setConfig-+   *ZN4DumpD4EvEUlSt10shared_ptrIN13ascend_spdlog6loggerEEE_logdump.ccCA_L0_UB_CrossbarL0_UB_Crossbar VECTOR_WR_PORT VECTOR_RD1_PORT VECTOR_RD2_PORT SCALAR_WR_PORT SCALAR_RD_PORT LSU_WR1_PORT LSU_WR2_PORT LSU_RD_PORT CUBE_PORT VECTOR_PORTCUBE_PORTMTE_PORTNORMALBARRINGWAIT_SYNC_EVENTENDDMAC_L4_PIPEDMAC_L5_PIPEVECTOR_PIPE_V2REQUESTDATAconfig.toml[%s] %s:%d %s config.toml cannot found, SIM.rotating of log use default value [%s] %s:%d %s cannot open %s instr_logcube_logvector_logscalar_logccu_loglsu_logrob_logbiu_stall_logmte_biu_req_logmte_biu_resp_logmte_rob_usage_logunzip_logfmd_logfmc_logmte_status_logbuffer_logrd_buffer_logl0a_rd_logl0a_wr_logl0b_rd_logl0b_wr_logl0c_rd_logl0c_wr_logub_rd_logub_wr_logl1_rd_logl1_wr_logbiu_logbiu_result_logbiu_rd_data_loginstr_popped_logub_logbank_conflict_logissque_logicache_logbp_logbuffer_op_logdcache_logbuffer_pingpong_conflict_logreg_logmte_logSIM.rotating_file_sizeSIM.rotating_file_number[{0:08d}](PC: 0x{1:08x}) {2:s} : (Binary: 0x{3:08x}) {4:s} [{0:08d}](PC: 0x{1:08x}) {2:s} : (Binary: 0x{3:08x}) {4:s} Bank conflict RD({5:d}) WR({6:d})[{0:08d}](PC: 0x{1:08x}) {2:s} : (Binary: 0x{3:08x}) {4:s} Bank conflict RD({5:d}) WR({6:d}), WrCubelock wait({7:d}))[{0:08d}](PC: 0x{1:08x}){2:s} : (Binary: 0x{3:08x}) {4:s} start_cycle({5:d}) end_cycle({6:d})tick: {0:08d}tick: {0:d}, LSU_OUT_burst_length: {1:d}. Address: 0x{2:x}tick: {0:d}, LSU_IN_burst_length: {1:d}. Address: 0x{2:x}{0:d} {1:d} {2:d} 0x{3:x} tick: {0:d}, MTE RD ROB. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, READ_BIU_ADDR: 0x{5:08x}tick: {0:d}, MTE RECIEVE BIU RD RESP. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, READ_ADDR: 0x{5:08x}, AXI: {6:d}.tick: {0:d}, MTE RECIEVE BIU WR RESP. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, WRITE_ADDR: 0x{5:08x}, AXI: {6:d}.tick: {0:d}, MTE SEND BIU RD REQ. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, READ_ADDR: 0x{5:08x}, AXI: {6:d}.tick: {0:d}, MTE SEND BIU WR REQ. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, WRITE_ADDR: 0x{5:08x}, AXI: {6:d}.tick: {0:d}, MTE LOWER ROB IS INCREASED BY: {1:d} B, REMAINING: 0x{2:x}.tick: {0:d}, MTE LOWER ROB IS DECREASED BY: {1:d} B, REMAINING: 0x{2:x}.tick: {0:d}, MTE HIGHER ROB IS INCREASED BY: {1:d} B, REMAINING: 0x{2:x}.tick: {0:d}, MTE HIGHER ROB IS DECREASED BY: {1:d} B, REMAINING: 0x{2:x}.tick: {0:d}, Cube_conflict_stage {1:d}.tick: {0:d}, BIU_Read_Req_Num: {1:d}.tick: {0:d}, BIU_Write_Req_Num: {1:d}.tick: {0:d}, fmd engine: {1:d} in working statustick: {0:d}, fmd engine: {1:d} in idle statustick: {0:d}, fmd engine: {1:d} in stall statustick: {0:d}, unzip engine: {1:d} in working statustick: {0:d}, unzip engine: {1:d} in idle statustick: {0:d}, unzip engine: {1:d} in stall statusFMC block compression fail. Inst ID: {0:d}, Block ID: {1:d}, Total: {2:d}tick: {0:d}, {1:s} is busy.current_tick: {0:d}.tick: {0:d}, BIU_RD_TAG_ID_USED_UPtick: {0:d}, BIU_ROB_FULLtick: {0:d}, BIU_RD_OTSD_FULLYtick: {0:d}, BIU_WR_TAG_ID_USED_UPtick: {0:d}, BIU_WR_BUSYtick: {0:d}, BIU_WR_OTSD_FULLYtick: {0:d}, L2_BIU_IN_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, SYSCACHE_BIU_IN_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, DDR_BIU_IN_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, L2_BIU_OUT_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, SYSCACHE_BIU_OUT_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, DDR_BIU_OUT_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, Mac_Usage: {1:f} I1-I6 Usage: {2:f} WR1-WR3 Usage: {3:f}.tick: {0:d}, Dma_Usage, Mac_Usage: {1:f} I1-I6 Usage: {2:f} WR1-WR3 Usage: {3:f}.tick: {0:d}, Mac_Usage: {1:f}.tick: {0:d}, Cube_conflict_stage {1:s}.tick: {0:d}, {1:s}, {2:s}.tick: {0:d}, {1:s} pc: 0x{2:08x}.tick: {0:d}, {1:s}, write: addr: 0x{2:x}, size: {3:d}.tick: {0:d}, {1:s}, Read_request: addr: 0x{2:x}, port: 0x{3:x}.tick: {0:d}, {1:s}, Write_request: addr: 0x{2:x}, port: 0x{3:x}.tick: {0:d}, {1:s}, Partial_write_request: addr: 0x{2:x}, port: 0x{3:x}.tick: {0:d}, {1:s}, Read_pingpong_conflict: addr: 0x{2:x}, size: {3:d}.tick: {0:d}, {1:s}, Write_pingpong_conflict: addr: 0x{2:x}, size: {3:d}.[{0:08d}]({1:s}): STATUS EXECUTE : {2:s} change into {3:s}, Trigger pipe is {4:s}[{0:08d}]({1:s}): STATUS RESUME : {2:s} change into {3:s}[{0:08d}]({1:s}): POP STALL : (PC: 0x{2:08x}), (Binary: 0x{3:08x}) {4:s} [{0:08d}] EVENT QUEUE ADD SET FLAG HAZARD: SRC_PIPE:{1:s} DST_PIPE:{2:s} EVENT_ID:{3:d} WAITTING_RETIRE_NUM : VEC0:{2:d} | VEC1:{3:d} | MTE1:{4:d} | MTE2:{5:d} | MTE3:{6:d} | MTE4:{7:d} | MTE5:{8:d} | CUBE:{9:d}[{0:08d}]({1:s}): status is {2:s}[{0:08d}] event: src pipe is {1:s}, dst pipe is {2:s}, id is {3:d}, num is {4:d}[{0:08d}]: cache read address is 0x{1:08x}, size is 0x{2:08x}, status is {3:s}[{0:08d}]: cache refill acknowledge, id is 0x{1:08x}, address is 0x{2:08x} [{0:08d}]: cache refill request, id is 0x{1:08x}, address is 0x{2:08x}[{0:08d}]: icache load data is 0x{1:08x}[{0:08d}]: predictor sucessful, branch result is 0x{1:08x}, pht index is {2:d}[{0:08d}]: predictor fail, branch result is 0x{1:08x}, pht index is {2:d}++++++++++++++++++++++core: {0:d}, tick: {1:d}, kernal{2:d} done++++++++++++++++++++++. [{0:08d}]({1:s}): status is {2:s}, source pipe is {3:s}[{0:08d}] SET_EVENT ------ SRC_PIPE ----- DST_PIPE ----- EVENT_ID ----- NUM[{0:08d}] WAIT_EVENT ----- SRC_PIPE ----- DST_PIPE ----- EVENT_ID ----- NUM # {0:15s}{1:15s}{2:d}{3:15d}tick: {0:08d} {1:s} {2:s} Address {3:08x} size {4:d}tick: {0:08d} {1:s}tick: {0:08d} {1:s}:{2:04d}tick: {0:d}, {1:s}, Read_bank_conflict: addr: 0x{2:x}, size: {3:d}.tick: {0:d}, {1:s}, Write_bank_conflict: addr: 0x{2:x}, size: {3:d}.tick: {0:d}, {1:s}, Partial_write_bank_conflict: addr: 0x{2:x}, size: {3:d}.ZN9BasicCube19dw_calculateB8toS32IhaEEvRK23tag_depthwise_conv_infojjEUlPhE_ZN9BasicCube19dw_calculateB8toS32IaaEEvRK23tag_depthwise_conv_infojjEUlPaE_ZN9BasicCube19dw_calculateB8toS32IhhEEvRK23tag_depthwise_conv_infojjEUlPhE_ZN9BasicCube21mmad_calculateB8toS32IhaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_ZN9BasicCube21mmad_calculateB8toS32IhaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_ZN9BasicCube21mmad_calculateB8toS32IhhEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_ZN9BasicCube21mmad_calculateB8toS32IhhEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_ZN9BasicCube21mmad_calculateB8toS32IaaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_ZN9BasicCube21mmad_calculateB8toS32IaaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_9BasicCubeSt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IaaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IaaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IhhEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IhhEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IhaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IhaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPhZN9BasicCube19dw_calculateB8toS32IhhEEvRK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPaZN9BasicCube19dw_calculateB8toS32IaaEEvRK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPhZN9BasicCube19dw_calculateB8toS32IhaEEvRK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13CubePipeSliceSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE*ZN9BasicCube24mmad_calculatefp16tofp16ER13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_*ZN9BasicCube24mmad_calculatefp16tofp16ER13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_*ZN9BasicCube24mmad_calculatefp16tofp32ER13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_*ZN9BasicCube24mmad_calculatefp16tofp32ER13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_*ZN9BasicCube16arrange_matrix_aER13cube_fsm_paraP18tag_cube_exec_infoEUlPhE_*ZN9BasicCube13read_matrix_cER13cube_fsm_paraP18tag_cube_exec_infoEUlPhE_*ZN9BasicCube17dw_conv_apply_memER23tag_depthwise_conv_infoEUlPtE_*ZN9BasicCube18dw_conv_read_mat_aER23tag_depthwise_conv_infoEUlPhE_*ZN9BasicCube18dw_conv_read_mat_bER23tag_depthwise_conv_infoEUlPtE_*ZN9BasicCube20dw_calculateF16toF16ERK23tag_depthwise_conv_infojjEUlPtE_*ZN9BasicCube20dw_calculateF16toF32ERK23tag_depthwise_conv_infojjEUlPtE_decodeB8U2toB8arrange_matrix_a_normal_modearrange_matrix_a_gemv_modearrange_matrix_b_b8_fp16decodeU2toFp16getB8U2opcodemmul_stage_exc_start@ arrange_matrix_adw_conv_apply_memget_r_b_info_normal_type-+   dw_calculateB8toS32mmad_calculateB8toS32mmad_calculateB8toS32mmad_calculateB8toS32mmad_calculatefp16tofp16mmad_calculatefp16tofp32pop_instrread_matrix_cdw_conv_read_mat_bupdate_pipeline_stagetickdumpdw_conv_read_mat_adw_calculateF16toF16dw_calculateF16toF32dw_calculateB8toS32dw_calculateB8toS32*St19_Sp_counted_deleterIPtZN9BasicCube24mmad_calculatefp16tofp16ER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube24mmad_calculatefp16tofp16ER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube24mmad_calculatefp16tofp32ER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube24mmad_calculatefp16tofp32ER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN9BasicCube16arrange_matrix_aER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN9BasicCube13read_matrix_cER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube17dw_conv_apply_memER23tag_depthwise_conv_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN9BasicCube18dw_conv_read_mat_aER23tag_depthwise_conv_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube18dw_conv_read_mat_bER23tag_depthwise_conv_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube20dw_calculateF16toF16ERK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube20dw_calculateF16toF32ERK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE[error] issue_q_ nullptr[error] pmu_ nullptrCUBE::dw_calculateB8toS32:sMaskOffset == {0:d}: sMask_addr: {1:d}, sMask_value: {2:d}, channel: {3:d}, bias: {4:d}.CUBE::dw_calculateB8toS32:i == {0:d}: j: {1:d}, ch: {2:d}, mat_c_pos: {3:d}, mat_c_value: {4:08x}.cube get_row_col_in_frac_mtx: none zero number should no more than cube size.instr: {0:s} id: {1:d}basic_cube.cc[%s] %s:%d %s unexpected u2_num when low_pre_tbl == 3. [%s] %s:%d %s unexpected u2_num. [%s] %s:%d %s unexpected low_pre_tbl 62:63 value. [%s] %s:%d %s tick: %x, frac_run_stage: %x, matrix_piped_cycle: %x. [error] wrong data type! small k only support integer. [error] wrong data type! sparse mode does not support s4. dpw_fifo nullptr!pmu_ nullptr![%s] %s:%d %s mem alloc out of range [%s] %s:%d %s l0_b_round = 0x%x is larger than l0b size. Error! cube:is_set_legal : winograd and small-K mode can not work together instr: {0:s} id: {1:d}Error! cube:is_set_legal : winograd and offset mode can not work togetherinstr: {0:s} id: {1:d}Error! cube:is_set_legal :sparse and SPR_LOW_PRE_TBL[63:62] == 2'b11 can not work together, when data type == b8u2.instr: {0:s} id: {1:d}Error! cube:is_set_legal : offset and SPR_LOW_PRE_TBL[63:62] == 2'b11 can not work together, when data type == b8u2.instr: {0:s} id: {1:d}isInstrSmallerThanOne16x16Matrx or two adjacent depthwise_convwaiting_sync_pulse[NOT SUPPORT] cube structure sparsity instr: {0:s} id: {1:d} not support in h200[NOT SUPPORT] cube instr: {0:s} id: {1:d} not support in h200unexpected cube instr opcode cube instr: {0:s} Id: {1:d} calculate fp16 to fp32 input is NaN.cube instr: {0:s} Id: {1:d} calculate fp16 to fp32 input is inf.CUBE {0:s}: l0b addr out of range, instr id: {1:d}cube instr: {0:s} Id: {1:d} input fp16 is NaN/INF.cube instr: {0:s} Id: {1:d} calculate fp16 to fp16 input is NaN.cube instr: {0:s} Id: {1:d} calculate fp16 to fp16 input is inf.CUBE {0:s}: l0a addr out of range, instr id: {1:d}CUBE {0:s}: l0c addr out of range, instr id: {1:d}CUBE {0:s}: l0B addr out of range, instr id: {1:d}tick: {0:d} enable_nop_counter: CUBE: dw_conv_read_info Error, ret = {0:x}. dw_conv_apply_mem: Error, ret = {0:d}. dw_conv_read_mat_a: Error, ret = {0:d}. vdrop_counter_ nullptr tick: {0:d}, reached_vdrop_interval.tick: {0:d}, en_vdrop.tick: {0:d}, en_check_sync_p.cube_dummpy_cyclecube_nop_cyclevector_writel0c_bp_stalll0a_auto_pingpong_setl0b_auto_pingpong_setl0c_auto_pingpong_set[%s] %s:%d %s cube_busy_cnt is nullptr! [%s] %s:%d %s dump_ nullptr! tick: {0:d} pipeline content: stage: {0:d}; count: {1:d}; pc: {2:x};fsm read a cur_tick: {0:d}, last read: {1:d}, a_col_continue_index: {2:d}****fsm read b cur_tick: {0:d}, last read: {1:d}, b_col_continue_index: {2:d}fsm read c cur_tick: {0:d}, c_col_continue_index: {1:d}fsm ****write c cur_tick: {0:d}, c_col_continue_index: {1:d}fsm ****write c cur_tick: {0:d}, c_col_continue_index: {1:d}, start_addr: {2:x}CUBE::dw_conv_stage_write_l0c:matrix_i == {0:d}: row: {1:d}, column: {2:d}, pos_arry: {3:d}, pos_tmp: {4:d}.CUBE::dw_conv_read_mat_a:i: {0:d}, j: {1:d}, matrix_a_arr_pos: {3:d}, data: 0x{4:x}.CUBE::dw_calculateF16toF16:i == {0:d}: j: {1:d}, ch: {2:d}, mat_c_pos: {3:d}, mat_c_value: {4:08x}.CUBE::dw_calculateF16toF32:i == {0:d}: j: {1:d}, ch: {2:d}, mat_c_pos: {3:d}, mat_c_value: {4:08x}.dw_conv_read_info: isa is nullptr. dw_conv_apply_mem: Error! W must equal to 16*N + 2, When Xt[63] == 0'b1 instr: {0:s} id: {1:d}CUBE::dw_conv_read_info: H: {0:d} W: {1:d} conv_padding_ctrl: {2:d} mat_type: {3:d} sMask_addr: {4:d} feature_map_offset: {5:d} weight_matrix_offset: {6:d} a_w_size: {7:d} a_w_frac: {8:d} 13BasicRegister16BasicGPRRegisterset_exception@ scalar_read_registerscalar_write_register-+   basic_gpr_register.cc[%s] %s:%d %s GPR is not supporting set_exception function. unknown registerName8BasicLSU@             @                           @                        -+   basic_lsu.ccLSU Error: Unzip Table Length > %d. =<Nxp`hF$,V<4F@             @                           @                        -+   load_3d_decodemte_instr_decode14BasicMteDecodeSt23_Sp_counted_ptr_inplaceI10mte_info_tSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEbasic_mte_decode.ccvector::_M_insert_aux[NOT SUPPORT] k-sparse not support in h200[NOT SUPPORT] DECOMPRESS_HEADER not support in h200sparse mode do not support B4 data type!smask INDEX: src addr: 0x{0:08x} should be 2B aligned in biu port. Id: {1:d}smask INDEX: src addr: 0x{0:08x} should be 32B aligned in ub port. Id: {1:d}smask INDEX: dst addr: 0x{0:08x} should be 32B aligned. Id: {1:d}smask INDEX: dst addr: 0x{0:08x} is overflow. Id: {1:d}MTE {0:s}: src_addr: 0x{1:08x} overflow: 0x{2:08x}. Id: {3:d}depthwise: fm_h : {0:d} < 3. Id: {1:d}depthwise: fm_w : {0:d} is illegle when pad is disable. Id: {1:d}MTE: {0:s}: block number zero error. Id: {1:d}[NOT SUPPORT] SET_RAWHEADER_TO_OUT not support in h200[NOT SUPPORT] COMPRESS_UB_TO_OUT not support in h200load_3d:error padding = 0x{0:x} in B8 data type!MTE {0:s}: mte_err_illegal_k_m_start_pos k_start: {1:d}, c0: {2:d}. Id: {3:d}MTE {0:s}: mte_err_illegal_k_m_start_pos m_start: {1:d}. Id: {2:d}MTE {0:s}: mte_err_illegal_k_m_start_pos k_start: {1:d}, m_start: {2:d}. Id: {3:d}MTE {0:s}: mte_err_illegal_k_m_ext_step k_length: {1:d}, m_length: {2:d}. Id: {3:d}MTE: {0:s}: write addr wrap error. Id: {1:d}[NOT SUPPORT] DECOMPRESS_OUT_TO_DST not support in h200MTE {0:s}: dst_addr: 0x{1:08x} should be {2:d} byte align. Id: {3:d}MTE {0:s}: dst_addr: 0x{1:08x} overflow 0x{2:08x}. Id: {3:d}MTE {0:s}: mte_fpos_larger_fsize: fetch_pos_w:{1:d}, fetch_pos_h:{2:d}, filter_w:{3:d}, filter_h:{4:d}. Id: {5:d}MTE {0:s}: mte_fmapwh_larger_l1size: fm_w:{1:d}, fm_h:{2:d}, c_index:{3:d}. Id: {4:d}MTE {0:s}: mte_cidx_overflow: fm_w:{1:d}, fm_h:{2:d}, c_index:{3:d}. Id: {4:d}MTE {0:s}: mte_fmap_less_kernel. Id: {1:d}MTE {0:s}: mte_f1wpos_larger_fsize. Id: {1:d}MTE {0:s}: src_addr: 0x{1:08x} should be {2:d} byte align. Id: {3:d}MTE {0:s}: dst_addr: 0x{1:08x} should be 32 byte align. Id: {2:d}MTE {0:s}: dst_addr: 0x{1:08x} should be 512 byte align. Id: {2:d}MTE {0:s}: mte_illegal_fm_size: fm_w:{1:d}, fm_h:{2:d}. Id: {3:d}{0:s}: dst_addr = 0x{1:08x} not 512B align. Id: {2:d}{0:s}: dst_addr = 0x{1:08x} not 1024B align. Id: {2:d}{0:s}: burst_num = 0. Id: {1:d}{0:s}: burst_len = 0. Id: {1:d}MTE {0:s}: src_addr: 0x{1:08x} should be 32 byte align. Id: {2:d}[NOT SUPPORT] loadb2 do not support fp16 in h200[NOT SUPPORT] LOAD_L1_TO_L0B_WINOGRAD do not support fp16 in h200{0:s}: src_addr = 0x{1:08x} not 32B align. Id: {2:d}{0:s}: dst_addr = 0x{1:08x} not 32B align. Id: {2:d}{0:s}: src_addr = 0x{1:08x} not 32B align in pad mode. Id: {2:d}{0:s}: dst_addr = 0x{1:08x} not 32B align in pad mode. Id: {2:d}[NOT SUPPORT] LOAD_L1_TO_L0A_WINOGRAD do not support fp16 in h200Mm}EeU} }+#5=}]u __dmac_brc__dmac_brc_conv__dmac_padding@ move_data_opt2mov_smask_executedmac_mov_dataload3d_read_datawinograd_b_read_datawinograd_a_read_datawinograd_b_read_datawinograd_a_read_datawinograd_b_read_datawinograd_a_read_data            @                           @                        -+   dcmp_block15BasicMteExecutebasic_mte_execute.ccvector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)ERROR DMA INSTR INFOERROR BRC INSTR INFOMTE: {0:s}: decompress len less errorMTE: {0:s}: decompress len over/less errorWINOGARD SRC IS INF: SRC = 0x{0:x}WINOGARD SRC IS NAN: SRC = 0x{0:x}{0:s}, k sparse errorerror instr for mtespecial_hazard_handlingexecute_scalar_instrBasicScalarBasicScalarupdate_pipelinebasic_scalar_cmp_s64basic_scalar_cmp_u64basic_scalar_selbasic_scalar_andbasic_scalar_orbasic_scalar_xorbasic_scalar_notbasic_scalar_sbitsetbasic_scalar_sflbitsbasic_scalar_clzbasic_scalar_sff_b64basic_scalar_sbcntbasic_scalar_shrbasic_scalar_shlbasic_scalar_signextbasic_scalar_zeroextbasic_scalar_cmp_imm12is_scalar_buffer_accesscheck_fp_status@ basic_scalar_absbasic_scalar_negbasic_scalar_maxbasic_scalar_minbasic_scalar_cmp_f32basic_scalar_cmpn_f32basic_scalar_ldbasic_scalar_ld_immbasic_scalar_ld4basic_scalar_ld4_immbasic_scalar_ldpbasic_scalar_ld_ddrbasic_scalar_ld_ddr_immbasic_scalar_st_ddrbasic_scalar_st_ddr_immbasic_scalar_addbasic_scalar_subbasic_scalar_mulbasic_scalar_maddbasic_scalar_convbasic_scalar_sti_immbasic_scalar_stibasic_scalar_stpbasic_scalar_st4_immbasic_scalar_st4basic_scalar_st_immbasic_scalar_st-+   basic_scalar_divbasic_scalar_modbasic_scalar_dccibasic_scalar_sqrt11BasicScalarbasic_scalar.cc[%s] %s:%d %s op type errors [%s] %s:%d %s op errors [%s] %s:%d %s scalar buffer addr = 0x%x, larger than 0x%x. [%s] %s:%d %s Scalar: pc: 0x%x, instr %s overflow. [%s] %s:%d %s Scalar: pc: 0x%x, instr %s underflow. [%s] %s:%d %s Scalar: pc: 0x%x, instr %s nan. [%s] %s:%d %s Scalar: pc: 0x%x, instr %s inf. LDLD_conflit_StackLD_conflitdType errorsLD_IMMLD_IMM_conflit_StackLD_IMM_conflitLD4LD4_conflit_StackLD4_conflitLD4_IMMLD4_IMM_conflit_StackLD4_IMM_conflitLDPLDP_conflit_StackLDP_conflit[%s] %s:%d %s this->unifiedBufferBar_ is nullptr [%s] %s:%d %s scalar conv not support conv type: %x. ST_IMMST_IMM_conflit_StackST_IMM_conflitSTSTI_conflit_StackSTI_conflitSTPSTP_conflit_StackSTP_conflitST4_IMMST4_IMM_conflit_StackST4_IMM_conflitST4ST4_conflit_StackST4_conflitST_conflit_StackST_conflitSCALAR: {0:s}: ccu_div0. Divisor == 0 is division. pc: {1:x}SCALAR: {0:s}: pc: {1:x} [NOT SUPPORTED] dcache preload instruction is not supported.SCALAR: {0:s}: pc: {1:x} [NOT SUPPORTED] dcache preload imm instruction is not supported.SCALAR: {0:s}: pc: {1:x} [NOT SUPPORTED] DCCI instruction is not supported.SCALAR: {0:s}: ccu_neg_sqrt. Negative number in sqrt instruction. pc: {1:x}16BasicSPRRegisterset_exceptionvector_write_registervector_read_register@ BasicSPRRegister-+   scalar_write_registerscalar_read_registerbasic_spr_register.cc[%s] %s:%d %s Model Interrupted by Exception. tick: {0:d}, write spr reg: {1:s}, {2:x}, value: {3:x}tick: {0:d}, read spr reg: {1:s}, {2:x}, value: {3:x} @"$&(*,.02468:<>BDFHJLNPRTVXZ\^`bdfhjlnprtvxz|~read_spr_registerwrite_spr_registersprEncodeToSpr@ -+   9BasicUnitbasic_unit.ccunknown register encode11BasicVector@             @                           @                        -+   basic_vector.cc6CACube*ZN6CACube9apply_memEvEUlPhE_*ZN6CACube9apply_memEvEUlPhE0_*ZN6CACube9apply_memEvEUlPhE1_*ZN6CACube9apply_memEvEUlPhE2_*ZN6CACube9apply_memEvEUlPhE3_*ZN6CACube9apply_memEvEUlPhE4_*ZN6CACube9apply_memEvEUlPhE5_@ apply_mem-+   *St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E1_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E2_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E3_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E4_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E5_SaIvELN9__gnu_cxx12_Lock_policyE2EEca_cube.cc cube : get_next_status_small_k wrong cube fsm ! cube : get_w_l0c_next_status_small_k wrong cube fsm !5CaLSUSt23_Sp_counted_ptr_inplaceI14BasicMteDecodeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15BasicMteExecuteSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11fmcd_para_tSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ build_configCaLSU            @                           @                        -+   ca_lsu.ccMTE, instr ID is: ca_lsu.cc:320, L1_3D_SIZE = 0ERROR SRC PORT!ERROR DST PORT!deque::_M_range_check: __n (which is %zu)>= this->size() (which is %zu)AIPP/UNZIP tick:{0:d}: {1:s}: addr = 0x{2:08x}, size = {3:x}, {4:s}, instr_id = {5:d}, retire_set = {6:d}11CA_LSU_AIPPSt23_Sp_counted_ptr_inplaceISt6vectorI10AIPP_PIXELSaIS1_EESaIS3_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceISt6vectorIS0_IhSaIhEESaIS2_EESaIS4_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14biuReadUopTypeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16AIPP_INNER_TRANSSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEcheck_paramprint_img_to_file@ build_rd_uopprepare_pad_setaipp_dtcaipp_data_sync_bitaipp_data_sync_byteinit_funcaipp_scfaipp_trimaipp_write_l1pad_areaaipp_paddinginit_exec            @                           @                        -+   ca_lsu_aipp.cc[%s] %s:%d %s ERROR: min/var_reci must be INF or NaN [%s] %s:%d %s ERROR: v_size should be even when YUV420 [%s] %s:%d %s ERROR: v_start should be even when YUV420 [%s] %s:%d %s ERROR: invalid h_res parameter [%s] %s:%d %s ERROR: invalid padding parameter ut_mte_aipp_debug_1%s/%s[%s] %s:%d %s open fail errno = %d ------------------------------------------------------------------------------------------------------------------------------------------- %02x llt/model/data/isg_data10CaLsuBiuIFSt23_Sp_counted_ptr_inplaceI9mte_uop_tSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ @ gen_biu_wr_dst_uopgen_rd_ub_uopgen_wr_req            @                           @                        build_config-+   tick: {0:08d}: AIPP UV: TAG_ID: {1:d}, UOP_SIZE: {2:d}ca_lsu_biu_if.ccdeque::_M_new_elements_at_backdeque::_M_new_elements_at_front[%s] %s:%d %s wr_uop is nullptr biu interface mte4 write valid !ca_lsu_biu_if.cc:641, CA MTE BIU IF: Error, wrong command generation state.ca_lsu_biu_if.cc:1293, ERROR PORTca_lsu_biu_if.cc:1128, req size = 0ca_lsu_biu_if.cc:884, resp size = 0tick: {0:d}, in_order_tag, otsd_num = {1:d}tick: {0:d}, outof_order_tag, otsd_num = {1:d}ca_lsu_biu_if.cc:467, CA MTE BIU IF: Error, wrong command generation state.tick: {0:d}. delete_fn_data_tn: tag_id: {1:d}, trans_id: {2:d}, cmd_id: {3:d}.tick: {0:d}, LAYOUT_BUF_OUT: INSTR_ID: {1:d}, IDX: {2:d}, ADDR: 0x{3:x}, RETIRE: {4:d}tick: {0:d}, LAYOUT_BUF_IN: TAG_ID: {1:d}, UOP_ID: {2:d}, INSTR_ID: {3:d}, ADDR: 0x{4:x}, IDX: {5:d}tick: {0:08d}: AIPP Y REQ: DATA_SIZE: {1:d}, TAG_ID: {2:d}, RETIRE_SET: {3:d}, BUF_SIZE: {4:d}tick: {0:08d}: AIPP UV REQ: DATA_SIZE: {1:d}, TAG_ID: {2:d}, RETIRE_SET: {3:d}, BUF_SIZE: {4:d}  "&,,0opDecode@             @                           @                        -+   12CmdSchedulerSt23_Sp_counted_ptr_inplaceI12cmdIssueTypeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEca_lsu_cmd_scheduler.ccca_lsu_cmd_scheduler.cc: 617, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 632, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 648, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 669, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 684, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 692, AIPP IS nullptr. poped from IQca_lsu_cmd_scheduler.cc: 459, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 93, ERROR MTE INSTR!ca_lsu_cmd_scheduler.cc: 146, MTE CMDSCHEDULER: ERROR, UNKNOWN CMD TYPE!ca_lsu_cmd_scheduler.cc: 707, AIPP IS WRONG SRC PORTca_lsu_cmd_scheduler.cc: 721, ERROR CMD TYPE!. pop success 18DepthWiseUopEngine@             @                           @                        -+   ca_lsu_depthwise_uop_engine.cc12DmaUopEngine@             @                           @                        -+   ca_lsu_dma_uop_engine.ccDmaUopEngineerror src id! ERROR SRC PORT13FmcdUopEngine@             @                           @                        -+   ca_lsu_fmcd_uop_engine.ccFmcdUopEngineca_lsu_fmcd_uop_engine.cc: 269, req_size = {0:d} != resp_size = {1:d}12FmdUopEngine@ gen_fmd_uop            @                           @                        -+   ca_lsu_fmd_uop_engine.ccFmdUopEngineca_lsu_fmd_uop_engine.cc: 94, fmd header is not emptyca_lsu_fmd_uop_engine.cc: 332, ERROR FMD DST PORT16Img2colUopEngine@             @                           @                        -+   ca_lsu_img2col_uop_engine.cc11CaInterface@ gen_wr_uopgen_biu_wr_uop            @                           @                        -+   ca_lsu_interface.ccca_lsu_interface.cc: 77, mte uop t is nullptr!ca_lsu_interface.cc: 82, band width is 0!16KSparseUopEngine@             @                           @                        -+   ca_lsu_ksparse_uop_engine.ccKSparseUopEngineSMASK WRITE13CaL0Interface@             @                           @                        -+   ca_lsu_l0_interface.ccDEPTH WRITEL0A WRITEL0B WRITELOC WRITE13CaL1Interface@ gen_aipp_write_info            @                           @                        sendWriteReq-+   ca_lsu_l1_interface.ccL1 INTF: ERROR DST PORTaipp adapter error instr idL1 BIU WRITEL1 UB WRITEERROR WRITE PORT!L1 READtick: {0:08d}, l1 write is back pressure by depthwise conv which may result hang up!15PlanarUopEngine@ __set2d_gen_uop            @                           @                        -+   ca_lsu_planar_uop_engine.ccca_lsu_planar_uop_engine.cc:135, ERROR DST PORTca_lsu_planar_uop_engine.cc:162, ERROR INSTR IN UE2D13CaUBInterface@             @                           @                        -+   sendWriteReqca_lsu_ub_interface.ccUB WRITEUB READtick:{0:d}: UB READ RESP: {1:s}, instr_id = {2:d}14UnzipUopEngineSt23_Sp_counted_ptr_inplaceI9LSUCmdReqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ uzp_cyclecheck_unzip_index_isa_para@ check_out_dst_unzip_isa_para@ gen_rd_uopdecode_cmduzp_high_sparseuzp_low_sparseuzp_struzp_quantuzp_cycleuzp_low_sparse_dictuzp_high_sparse_dictuzp_bypasschk_biu_idx_vlduzp_mte_wdatagenerate_uopbuild_configuzp_head            @                           @                        -+   ca_lsu_unzip_uop_engine.ccinput_len shoud be %u byte compress block data len %d shoud not be more than 64bit [%s] %s:%d %s memcpy_s failed, error num: %d, which j is %d [%s] %s:%d %s unzip index instr block num is 0. [%s] %s:%d %s unzip index src addr: 0x%lx not 2B aligned. [%s] %s:%d %s unzip index src addr: 0x%lx not 8B aligned. [%s] %s:%d %s dst = L0, dst_addr(0x%lx) + data_size(%d) >= L0_size(%d), addr wrapping. [%s] %s:%d %s dst = L0, dst_addr(0x%lx) >= L0_size(%d), addr wrapping. [%s] %s:%d %s dst = L1, dst_addr(0x%lx) + data_size(%d) >= L1_size(%d), addr wrapping. [%s] %s:%d %s offset flag is set but data size(%d) > 256B. [%s] %s:%d %s data size is 0. [%s] %s:%d %s data size(%d) > re-order buffer size(%d). instr_id: %d. [%s] %s:%d %s circulant_matrix_len is %d ,and will cause DIVIDE_BY_ZERO error [%s] %s:%d %s data_size is %d ,and should be n * %d in cycle mode [%s] %s:%d %s new (std::nothrow) unzip index instruction isssued before index used up, discarding all index and re-fetch. [%s] %s:%d %s unzip not finished but data is used up. [%s] %s:%d %s unzip sparse model length check failed. engine %u: %u UnzipUopEnginetick: , UNZIP INDEX is re-execute times by unzip engine.[%s] %s:%d %s index used up and no unzip index instruction issued ahead. , unzip index not enough, instr: will be retired directly[%s] %s:%d %s sparse mode with dict, unzip data size: %d per engine < 256/4. [%s] %s:%d %s sparse mode with unsigned dict. [%s] %s:%d %s quant mode without dict but unsigned flag set. [%s] %s:%d %s cmp flag in head indicates data is not compressed. 9UopEngineSt23_Sp_counted_ptr_inplaceI15biuWriteUopTypeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ gen_rd_uopset_uop_to_biuWIntfset_uop_to_biuRIntf            @                           @                        -+   ca_lsu_uop_engine.ccca_lsu_uop_engine.cc:67, Wrong UE Type.ca_lsu_uop_engine.cc:115, Wrong UE Type.BasicUopEngine17WinogradUopEngine@             @                           @                        -+   ca_lsu_winograd_uop_engine.ccexcuteUop_readDeltaexcuteRdbuff_VADD_DownexcuteRdbuff_VADD_TOPgenerateUopalign_buffer_offsetgen_write_mask@ excuteUop_readFeature                               9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+   7tagFp16ca_vec_col2img_uop_engine.cc[%s] %s:%d %s memset_s failed, error num: %d [%s] %s:%d %s img2col error, stride_w = 0, forced to 1. [%s] %s:%d %s img2col error, stride_h = 0, forced to 1. [%s] %s:%d %s img2col error, dialtion_w = 0, forced to 1. [%s] %s:%d %s img2col error, dialtion_h = 0, forced to 1. [%s] %s:%d %s fetch position: (%d, %d) in filter >= kernal size: (%d, %d). [%s] %s:%d %s img2col error, fm_w: %d or fm_h: %d is 0. [%s] %s:%d %s img2col error, dilated filter size: (%d, %d) > fm size: (%d, %d). [%s] %s:%d %s img2col error, 1st filter width position: %d > fm_w + pad_right - dilated_filter_width. [%s] %s:%d %s img2col error, 1st filter height position: %d > fm_h + pad_bottom - dilated_filter_height. [%s] %s:%d %s img2col error, 1st filter position(%d, %d) < -255. emuuuuuuuuuuuuuuu%euu-7--77uuuuuuuuuuuuAuuuuuuuKK7AAAuuUUuu]uuuuuuuubuild_config@                                9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+   gen_uops_read_onlygen_uops_sprgen_uops_write_onlygen_uops_ub2ubgen_uops_dpf16_mergegen_uops_dma_mcbgen_uops_vdpgen_uops_v4dtransgen_uops_vbigen_uops_commongen_uops_objdet_type2gen_uops_vms4gen_uops_dmagen_uops_specialgen_uops_vscgen_uops_vgather_vscattergen_uops_three_instrgen_uops_objdet_type3gen_uops_objdetissue_uop8CaVectorSt23_Sp_counted_ptr_inplaceIN8CaVector16VecPreRetireInfoESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7VEC_UOPSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12Vms4ListInfoSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11Vms4BufInfoSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14Vms4OutBufInfoSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEca_vector.cctick: {0:d}, deqscale_pre: 0x{1:x}, deqscale_next: 0x{2:x}, mcb_pre: 0x{3:x}, mcb_next: 0x{4:x}, burst_idx: 0x{5:x},tick: {0:d}, bInstrFusion: {1:d}, is_src_same: {1:d}, is_h_suprt: {1:d}, is_data_suprt: {1:d}, is_dst_addr_suprt: {1:d}, is_mcb_suprt: {1:d}tick: {0:d}, bInstrFusion: {1:d}, is_mcb_suprt: {1:d}, DMA_MOV can't fusion since mcb is different!tick: {0:d}, uop->id:{1:d}, Err fusion type.tick: {0:d}, uop_mode1_perf_dble: {1:d}, this pair don't support.tick: {0:d}, uop_mode1_perf_dble: {1:d}, is_src0_suprt_mode1: {2:d}, is_src1_suprt_mode1: {3:d}, is_dst_suprt_mode1: {4:d}, two_src_dif_linetype: {5:d}.=============vms4_trigger_rd, send_rd_req, tick is:{0:d},list_idx is:{1:d},uop->repeat_time is:{2:d},start_addr is:0x{3:x}==================================vms4_trigger_rd, send_rd_req, tick is:{0:d},list is:{1:d},buf is:{2:d},cur_rd_size is:{3:d},start_addris:0x{4:x},uop->ub_rd0_req_id is:{5:d},cur_list->list_pre_rd_size is:{6:d},list_total_size is:{7:d}================================== vms4_check_rd_req, rd_req_arbit_suc, tick is:{0:d},list is:{1:d},list_buf is:{2:d},rd_req_id is:{3:d} ================================== tick is:{0:d},vms4_check_rd_buf, rd_req_cpmplete, repeat is:{1:d},list is:{2:d},buf is:{3:d},buf_rd_req_size is:{4:d},buf_size_cnt is:{5:d},is_list_rd_end is:{6:d}=====================++++++++++++++++vms4_check_wr_req, wr_req_completed, tick is:{0:d},out_buf_idx is:{1:d},uop->ub_wr_req_id is:{2:d}++++++++++++++++------------ CaVector::vms4_check_wr_req,set is_list_wr_end, tick is:{0:d},list is:{1:d},wr_end_req_id is:{2:d} ---------------------------------- CaVector::vms4_rd_proc,rdy_to_rd,send_rd_req,step2 tick is:{0:d} ---------------------------------- CaVector::vms4_rd_proc,rdy_to_rd,step3 tick is:{0:d},vms4_rd_proc_list_id is:{1:d},vms4_rd_proc_buf_id is:{2:d} ---------------------------------- CaVector::vms4_rd_proc,send_rd_req,step4 tick is:{0:d},vms4_rd_proc_list_id is:{1:d},vms4_rd_proc_buf_id is:{2:d} ----------------------tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},burst_num: {6:d},burst_len: {7:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},burst_num: {6:d},burst_len: {7:d},conv_relu: {8:d},lrelu_ctrl: {9:d},on_fly_ctl: {10:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},burst_num: {6:d},burst_len: {7:d},h: {8:d},conv_relu: {9:d},brc_rpt_ctrl: {10:d},on_fly_ctl: {11:d},on_fly_op_mode: {12:d},lrelu_ctrl: {13:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},mode: {6:d},C: {7:d},image_size: {8:d},ele_size: {9:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d}, vbi_rep_mode: {6:d}, v_rep_num: {7:d}, h_rep_num: {8:d},MASK_mode: {9:d},MASK[0]: 0x{10:x},MASK[1]: 0x{11:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},VSEL_mode: {6:d},MASK_mode: {7:d},MASK[0]: 0x{8:x},MASK[1]: 0x{9:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},reduce_mode: {6:d},src1_rep_std: {7:d},MASK_mode: {8:d},MASK[0]: 0x{9:x},MASK[1]: 0x{10:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},s16_bit_extend: {6:d},MASK_mode: {7:d},MASK[0]: 0x{8:x},MASK[1]: 0x{9:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},reg_type: {6:d},region_prop_ctrl: 0x{7:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d},vms4_type: {4:d},vms4_mask: {5:d},list0_size: {6:d},list1_size: {7:d},list2_size: {8:d},list3_size: {9:d},region_size: {10:d}//---UOP Info ----------------------------------------------------UOP issue tick is:{0:d}UOP id is:{0:d}UOP ub_rd0 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_rd1 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP special rd,ub_rd1 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_wr_req masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_rd2 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_rd3 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_wr1_req masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP rd_latency is:{0:d}UOP exe_latency is:{0:d}UOP wr_latency is:{0:d}UOP stage is:{0:d}UOP retire stage is:{0:d}UOP back_pressue cycle is:{0:d}UOP read_conflict_cycle is:{0:d}UOP valu_conflict_cycle is:{0:d}UOP order_conflict_cycle is:{0:d}UOP throughput_conflict_cycle is:{0:d}UOP var_valu_conflict_cycle is:{0:d}UOP wr_conflict_cycle is:{0:d}UOP bypass_iss_delay is:{0:d}UOP repeat_time is:{0:d}UOP src1 value bypassed:{0:d}UOP dst value bypassed:{0:d}UOP dma_vdeq_burstn_uop0_delay:{0:d}UOP dma_vdeq_burst_uop0_rd_ub_cflt:{0:d}UOP dma_vdeq_burst_uop0_rd_ub_delay:{0:d}UOP vexp_vln_delay:{0:d}UOP viou_vaadd_iss_delay:{0:d}UOP special_instr_iss_delay:{0:d}++++++++++++++++ vms4_trigger_wr, set wr_end_req_id, tick is:{0:d},list is:{1:d},wr_end_req_id is:{2:d}++++++++++++++++++++++++++++++++ vms4_trigger_wr, can't set wr_end_req_id! tick is:{0:d},list is:{1:d},wr_end_req_id is:{2:d},is_list_sort_end is:{3:d},sort_proc_rdy_to_wr is:{4:d},wr_proc_rdy_to_wr is:{5:d}++++++++++++++++++++++++++++++++ vms4_trigger_wr, send_wr_req, tick is:{0:d},out_buf_idx is:{1:d},wr_size is:{2:d},uop->ub_wr_req_id is:{3:d},start_addr is:0x{4:x}++++++++++++++++------------ CaVector::vms4_sort_proc,sort_proc_rdy_to_wr,send_wr_req,step1 tick is:{0:d} ---------------------------------- CaVector::vms4_sort_proc,wr_proc_rdy_to_wr,send_wr_req,step2 tick is:{0:d} ----------------------*******************vms4_sort_proc, sort_procing, tick is:{0:d},repeat is:{1:d},sort out list is:{2:d},sort out list_buf is:{3:d}, out buf is:{4:d},uop->isa_info->vms4_cur_sort_id is:{5:d}*******************------------ CaVector::vms4_sort_proc,rdy_to_wr,step3 tick is:{0:d} ---------------------------------- CaVector::vms4_wr_proc,rdy_to_wr,send_wr_req,step2 tick is:{0:d} ---------------------------------- CaVector::vms4_wr_proc,rdy_to_wr,step3 tick is:{0:d} ----------------------tick: {0:d}, UOP id is:{1:d}, l0c_wr_req_id is:{2:d},l0c_wr_proc_len is:{3:d}tick: {0:d}, UOP id is:{1:d}, ub_wr_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, uop->id:{1:d}, uop->l0c_wr_req_id:{2:d}, uop wr latency == 0, while L0C wr not completed.tick: {0:d}, uop->id:{1:d}, uop->ub_wr_req_id:{2:d}, uop wr latency == 0, while UB wr not completed.tick: {0:d}, UOP id is:{1:d}, ub_rd0_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, UOP id is:{1:d}, ub_rd1_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, UOP id is:{1:d}, VDEQ ub_rd0_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, UOP id is:{1:d}, l0c_rd0_req_id is:{2:d},l0c_rd0_proc_len is:{3:d}tick: {0:d}, UOP id is:{1:d}, src0 rd is optimizedtick: {0:d}, UOP id is:{1:d}, ub_rd2_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, UOP id is:{1:d}, src2 rd is optimizedtick: {0:d}, UOP id is:{1:d}, ub_rd3_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, retire set_deqtick: {0:d}, retire instr1tick: {0:d}, I1 step2, decodetick: {0:d}, uop->id:{1:d}, VDEQ step1.tick: {0:d}, uop->id:{1:d}, VDEQ step2.tick: {0:d}, uop->id:{1:d}, VDEQ step3.tick: {0:d}, uop->id:{1:d}, VDEQ step4.tick: {0:d}, uop->id:{1:d}, VDEQ step5.tick: {0:d}, uop->id:{1:d}, VDEQ step6.tick: {0:d}, uop->id:{1:d}, VDEQ step7.tick: {0:d}, uop->id:{1:d}, is_uop_rd_invalid:{2:d}, is_uop_wr_invalid:{3:d}.bypass delay check step4,tick: {0:d}, UOP id is:{1:d}, UOP vbi_h_repeat_idx is:{2:d},pre_uop_issue_cyc is:{3:d},pre_uop_issue_rpt is:{4:d}bypass delay check step5,tick: {0:d}, UOP id is:{1:d}, UOP vbi_h_repeat_idx is:{2:d},pre_uop_issue_cyc is:{3:d},pre_uop_issue_rpt is:{4:d}bypass delay check step4,tick: {0:d}, UOP id is:{1:d}, UOP repeat_time is:{2:d},pre_uop_issue_cyc is:{3:d},pre_uop_issue_rpt is:{4:d}bypass delay check step5,tick: {0:d}, UOP id is:{1:d}, UOP repeat_time is:{2:d},pre_uop_issue_cyc is:{3:d},pre_uop_issue_rpt is:{4:d}gc_[WSPLI=951-)%! l7 7 zz7tt7.....vvvvvvvv&&&&vvvV6 fvvvv4vvvnvNNvB ^,,vv44@                                9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+     proc10VecDecoderSt23_Sp_counted_ptr_inplaceI12VEC_ISA_INFOSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEvec_decoder.ccillegal cfg about the list_en paramillegal cfg about the isa_info->size0 paramillegal cfg about the isa_info->size1 paramillegal cfg about the isa_info->size2 paramillegal cfg about the isa_info->size3 paramillegal cfg about the repeatTime paramillegal cfg about the list_en param when (exhaust_en==1 && repeat_time>1)illegal cfg about the list_size param when (exhaust_en==1 && repeat_time>1)use MINI tablethis dma instr not supportthis dma conv_relu not support, conv_relu: vec_instr_illegal_cfg: {0:s}, id: {1:d}[NOT SUPPORT] instr {0:s}, conv_type: DEQ, id: {1:d} not support in h200 bitset::set%s: __position (which is %zu) >= _Nb (which is %zu)vec_illegal_mask: {0:s}, id: {1:d}vec_instr_undef: {0:s}, id: {1:d}[NOT SUPPORT] instr {0:s} conv_relu: {1:02x}, id: {2:d} not support in h200[NOT SUPPORT] instr {0:s} on-the-fly calculation, id: {1:d} not support in h200[NOT SUPPORT] instr {0:s} L0CDPF16 to UB, id: {1:d} not support in h200[NOT SUPPORT] instr {0:s} leaky-relu, id: {1:d} not support in h200vec: ccu_addr_err: {0:s}, addr: 0x{1:08x} is overflow ub buffer size, id: {2:d}vec: ccu_addr_err: {0:s}, addr: 0x{1:08x} is overflow l0c buffer size, id: {2:d}vec_instr_illegal_cfg: {0:s}, don't support op_cal! on-the-fly operation should be 0, id: {2:d}vec_instr_illegal_cfg: {0:s}, conv_relu don't support op_cal! on-the-fly operation should be 0, id: {2:d}vec_instr_illegal_cfg: instr {0:s}, burst_len can't be 0, id: {1:d}src1_start_line: src1_end_line: dst_start_line: dst_end_line:vec_instr_illegal_cfg: {0:s}, on_fly_cal src UB and dst UB addr cflt, id: {1:d}vec_instr_addr_misalign: {0:s}, on_fly_cal dst addr 0x{1:08x}is not 32B aligned!, id: {2:d}[NOT SUPPORT] instr {0:s}, id: {1:d} not support in h200@@@@@MMMMP(tFM6FFFFF.#~s6+{&bWRG ZOxm h] peLA<1D9vkJ?`U4)@                                9 R S   /  - . < 1 / / 4 >  0 /-.   9 R R S S   9 : 0 < 1 / / > R R R S S S - . /      -./<1//>RRRSSS 9:0RS99990RRRSSS<1//>  90://>>RRSS 90://>>RRSS 904 90490://>>RRSS90://>>RRSS0RRRSSS-./<1//> 9:4-./4-./9:< 1 / / >  0   R R R R S S S 9:<1//>0 RRRRSSS-./4-./4 90:RRRRSSSS 90:RRRRSSSS0RRRSSS            0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- @--(( @((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @-@-(( @(@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @    9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                                                                                        -+   mov_l0c_ub_opmov_l0c_ub_opmov_l0c_ub_opmov_l0c_ub_opexec_vms4exec_mov_l0c_ub8ARITH_OPI7tagFp16aE8ARITH_OPI7tagFp16hE8ARITH_OPIj7tagFp16E8ARITH_OPI7tagFp16jE8ARITH_OPIiiE8ARITH_OPIi7tagFp16E8ARITH_OPIjjE8ARITH_OPIshE8ARITH_OPI7tagFp16S0_E6DIV_OPI7tagFp16S0_E6MLA_OPI7tagFp16jE9VecPVFunc8LRELU_OPI7tagFp16S0_E7RELU_OPI7tagFp16S0_E8LRELU_OPIjjE6MUL_OPI7tagFp16S0_E7RELU_OPIjjE6EXP_OPI7tagFp16S0_E6EXP_OPIjjE7SQRT_OPI7tagFp16S0_E7SQRT_OPIjjE8RSQRT_OPI7tagFp16S0_E8RSQRT_OPIjjE7RELU_OPIiiE6REC_OPI7tagFp16S0_E6REC_OPIjjE5LN_OPI7tagFp16S0_E5LN_OPIjjE6ABS_OPI7tagFp16S0_E6ABS_OPIjjE8ARITH_OPIssE6ABS_OPIssE6ADD_OPI7tagFp16S0_E6ADD_OPIjjE6MAX_OPI7tagFp16S0_E6MAX_OPIjjE6MAX_OPIssE6MIN_OPI7tagFp16S0_E6MIN_OPIjjE6MIN_OPIssE6NOT_OPIssE6MAX_OPIiiE6MIN_OPIiiE6ADD_OPIiiE6ADD_OPIssE6MUL_OPIiiE6MUL_OPIssE6MUL_OPIjjE6SUB_OPI7tagFp16S0_E6SUB_OPIiiE6SUB_OPIssE6SUB_OPIjjE10ADDRELU_OPI7tagFp16S0_E10ADDRELU_OPIssE10ADDRELU_OPIjjE10ADDRELU_OPIiiE10SUBRELU_OPI7tagFp16S0_E10SUBRELU_OPIssE10SUBRELU_OPIjjE10SUBRELU_OPIiiE8ARITH_OPIsaE14ADDRELUCONV_OPIsaE14ADDRELUCONV_OPI7tagFp16aE14ADDRELUCONV_OPIj7tagFp16E14ADDRELUCONV_OPIshE14SUBRELUCONV_OPIsaE14SUBRELUCONV_OPI7tagFp16aE14SUBRELUCONV_OPIj7tagFp16E14SUBRELUCONV_OPIshE6DIV_OPIjjE11MUL_CONV_OPI7tagFp16aE11MUL_CONV_OPI7tagFp16hE15ADD_DEQ_RELU_OPIi7tagFp16E7AXPY_OPI7tagFp16S0_E7AXPY_OPIjjE7AXPY_OPI7tagFp16jE6CMP_OPI7tagFp16S0_E6CMP_OPIjjE6CMP_OPIssE6SHR_OPIiiE6SHR_OPIjjE6SHR_OPIssE8ARITH_OPIttE6SHR_OPIttE6SHL_OPIttE6SHL_OPIjjE5OR_OPIssE6AND_OPIssE6MLA_OPI7tagFp16S0_E6MLA_OPIjjE7MADD_OPI7tagFp16S0_E7MADD_OPIjjE12MADD_RELU_OPI7tagFp16S0_E12MADD_RELU_OPIjjE6MOV_OPIssE7RELU_OPIssEvec_pv_func.ccvec_ub_wrap_around: instr {0:s}, burst_len can't be 0, id: {1:d}VecPVFunc: instr {0:s}, memcpy_s error, id: {1:d}N10AiCorePSim24AiCoreSimThreadContainerETickAiCoreThreadEntry@ Start-+   aicore_psim.cc[%s] %s:%d %s Error in running AiCoreIdx=%d, ChipId=%d [%s] %s:%d %s Array new (std::nothrow) or free array! 10aicpu_core@ -+   aicpu_core.cctoml::Value::Value(toml::Value&&)toml::Value& toml::Value::operator=(toml::Value&&)const toml::Value* toml::Value::findChild(const string&) consttoml::Value::Value(const toml::Value&)toml::Value& toml::Value::operator=(const toml::Value&)toml::Value* toml::Value::findChild(const string&)encountered non table valueinvalid keytype must be array to do push(Value).type must be table to do set(key, v).cfg.cpptype check failedunexpected tokeninline table didn't have ',' for delimiter?inline table has multiple same keys: key=Error: line could not open file: stream is in bad state. file does not exist?Invalid UTF8 BOMerror when parsing group keyparse key failedno equal?Multiple same key: error when parsing key Valuebasic_string::erase[error] Failed to find config tab: [error] Config file is invalid. Path: Reason:  QtU >0)+5sHc #V&)Z(-o03s7}:d=`AD+jHK'OBSsV}Zv^Gb#f j#m^quGz3/~XTΊ{s*ؗIgƠ;P+:o rr`sJe|Q73EmqH(19BLBU^gpq {v|ܶ7C 6#*/:FR^jw֜#<2@]O+^!mB| +6BNZfr-;JYhw(9J\m*>Rf{G3H@`>>A~@~i?[INFO] operator library version: 20191112-1O@GG~~}|{zyyxwvvutsrrqpoonmmlkjihgedca`_]\[ZXWVUTRQPONMLKJHGFEDCBA@?>=<<;:98765433210/..-,+**)('&&%$##"!!          6TUUUTUUU~~}|{zyyxwvvutsrrqpoonmmlkjihgedca`_]\[ZXWVUTRQPONMLKJHGFEDCBA@?>=<<;:98765433210/..-,+**)('&&%$##"!!          & 5lF!V- 8tDP\h!u⎁Yњ}j-i!/l> M[jy!'zEμfb g6Q9+k<M`_a$q@֚'fL7-SA7Vyj% +a 6 DU t ̔   9 [ N~ " W G0 U 5z ǟ & 2:azs.Y׃3`S}+J]zW!v@XsǦTvD,zx[Vv=xu$Q~ 9i/a2g C|)dVT\*pG%q YI@dRet : %lfget_omg_pathopen_fp_fileload_fp_filefp_file_op.cc[%s] %s:%d %s hiai_install_file is too long /runtime/bin/[%s] %s:%d %s strcat failed, errno is: %d [%s] %s:%d %s strcpy_s failed, errno is: %d ./model/pv_model/src/base/fp/data/fp32_ln.dat[%s] %s:%d %s strcpy_s failed, err = %d File: %s, file path is wrongCan't Open fp32_ln.dat! !./model/pv_model/src/base/fp/data/fp32_exp.datCan't Open fp32_exp.dat! !./model/pv_model/src/base/fp/data/fp16_ln.datCan't Open fp16_ln.dat! !./model/pv_model/src/base/fp/data/fp16_exp.datCan't Open fp16_exp.dat! !The fp file type is not supported! fp32_ln_cache: malloc failed fp32_exp_cache: malloc failed fp16_ln_cache: malloc failed fp16_exp_cache: malloc failed 17BasicBusInterfaceinit@ -+   directWriteAiCoredirectWriteAivCoredirectWriteAicpuCorebasic_bus_interface.cc[{0:010d}] [hwts : {1:d} : {2:s}] Write registers of ai core {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] Write registers of aiv core {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] Write registers of aicpu core {3:d}, mailbox addr = {4:x}  @ 0@Pp 0@Pp 0@Pp 0@Pp 0@Pp  0 @ P p  0@Pp 0@Pp 0@Pp 0@Pp 0@Pp 0@Pp  0 @ P p  0@Pp 0@Pp 0@Pp 0@Pp 0@Ppproc_host_l2_normal_setclr_maskXsetRegisterDefaultValueReadModWriteRegPendingRegisterSynchronizationwriteReg@ BasicHwts-+   write_entry_bitfindL1MaskaxiExcepInterruptassert_pre_pause_interruptassert_post_pause_interruptsqcq_state_killwait_proc_assert_sq_empty_interruptassert_cq_full_interruptassert_task_paused_interruptremove_aicore_from_idle_listassert_event_record_interruptprint_sq_update_head_cntextract_sqe_formatupdate_event_table_bits_registerupdate_notify_table_bits_registersq_update_head_registercq_updatesqcq_state_ctrl_procsqe_state_init_proc_sqcq_state_pause_proc_sq_event_table_pollingsq_notify_table_pollingsimplify_sqcq_state_proc_req_active_sq_idfree_active_sq_idticktask_blk_fsmsend_sdma_donesq_active_req_swapin_opbuildfull_sqcq_state_proc_sq_prefetchreadExtwriteExt@P 0p@P 0ptaskDoneInterrupttaskErrorInterrupt9BasicHwtsSt23_Sp_counted_ptr_inplaceI15block_schedulerSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI19hwts_sdma_schedulerSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI19hwts_virtualizationSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceISt6vectorIjSaIjEESaIS2_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15BasicQueueEntrySaIS0_ELN9__gnu_cxx12_Lock_policyE2EEbasic_hwts.ccProject.name[{0:010d}] [hwts : {1:d} : {2:s}] entry id cannot larger than 1024 : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] Can't find l1 mask according to l2 register.[{0:010d}] [hwts : {1:d} : {2:s}] In axiExcepInterrupt()! call threadBlockDoneInterrupt![{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} task pre pause interrupt asserts[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} task post pause interrupt asserts[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} task resume[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} SQ empty interrupt asserts[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} CQ full interrupt asserts[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} task paused interrupt asserts[{0:010d}] [hwts : {1:d} : {2:s}] basic_hwts: AIC core_id: 0x{3:x} is not in idle ai core queue.[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} event record Interrupt[{0:010d}] [hwts : {1:d} : {2:s}] slot_idx = {3:d}, cur_head_cnt = {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] num_ext_pkt = {3:d}, interrupt_en = {4:d}, pre_p = {5:d}, post_p = {6:d}, type = {7:d}, block_dimen = {8:d}, sub_stream_id = {9:d}, task_id = {10:d}[{0:010d}] [hwts : {1:d} : {2:s}] error: Invalid SQE type, message type {3:d} is unsupported.[{0:010d}] [hwts : {1:d} : {2:s}] address wrap around SQ bound : sqe_cur_addr=0x{3:x}, bound_addr=0x{4:x}[{0:010d}] [hwts : {1:d} : {2:s}] Invalid SQ ID 0x{3:x}.[{0:010d}] [hwts : {1:d} : {2:s}] Invalid EVENT ID 0x{3:x}.[{0:010d}] [hwts : {1:d} : {2:s}] SQ[{3:d}] TYPE_SQE_FORMAT_EVENT_REC -> COMPLETE event id:{4:d} completes normally[{0:010d}] [hwts : {1:d} : {2:s}] SQ[{3:d}] TYPE_SQE_FORMAT_WAIT_EVENT -> COMPLETE event id:{4:d} completes normally[{0:010d}] [hwts : {1:d} : {2:s}] SQ[{3:d}] TYPE_SQE_FORMAT_WAIT_EVENT -> PAUSE event id:{4:d} set pending flag[{0:010d}] [hwts : {1:d} : {2:s}] Invalid SQE tyoe 0x{3:x}.[{0:010d}] [hwts : {1:d} : {2:s}] Invalid Notify ID 0x{3:x}.[{0:010d}] [hwts : {1:d} : {2:s}] SQ[{3:d}] TYPE_SQE_FORMAT_NOTIFY_REC -> COMPLETE event id:{4:d} completes normally[{0:010d}] [hwts : {1:d} : {2:s}] SQ[{3:d}] TYPE_SQE_FORMAT_WAIT_NOTIFY -> COMPLETE event id:{4:d} completes normally[{0:010d}] [hwts : {1:d} : {2:s}] SQ[{3:d}] TYPE_SQE_FORMAT_WAIT_NOTIFY -> PAUSE event id:{4:d} set notify flag[{0:010d}] [hwts : {1:d} : {2:s}] sq_slot_id={3:d}, sq_head={4:d}[{0:010d}] [hwts : {1:d} : {2:s}] Update head register. sq_slot_id={3:d}, task_type={4:d}, step={5:d}, sq_head={6:d}, sq_head_pre={7:d}, sq_tail={8:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq_head_update : SQ[{3:d}] is disabled.[{0:010d}] [hwts : {1:d} : {2:s}] cq_head={3:d}, cq_tail={4:d}, cq_length={5:d}, cqe_task_id={6:d}[{0:010d}] [hwts : {1:d} : {2:s}] cq_base_addr=0x{3:x}, cq_curr_addr=0x{4:x}, cq_bound_addr=0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] cqe_task_id={3:d}, sq_head_pre={4:d}, cq_head={5:d}, cq_tail={6:d}, cq_length={7:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} prefetch clear[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} enable task kill-wait state[{0:010d}] [hwts : {1:d} : {2:s}] GET sq slot ID:{3:d} Active SQ remained: {4:d}. Active SQ grant flag:{5:d} task_id:{6:d}[{0:010d}] [hwts : {1:d} : {2:s}] cq_head: {3:d}, cq_len: {4:d}, cq_tail: {5:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} CQ full insterrupt asserts.[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} enable task pre-pause state[{0:010d}] [hwts : {1:d} : {2:s}] Cannot get core: num({3:d}) slot ID:{4:d} type {5:d} message [{:010d}] [task_start] : RTSQ={:d}, task_type={:d}, task_id={:d}, blkdim={:d}[{:010d}] [task_start] : RTSQ={:d}, task_type={:d}, task_id={:d}[{0:010d}] [task_error] : RTSQ={:d}, task_type={:d}, task_id={:d}, sdma_scheduler_ is null[{0:010d}] [hwts : {1:d} : {2:s}] nullptr sdma_scheduler_ pointer!!:{3:d} get type {4:d} message [{0:010d}] [hwts : {1:d} : {2:s}] TASK PAUSE -> IDLE sq slot ID:{3:d} pre_p task resume[{0:010d}] [hwts : {1:d} : {2:s}] TASK PAUSE -> IDLE sq slot ID:{3:d} cq full task resume[{0:010d}] [hwts : {1:d} : {2:s}] TASK PAUSE -> POST_P_END sq slot ID:{3:d} post_p task resume[{0:010d}] [hwts : {1:d} : {2:s}] TASK PAUSE -> RUNNING sq slot ID:{3:d} normal task resume[{0:010d}] [hwts : {1:d} : {2:s}] TASK PASUE -> SQCQ_TASK_PENDING_SWAP_IN_STATE SQ Id:{3:d}, wait EVENT id {4:d} type:{5:d} task resume[{0:010d}] [hwts : {1:d} : {2:s}] TASK PASUE -> RUNNING SQ Id:{3:d}, wait NOTIFY id {4:d} type:{5:d} task resume[{0:010d}] [hwts : {1:d} : {2:s}] SQ slot id:{3:d},SQCQ_TASK_PENDING_SWAP_IN_STATE -> SQCQ_TASK_RUNNING_STATE, type {4:d}, map Active SQ Id:{5:d}[{0:010d}] [hwts : {1:d} : {2:s}] No more active SQ. Doorbell SQ id={3:d}[{0:010d}] [hwts : {1:d} : {2:s}] doorbell_sq_id = {3:d} goes to FULL sq fsm.[{0:010d}] [hwts : {1:d} : {2:s}] doorbell_sq_id = {3:d} goes to SIMPLIFIED sq fsm.[{0:010d}] [hwts : {1:d} : {2:s}] error: complete cannot find SQ ID {3:d} in active_sq list. Type:{4:d} message, sq_en {5:x}[{0:010d}] [hwts : {1:d} : {2:s}] free up SQ ID {3:d} in active_sq list successfully. Type:{4:d} message, sq_en {5:x}[{0:010d}] [hwts : {1:d} : {2:s}] bus_port_ is nullptr [{0:010d}] [hwts : {1:d} : {2:s}] nullptr sq_ts_slot slot id = {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] nullptr cur_active_qentry slot id = {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] send sdma done to channel {3:d}.[{0:010d}] [hwts : {1:d} : {2:s}] Requesting Doorbell sq id={3:d} maps to Active sq id=0x{4:x}.[{0:010d}] [hwts : {1:d} : {2:s}] Existing active sq id. Doorbell sq id={3:d} maps to Active sq id=0x{4:x}.hwts_log[{0:010d}] [hwts : {1:d} : {2:s}] hwts sqe size is 64B mode. val=0x{3:x}[{0:010d}] [hwts : {1:d} : {2:s}] hwts sqe size is 128B mode. val=0x{3:x}[{0:010d}] [hwts : {1:d} : {2:s}] sqid {3:d} is paused[{0:010d}] [hwts : {1:d} : {2:s}] MEMCPY STATE -> SQCQ_TASK_RUNNING_STATE:{3:d} get type {4:d} message [{0:010d}] [hwts : {1:d} : {2:s}] SQ slot id:{3:d}, write value address {4:x}, size {5:d}[{0:010d}] [hwts : {1:d} : {2:s}] SQ slot id:{3:d} , blk granted SQCQ_TASK_READY_STATE -> SQCQ_TASK_RUNNING_STATE, type {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] SQ slot id:{3:d} , block dim shouldn't be ZERO, back to idle via complete state. type {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} task paused actively, type {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] SDMA MEMCPY : running->complete, SQ ID {3:d} removed successfully. Type:{4:d} message[{0:010d}] [hwts : {1:d} : {2:s}] nullptr sdma_scheduler_ pointer!!r:{3:d} get type {4:d} message [{0:010d}] [hwts : {1:d} : {2:s}] Write value : running->complete, SQ ID {3:d} removed successfully. Type:{4:d} message[{0:010d}] [hwts : {1:d} : {2:s}] AIC CMD : running->complete, SQ ID:{3:d} task complete[{0:010d}] [hwts : {1:d} : {2:s}] SQCQ TASK COMPLETE! SQ slot id:{3:d}, task_id:{4:d} type:{5:d} complete.[{0:010d}] [hwts : {1:d} : {2:s}] Call taskDoneInterrupt, SQ={3:d}, task_id={4:d}, task_type:{5:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} enables post puase state, type {4:d}[{:010d}] [task_end] : RTSQ={:d}, task_type={:d}, task_id={:d}[{0:010d}] [hwts : {1:d} : {2:s}] SKIPPED!! cur_head_cnt SAME AS sq_tail!! NO MORE NEW SQE !doorbell_sq_idx={3:d}[{0:010d}] [hwts : {1:d} : {2:s}] s_queue_[{3:d}]->prev_head_cnt = {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] s_queue_[{3:d}]->cur_head_cnt = {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] N s_queue_[{3:d}]->cur_head_cnt = {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] N s_queue_[{3:d}]->prev_head_cnt = {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] N sq db = {3:d} sq_head = {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] N sq db = {3:d} sq_tail = {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] model:hwts:sq_base_addr = 0x{3:x}, sq_head :{4:d}, sq_tail : {5:d}, sq_length : {6:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq_curr_addr = 0x{3:x}, sq_bound_addr= 0x0x{4:x}[{0:010d}] [hwts : {1:d} : {2:s}] prev_head_cnt={3:d}, sq_head={4:d}, slot_idx={5:d}[{0:010d}] [hwts : {1:d} : {2:s}] cur_head_cnt=={3:d}, sq_tail={4:d}, slot_idx={5:d}[{0:010d}] [hwts : {1:d} : {2:s}] doorbell_sq_idx:{3:d} prefetch buffer full[{0:010d}] [hwts : {1:d} : {2:s}] PUSH SQE slot id({3:d}) sqe vector size({4:d}) <<<< cur_head_cnt({5:d}) task_id({6:d})[{0:010d}] [hwts : {1:d} : {2:s}] SQ id:{3:d} Prefetch buffer size is not enough: {4:d} , new (std::nothrow) used size: {5:d}[{0:010d}] [hwts : {1:d} : {2:s}] Active SQ list size: {3:d} , SQE num of entry: {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] general hwts register read HWTS_SLOT_IGNORE_ID, address : {3:x}, value : {4:x}[{0:010d}] [hwts : {1:d} : {2:s}] Done! read AICPU_BLK_CFG_NS, address:{3:x}, value:0x{4:x} aicpu:{5:d}[{0:010d}] [hwts : {1:d} : {2:s}] Done! read AICPU_BLK_CFG_S, address:{3:x}, value:0x{4:x} aicpu:{5:d}[%s] %s:%d %s pSQE is nullptr [%s] %s:%d %s Read prefetch: Doorbell SQ %d opcode = %d [{0:010d}] [hwts : {1:d} : {2:s}] slot id cannot larger than 1024 : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] active id cannot larger than {3:d} : {4:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq slot id cannot larger than 1024 : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] cq slot id cannot larger than 1024 : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq cq slot id cannot larger than 1024 : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_SQ_SEC_EN Secure mode enabled. slot id : {3:d} , address : {4:x}, value: {5:x}[{0:010d}] [hwts : {1:d} : {2:s}] non per SQ,CQ slot (0~1023) or per entry (0~1023) id : {3:d}, reg=0x{4:08X}, address=0x{5:08X}[{0:010d}] [hwts : {1:d} : {2:s}] hwts register read, slot id : {3:d}, address : {4:x}, value : {5:x}NS[{0:010d}] [hwts : {1:d} : {2:s}] Done! WRITE AICPU_BLK_CFG_NS, address:{3:x}, value:{4:x} aicpu:{5:d}[{0:010d}] [hwts : {1:d} : {2:s}] Done! WRITE AICPU_BLK_CFG_S, address:{3:x}, value:{4:x} aicpu:{5:d}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_CROSS_SOC_EVENT_TABLE is read only[{0:010d}] [hwts : {1:d} : {2:s}] general hwts register write HWTS_SLOT_IGNORE_ID, address : {3:x}, value : {4:x}[{0:010d}] [hwts : {1:d} : {2:s}] Clear L1 non secure normal interrupt! L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] Clear L1 secure normal interrupt! L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_NORMAL_{6:s}_MASK0_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_NORMAL_NS_MASK1_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_NORMAL_NS_MASK2_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_DEBUG_NS_MASK0_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_DEBUG_NS_MASK1_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_DEBUG_NS_MASK2_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_ERROR_NS_MASK0_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_ERROR_NS_MASK1_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_ERROR_NS_MASK2_SET L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_NORMAL_{6:s}_MASK0_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_NORMAL_NS_MASK1_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_NORMAL_NS_MASK2_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_DEBUG_NS_MASK0_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_DEBUG_NS_MASK1_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_DEBUG_NS_MASK2_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_ERROR_NS_MASK0_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_ERROR_NS_MASK1_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS_L1_ERROR_NS_MASK2_CLR L1 interrupt status : 0x{3:x}, L2 address : 0x{4:x}, L2 value : 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] hwts register write, slot id : {3:d}, address : {4:x}, value : {5:x}[{0:010d}] [hwts : {1:d} : {2:s}] sq slot id cannot larger than 52 : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] cq slot id cannot larger than 52 : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq cq slot id cannot larger than 52 : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] non per SQ,CQ slot (0~51) or per entry (0~1023) id : {3:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} sendInterrupt for sq slot, INT ID:{4:d}, status = 0x{5:x}[{0:010d}] [hwts : {1:d} : {2:s}] Send a norm interrupt to host {3:d}: type=0x{4:x}[{0:010d}] [hwts : {1:d} : {2:s}] Send a done interrupt to FW! q_slot_id : {3:d}, interrupt_type : {4:d}, done_reg_update_flag : {5:d}, task_type : {6:d}[{0:010d}] [hwts : {1:d} : {2:s}] sq slot ID:{3:d} sendInterrupt for sq slot, INT ID:{4:d}[{0:010d}] [hwts : {1:d} : {2:s}] Send an error interrupt to FW! q_slot_id : {3:d}, interrupt_type : {4:d}, error_reg_update_flag : {5:d}, task_type : {6:d}21BasicInterruptHandlerregTriggerInterruptregHostTriggerInterruptboExceptionType2Str@ aiCoreDoneInterruptaivCoreDoneInterruptaicpuCoreDoneInterrupt-+   basic_interrupt_handler.ccexternal_threadBlock_done_ callback function is called here! count : %u, slot_it : %u, interrupt_num : %hu [%s] %s:%d %s reg Trigger Interrupt is null [%s] %s:%d %s reg host Trigger Interrupt is null [%s] %s:%d %s host id is %u, which bigger than %u [%s] %s:%d %s SP_LEVEL_NUM_BO_EXCEPTION [%s] %s:%d %s TWO_TASK_OVERRIDE_BITMAP_CONFLICT_BO_EXCEPTIONI [%s] %s:%d %s MORE_THAN_2_TASK_EXEC_SIMULTANEOUSLY_BO_EXCEPTIOIN [%s] %s:%d %s PING_PONG_MODE_BO_EXCEPTION FATAL[%s] %s:%d %s unknow bo exceotion Type [%s] %s:%d %s basic_interrupt_handler.cc: returned done Ai Core Num is invalid. [%s] %s:%d %s basic_interrupt_handler.cc: returned done AIV Core Num is invalid. [%s] %s:%d %s basic_interrupt_handler.cc: returned done AICPU Core Num is invalid. 15BasicQueueEntry@ BasicQueueEntry-+   setInterruptNumgetAndResetInterruptNumbasic_qentry.cc[{0:010d}] [hwts : {1:d} : {2:s}] setInterruptNum {3:d} [{0:010d}] [hwts : {1:d} : {2:s}] getInterruptNum {3:d} resetInterruptNum {4:d}12SQCQTaskSlot@ SQCQTaskSlot-+   sendTask2AiCoresendTask2AivCoresendTask2AicpuCoresetInterruptNumgetAndResetInterruptNumserveAiCoreDonetaskBlkFsmPerSlottaskBlockRunningget_next_blkidbasic_task_slot.h: core_id: 0x is not in busy ai core queuecore_id: 0x is not in ready_ai_core_ queuebasic_qtask_slot.cc[{0:010d}] [hwts : {1:d} : {2:s}] HWTS scheduler alloc AI Core {3:d} to sq slot {4:d}, blk id {5:d}[%s] %s:%d %s BS Slot alloc AI Core %d to task slot %d, blk id %d [{0:010d}] [hwts : {1:d} : {2:s}] HWTS scheduler alloc AIV Core {3:d} to sq slot {4:d}, blk id {5:d}[%s] %s:%d %s BS Slot alloc AIV Core %d to task slot %d, blk id %d [{0:010d}] [hwts : {1:d} : {2:s}] HWTS re-use AICPU Core {3:d} to sq slot {4:d}, blk id {5:d}[{0:010d}] [hwts : {1:d} : {2:s}] HWTS scheduler alloc AICPU Core {3:d} to sq slot {4:d}, blk id {5:d}[%s] %s:%d %s BS Slot alloc AICPU Core %d to task slot %d, blk id %d [{0:010d}] [hwts : {1:d} : {2:s}] setInterruptNum {3:d} [{:010d}] [block_end] : RTSQ={:d}, task_type={:d}, task_id={:d}, blkID={:d}, coreID={:d}, sub_stream_id={:d}, remain_blk_num={:d}[{0:010d}] [hwts : {1:d} : {2:s}] block is completed. cur_block_id({3:d}) curRunningBlockNum({4:d}) remain blk({5:d})[{0:010d}] [hwts : {1:d} : {2:s}] cur_active_qentry is null pointer. cur_block_id({3:d})[{0:010d}] [hwts : {1:d} : {2:s}] slot:{3:d} is already occupied.[{0:010d}] [hwts : {1:d} : {2:s}] alloc_table_ is nullptr [%s] %s:%d %s SQCQTaskSlot::taskBlockRunning task_typed error!!! [{0:010d}] [hwts : {1:d} : {2:s}] task_typed error!!![%s] %s:%d %s idle core or alloc table is null [{:010d}] [block_start] : RTSQ={:d}, task_type={:d}, task_id={:d}, blkID={:d}, coreID={:d}, sub_stream_id={:d}[{0:010d}] [hwts : {1:d} : {2:s}] AICPU core ID {3:d} will be re-used by blk ID {4:d} 15block_schedulertoken_gen_process@ -+   remove_core_from_idle_listset_blk_vldset_core_ackprepare_core_ackget_blk_gntget_num_free_coresq_is_doneadd_num_blk_grantai_core_pool_processconfig_corest2_processruntickblock_scheduler.cc[%s] %s:%d %s an error occured, i is %d and total credit exp is%d hwts_aic_bs_loghwts_aicpu_bs_loghwts_aiv_bs_log[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} is not found in idle list[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} request block[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} ack[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} core {5:d} prepare ack[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} check blk_gnt = {5:d}[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} is blocked[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} is done, free blocked list[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} blk id {5:d} will reuse aicpu core[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} blk dim {5:d} all blk done[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} blk_vld = 1[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] AI core bitmap {4:d}, {5:d}, {6:d}, {7:d}, {8:d}, {9:d}, {10:d}, {11:d}, {12:d}, {13:d}, {14:d}, {15:d}, {16:d}, {17:d}, {18:d}, {19:d}, {20:d}, {21:d}, {22:d}, {23:d}, {24:d}, {25:d}, {26:d}, {27:d}, {28:d}, {29:d}, {30:d}, {31:d}, {32:d}, {33:d}, {34:d}, {35:d} [{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] blk_gnt {4:d} but no AI core[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} is assigned to SQ id {5:d}[{0:010d] [block_scheduler_{1:d} : {2:d} : {3:s}] non-scure pool {4:d} core {5:d} disable[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] scure pool {4:d} core {5:d} disable[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] non-secure pool {4:d} core {5:d} enable[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] non-secure pool {4:d} core {5:d} disable[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] secure pool {4:d} core {5:d} enable[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] secure pool {4:d} core {5:d} disable[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] high priority group pri_lvl = {4:d}, blk_vld_idx = {5:d}[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] low priority group pri_lvl = {4:d}, blk_vld_idx = {5:d}[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] low priority group RR blk_vld_idx = {4:d}[%s] %s:%d %s token_gen_process failed [{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} ACK[%s] %s:%d %s weight cnt of index %d is zero [{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} FREE[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} ALLOC, SQ {5:d}[%s] %s:%d %s block_scheduler run faield [{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} is assigned to SQ {5:d}getConfigPathassignConfigPathupdateConfigPathdavinci_mini.speclib_pvmodel.solibcamodel.soconfig_file.cc[%s] %s:%d %s Config file is found, path is %s [%s] %s:%d %s Config file not found: %s config_pv_aicore_model.toml[%s] %s:%d %s Using config file [%s] [%s] %s:%d %s Config file [%s] not found. [%s] %s:%d %s Invalid config file. [%s] %s:%d %s Using user config file [%s] [%s] %s:%d %s Unable to assign user config file [%s] ca_model/etcmodelmodel/model_v200model_v200../../../../etc19hwts_sdma_scheduler@ -+   set_blk_vldsdma_doneconfig_sdma_chsdma_fsmhwts_sdma_scheduler.cc[{0:010d}] [SDMA : {1:d} : {2:s}] New SDMA request SQ id {3:d}[{0:010d}] [SDMA : {1:d} : {2:s}] SDMA channel {3:d} done[{0:010d}] [SDMA : {1:d} : {2:s}] SDMA pool {3:d} non-secure channel {4:d} disable[{0:010d}] [SDMA : {1:d} : {2:s}] SDMA pool {3:d} secure channel {4:d} disable[{0:010d}] [SDMA : {1:d} : {2:s}] SDMA pool {3:d} non-secure channel {4:d} enable[{0:010d}] [SDMA : {1:d} : {2:s}] SDMA {3:d} non-secure channel {4:d} disable[{0:010d}] [SDMA : {1:d} : {2:s}] SDMA pool {3:d} secure channel {4:d} enable[{0:010d}] [SDMA : {1:d} : {2:s}] SDMA {3:d} secure channel {4:d} disable[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} gets SDMA channel {4:d}[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} SDMA secure channel {4:d} writes SQE to address {5:x}[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} SDMA secure channel {4:d} updates SQ tail {5:d}[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} SDMA non-secure channel {4:d} writes SQE to address {5:x}[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} SDMA non-secure channel {4:d} updates SQ tail {5:d}[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} SDMA secure channel {4:d} updates CQ head {5:d}[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} SDMA non-secure channel {4:d} updates CQ head {5:d}[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} SDMA free secure channel {4:d}[{0:010d}] [SDMA : {1:d} : {2:s}] SQ {3:d} SDMA free non-secure channel {4:d}19hwts_virtualizationSt23_Sp_counted_ptr_inplaceISt6vectorItSaItEESaIS2_ELN9__gnu_cxx12_Lock_policyE2EE@ -+   update_pool_statusrefill_tokenadd_vm_run_countpool_arbitermain_fsmvm_arbitervmg_sqdb_list_insert[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] VMG {3:d} enable {4:d} active SQid {5:d}[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] VMG {3:d} disable {4:d} active SQid {5:d}hwts_virtualization.cc[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] VM {3:d} current token = {4:d}[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] Strict mode unlock VMG {3:d} @ VM {4:d} runtime={5:d} token={6:d}[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] SQ {3:d} in VM {4:d} runtime counter = {5:d}[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] NORMAL POOL VMG@VM{3:d}={4:d} gives Active SQ idx = {5:d}.[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] COMMON POOL VMG@VM{3:d}={4:d} gives Active SQ idx = {5:d}.[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] HIGH NORMAL POOL VMG@VM{3:d}={4:d} gives Active SQ idx = {5:d}.[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] HIGH COMMON POOL VMG@VM{3:d}={4:d} gives Active SQ idx = {5:d}.[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] SQ DB Id {3:d} @ VM={4:d}, VMG={5:d} grants Active SQ Id={6:d}[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] invalid VMG SQDB pointer vm_id (0~3) = {3:d}.[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] invalid SQ doorbell idx {3:d}.[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] INIT or RELAX MODE got VM {3:d} for SQ doorbell idx {4:d}.[{0:010d}] [VIRTUALIZATION : {1:d} : {2:s}] STRICT MODE got VM {3:d} for SQ doorbell idx {4:d}.12l2_schedulerst1_processst2_processrun@ -+   l2_sche_fsmtickset_sqcq_l2_lock_reqclear_sqcq_l2_lock_reqget_sqcq_own_l2l2_scheduler.cc[%s] %s:%d %s there is a error here, weight cnt is zero hwts_l2_sche_log[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} new (std::nothrow) request L2 buffer[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} will take L2 buffer, need swap in[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} will take L2 buffer, L2 has no owner[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} request L2 buffer, existing owner SQ{4:d}[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} will take L2 buffer, SWAP in[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} SWAP out done[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} SWAP out[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} SWAP in done[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} SWAP in[%s] %s:%d %s l2 scheduler run failed [{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} L2 buffer lock request[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} L2 buffer unlock[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} own l2 = {4:d}[ERROR] Unable to read environment variable [].[INFO] Config file from absolute path: [ERROR] Config file cannot be found from absolute path: [INFO] Config file [] from environment variable [LD_LIBRARY_PATH]. Path: TOOLCHAIN_HOME] from environment variable [TOOLCHAIN_HOME]. Path: ] from current working directory. Path: ./etc/] from [./etc] directory. Path: [ERROR] Config file [] cannot be found.-cfg-noschema-class-schemaOverrideCfg-schemaOverrideScope-cpp-h-namespace-singleton.cpp.hr'cannot open 'w Invalid namespace '%s'unknown argument '%s' usage: %s -cfg -class options are: -noschema Do not generate a schema -schemaOverrideCfg -schemaOverrideScope -cpp default is .cpp -h default is .h -namespace X::Y::Z default is the global scope -singleton generate a singleton class -----------------------------------//%s%s Do not edit.// WARNING: This file was generated by %s. %s // access to an embedded// Description: a class providing %s // configuration string. #ifndef %s_h #define %s_h #include namespace %s { class %s { public: //-------- these would be private // Constructor and destructor. Ideally %s initialize the singleton. // but they have to be public so we can %s // Constructor and destructor. %s(); ~%s(); the singleton object // Get the configuration string from %s static const char * getString() { return s_singleton.m_str.c_str(); } // Get the configuration's schema int & schemaSizeconst char **& schema static void getSchema(%s, %s) s_singleton schema = %s.m_schema; schemaSize = %d; null terminated arraygetSchema static const char ** %s() // %s return s_singleton.m_schema; // Get the configuration string const char * getString() return m_str.c_str(); void getSchema(%s, %s) schema = m_schema; const char ** getSchema() // %s return m_schema; private: // Variables CONFIG4CPP_NAMESPACE::StringBuffer m_str; m_schema const char * %s[%d]; static %s s_singleton; // The following are not implemented %s & operator=(const %s &); %s(const %s &); }; }; // namespace %s #endif #include "%s%s" //-------- // Define the singleton object %s %s::s_singleton; %s::%s() m_schema[%d] = "%s"; m_schema[%d] = 0; m_str << ""; m_str << ""; } %s::~%s() // Nothing to do \\\t\n\"%s%s%s%t%n%%%" = ""; = [", ]; { } ConfigItem.cc0void config4cpp::ConfigItem::dump(config4cpp::StringBuffer&, const char*, bool, int) constN10config4cpp10ConfigItemE@copyFrom@else@elseIf@error@if@ifExists@in@include@matches@remove configFile(configType(exec(fileToDir(getenv(isFileReadable(join(osDirSeparator(osPathSeparator(osType(readFile(replace(siblingScope(split(N10config4cpp9ConfigLexEConfigParser.ccm_type == Configuration::CFG_STRINGm_type == Configuration::CFG_LISTm_listVal != 0m_type == Configuration::CFG_SCOPEm_scope != 0exec#0expecting identifier, line : cannot use '.' at start of the declaration of a variable or scope,expecting identifier or 'include'expecting ';' or '+'expecting '=', '?=' or '{'expecting 'include'The '@include' command cannot be used inside a scopecannot include "" due to security restrictionsfile#expecting ';' or '@ifExists' (included from )expecting 'if'expecting '('expecting ')'expecting '{'expecting '}'rexpecting '(', or a string expressionexpecting '@copyFrom'copy statement: cannot copy from own scope.copy statement: cannot copy from a parent scopeexpecting ';'copy statement: scope '' does not existcopy statement: '' is not a scopefromScope != 0item != 0expecting 'remove'expecting an identifier: can remove entries from only the current scope: '' does not exist in the current scopeexpecting 'error'expecting an identifier or '}'identifier '' not previously declaredexpecting a string, identifier or '['unix/:stringlistscopeno_value' is a scope instead of a string' is a list instead of a stringexpecting a string or identifierexpecting 'getenv('expecting ','cannot access the '' environment variableexpecting 'siblingScope('The siblingScope() function cannot be used in the root scopeexpecting 'read.file('error reading expecting 'join('expecting 'replace('expecting 'split('expecting 'os.exec('cannot execute "os.exec("") failed: execStatus == trueexpecting ']'' is not a listexpecting an identifier or '['i > 0expecting a string or ']''' is not a built-in function'.' is not a valid identifier'..' appears in identified 'end-of-line not allowed in string 'end-of-file encountered in block string starting at line is not a legal identifier near "" near 'config4cpp::ConfigParser::ConfigParser(config4cpp::Configuration::SourceType, const char*, const char*, const char*, config4cpp::ConfigurationImpl*, bool)void config4cpp::ConfigParser::parseCopyStmt()config4cpp::ConfigScope* config4cpp::ConfigItem::scopeVal() constconst char* config4cpp::ConfigItem::stringVal() constconfig4cpp::StringVector& config4cpp::ConfigItem::listVal() constvoid config4cpp::ConfigParser::parseRhsAssignStmt(config4cpp::LexToken&, short int)void config4cpp::ConfigParser::parseString(config4cpp::StringBuffer&)void config4cpp::ConfigParser::parseExec(config4cpp::StringBuffer&)void config4cpp::ConfigParser::getDirectoryOfFile(const char*, config4cpp::StringBuffer&)ConfigScope.ccm_type == Configuration::CFG_SCOPEm_scope != 0name[0] == '\0'.countWanted + countUnwanted == m_numEntriesitem->type() & Configuration::CFG_VARIABLESitem->type() == Configuration::CFG_SCOPEconfig4cpp::ConfigScope::ConfigScope(config4cpp::ConfigScope*, const char*)config4cpp::ConfigScope* config4cpp::ConfigItem::scopeVal() constvoid config4cpp::ConfigScope::listLocalNames(config4cpp::Configuration::Type, config4cpp::StringVector&) constvoid config4cpp::ConfigScope::dump(config4cpp::StringBuffer&, bool, int) const.Configuration.ccwStrLen != -1wPatternLen != -1static bool config4cpp::Configuration::patternMatch(const char*, const char*)N10config4cpp13ConfigurationEexec#file#ConfigurationImpl.ccm_type == Configuration::CFG_STRINGm_type == Configuration::CFG_LISTm_listVal != 0m_type == Configuration::CFG_SCOPEm_scope != 0cannot set default configuration: allow_patternsdeny_patternstrusted_directoriescannot set security configuration: cannot parse output of executing "" due to security restrictions0: variable '' was previously used as a scope: '' does not exist'scopeObj != 0i == len - 1scope != 0'' is not an entry' is not a scope' is a scope instead of a string' is a list instead of a string: no value specified for '' is a scope instead of a list' is a string instead of a list: bad value ('') specified for ''; should be one of: '',falsetrueboolean%d%d%c: non-integer value for 'str: Failed to extract uint64_t value from '%f%c: non-numeric value for ' value specified for '%f %s%s %%f%%c%d %s: invalid ('': should be ' ' where are,%s %%d%%c ' ' where aremicrosecondmicrosecondsmillisecondmillisecondssecondsecondsminuteminuteshourhoursdaydaysweekweeks infinitebytebytesBKBMBGBTBPB ' ' where are ' ' where aredurationMicrosecondscountDurationMicrosecondsInfo == countAllowedDurationMicrosecondsUnits; alternatively, you can use 'infinite'durationMillisecondsi < countDurationMillisecondsInfodurationSecondsi < countDurationSecondsInfo%d microseconds%d milliseconds%d secondsi < unitsInfoSizememorySizeBytesmemorySizeKBmemorySizeMB%d KB%d MB%f' is a string instead of a scope' is a list instead of a scope: scope '' does not existsize > 0strcmp(m_fileNameStack[size-1], fileName) == 0: line , circular include of 'scope '.' was previously used as a variable name/virtual void config4cpp::ConfigurationImpl::parse(config4cpp::Configuration::SourceType, const char*, const char*)const char* config4cpp::ConfigItem::stringVal() constconfig4cpp::StringVector& config4cpp::ConfigItem::listVal() constvirtual void config4cpp::ConfigurationImpl::remove(const char*, const char*)config4cpp::ConfigScope* config4cpp::ConfigItem::scopeVal() constconfig4cpp::ConfigItem* config4cpp::ConfigurationImpl::lookupHelper(config4cpp::ConfigScope*, const config4cpp::StringVector&) constvirtual const char* config4cpp::ConfigurationImpl::lookupString(const char*, const char*, const char*) constvirtual const char* config4cpp::ConfigurationImpl::lookupString(const char*, const char*) constvirtual void config4cpp::ConfigurationImpl::lookupList(const char*, const char*, const char**&, int&, const char**, int) constvirtual void config4cpp::ConfigurationImpl::lookupList(const char*, const char*, const char**&, int&) constvirtual void config4cpp::ConfigurationImpl::lookupList(const char*, const char*, config4cpp::StringVector&, const config4cpp::StringVector&) constvirtual void config4cpp::ConfigurationImpl::lookupList(const char*, const char*, config4cpp::StringVector&) constvirtual uint64_t config4cpp::ConfigurationImpl::stringToUint64(const char*, const char*, const char*) constvirtual int config4cpp::ConfigurationImpl::stringToDurationMicroseconds(const char*, const char*, const char*) constvirtual int config4cpp::ConfigurationImpl::stringToDurationMilliseconds(const char*, const char*, const char*) constvirtual int config4cpp::ConfigurationImpl::stringToDurationSeconds(const char*, const char*, const char*) constint config4cpp::ConfigurationImpl::stringToMemorySizeGeneric(const char*, config4cpp::SpellingAndValue*, int, const char**, const char*, const char*, const char*) constvirtual void config4cpp::ConfigurationImpl::lookupScope(const char*, const char*) constvoid config4cpp::ConfigurationImpl::popIncludedFilename(const char*)N10config4cpp17ConfigurationImplE#----------------------------------------------------------------------- # Default security checks for Config4* # ------------------------------------ # # allow_patterns is a list of wildcarded command lines that are allowed # to be executed (if the command resides in a directory listed in # trusted_directories). # deny_patterns is a list of wildcarded command lines that are # disallowed. # The wildcarded command-lines can contain "*", which denotes zero or # more characters. # trusted_directories is a list of directories in which the commands # listed in allow_patterns must be found. @if (osType() == "unix") { #-------- # Allow only a few commands that might be useful. allow_patterns = [ "curl *", "hostname", "uname", "uname *", "ifconfig" ]; # Disallow `...` (nested commands) and piped commands since we # have no idea what they might contain. deny_patterns = ["*`*", "*|*", "*>*"]; trusted_directories = ["/bin", "/usr/bin", "/usr/local/bin", "/sbin", "/usr/sbin"]; } @elseIf (osType() == "windows") { # Cygwin (or some other collection of UNIX-like tools) might # be installed on a Windows machine so the security # configuration is written accordingly. # The main difference from the UNIX settings is that # "deny_patterns" forbids the use of both UNIX and Windows-style # environment variables, that is, $NAME and %NAME%. "ipconfig" trusted_directories = [getenv("SYSTEMROOT") + "\system32"]; } @else { # If we don't know what operating system we are running on then # don't trust anything. allow_patterns = []; deny_patterns = ["*"]; trusted_directories = []; }; Config4* default securityallow_patternsdeny_patternstrusted_directories%s N10config4cpp28DefaultSecurityConfigurationELexBase.ccm_currSize > 1cannot open : cannot parse 'exec#': 0Invalid multi-byte character on line ?=!=!+&&||===;[]{}(),<...Fd%0{;K8m_ch == '"'Invalid escape sequence (%) in string on line config4cpp::LexBase::LexBase(config4cpp::Configuration::SourceType, const char*, config4cpp::UidIdentifierProcessor*)void config4cpp::StringBuffer::deleteLastChar()void config4cpp::LexBase::consumeString(config4cpp::LexToken&)N10config4cpp27UidIdentifierDummyProcessorEN10config4cpp7LexBaseEN10config4cpp8LexTokenE@ignoreEverythingIn@ignoreScopesIn@ignoreVariablesIn@optional@required@typedefN10config4cpp9SchemaLexEexpecting an identifier or keywordThere are multiple rules for ''expecting an identifieruid-Use of '@required' is incompatible with the uid- entry ('') in rule 'expecting '='Unknown type '' in rule 'expecting '['expecting an identifier, string or ']'expecting ','expecting ']'expecting expecting '@typedef'' in user-type definition 'error in validation rule '': near '; : bad value ('') for ''N10config4cpp10SchemaTypeEThe '' type should not take arguments in rule ''the value should be one of: 'false', 'true'N10config4cpp17SchemaTypeBooleanEThe '' type should take either no arguments or 2 arguments (denoting min and max durations) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be 'infinite' or in the format ' ' where is one of: 'microsecond', 'microseconds', 'second', 'seconds', 'minute', 'minutes' value for the second ('max') SchemaTypeDurationMicroseconds.ccmax == -1the value is outside the permitted range [, ]the value should be in the format ' ' microsecond, microseconds, second, seconds, minute, minutes; alternatively, you can use 'infinite'virtual bool config4cpp::SchemaTypeDurationMicroseconds::isA(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, int, config4cpp::StringBuffer&) constN10config4cpp30SchemaTypeDurationMicrosecondsEThe '' type should take either no arguments or 2 arguments (denoting min and max durations) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be 'infinite' or in the format ' ' where is one of: 'millisecond', 'milliseconds', 'second', 'seconds', 'minute', 'minutes', 'hour', 'hours', 'day', 'days', 'week', 'weeks value for the second ('max') SchemaTypeDurationMilliseconds.ccmax == -1the value is outside the permitted range [, ]the value should be in the format ' ' millisecond, milliseconds, second, seconds, minute, minutes, hour, hours, day, days, week, weeks; alternatively, you can use 'infinite'virtual bool config4cpp::SchemaTypeDurationMilliseconds::isA(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, int, config4cpp::StringBuffer&) constN10config4cpp30SchemaTypeDurationMillisecondsEThe '' type should take either no arguments or 2 arguments (denoting min and max durations) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be 'infinite' or in the format ' ' where is one of: 'second', 'seconds', 'minute', 'minutes', 'hour', 'hours', 'day', 'days', 'week', 'weeks value for the second ('max') SchemaTypeDurationSeconds.ccmax == -1the value is outside the permitted range [, ]the value should be in the format ' ' where is one of: second, seconds, minute, minutes, hour, hours, day, days, week, weeks; alternatively, you can use 'infinite'virtual bool config4cpp::SchemaTypeDurationSeconds::isA(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, int, config4cpp::StringBuffer&) constN10config4cpp25SchemaTypeDurationSecondsEThe '' type should take one or more arguments (denoting enum values) in rule ''the value should be one of: '',N10config4cpp14SchemaTypeEnumEthe '' type should take either no arguments or 2 arguments (denoting min and max values) in rule ''the first ('min') value is larger than the second ('max') argument in rule 'non-float value for the first ('min') argument in rule 'non-float value for the second ('max') argument in rule 'the value is outside the permitted range [, ]N10config4cpp15SchemaTypeFloatEThe '' type should take one or more arguments (denoting units) in rule ''the value should be in the format ' ' where is one of: '',N10config4cpp24SchemaTypeFloatWithUnitsEthe '' type should take either no arguments or 2 arguments (denoting min and max values) in rule ''the first ('min') value is larger than the second ('max') argument non-integer value for the first ('min') argument in rule 'non-integer value for the second ('max') argument in rule 'the value is outside the permitted range [, ]N10config4cpp13SchemaTypeIntEthe '' type should take one or more arguments (denoting units) in rule ''the value should be in the format ' ' where is one of: '',N10config4cpp22SchemaTypeIntWithUnitsEthe '' type requires one type argument in rule ''unknown type '' in rule 'you cannot embed a list type ('') inside another list in rule 'you cannot embed a scope type ('') inside a list in rule 'SchemaTypeList.cc0typeArgs.length() == 1elemTypeDef->cfgType() == Configuration::CFG_STRING; : bad value ('') for '[]'virtual void config4cpp::SchemaTypeList::checkRule(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const config4cpp::StringVector&, const char*) constvirtual void config4cpp::SchemaTypeList::validate(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const char*, const char*, const config4cpp::StringVector&, int) constN10config4cpp14SchemaTypeListEThe '' type should take either no arguments or 2 arguments (denoting min and max memory sizes) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be in the format ' ' where is one of: 'byte', 'bytes', 'KB', 'MB', GB value for the second ('max') the value is outside the permitted range [, ]the value should be in the format ' ' where is one of: 'byte', 'bytes', 'KB', 'MB', GBN10config4cpp25SchemaTypeMemorySizeBytesEThe '' type should take either no arguments or 2 arguments (denoting min and max memory sizes) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be in the format ' ' where is one of: 'KB', 'MB', 'GB', 'TB' value for the second ('max') ''KB', 'MB', 'GB', 'TB'the value is outside the permitted range [, ]the value should be in the format ' ' where is one of: 'KB', 'MB', 'GB', 'TB'N10config4cpp22SchemaTypeMemorySizeKBEThe '' type should take either no arguments or 2 arguments (denoting min and max memory sizes) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be in the format ' ' where is one of: 'MB', 'GB', 'TB', 'PB' value for the second ('max') the value is outside the permitted range [, ]the value should be in the format ' ' where is one of: 'MB', 'GB', 'TB', 'PB'N10config4cpp22SchemaTypeMemorySizeMBEthe '' type should not take arguments in rule ''N10config4cpp15SchemaTypeScopeEthe '' type should take either no arguments or 2 arguments (denoting min_length and max_length values) in rule ''the 'min_length' and 'max_length' of a string cannot be negative in rule 'the first ('min_length') argument is larger than the second ('max_length') argument in rule 'non-integer value for the first ('min_length') argument non-integer value for the second ('max_length') argument its length is outside the permitted range [, ]N10config4cpp16SchemaTypeStringEthe '' type requires pairs of column-type and column-name arguments in rule ''unknown type '' in rule 'you cannot embed a list type ('') inside a table in rule 'you cannot embed a scope type ('SchemaTypeTable.cc0typeArgsSize != 0typeArgsSize % 2 == 0: the number of entries in the '' is not a multiple of ; : bad value ('') for the '' column in row of the 'virtual void config4cpp::SchemaTypeTable::checkRule(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const config4cpp::StringVector&, const char*) constvirtual void config4cpp::SchemaTypeTable::validate(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const char*, const char*, const config4cpp::StringVector&, int) constN10config4cpp15SchemaTypeTableEthe '' type requires pairs of type and name arguments in rule ''unknown type '' in rule 'you cannot embed a list type ('') inside a tuple in rule 'you cannot embed a scope type ('SchemaTypeTuple.cc0typeArgsSize != 0typeArgsSize % 2 == 0: there should be entries in the '' ; entries denote ',; : bad value ('') for element ('') of the 'virtual void config4cpp::SchemaTypeTuple::checkRule(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const config4cpp::StringVector&, const char*) constvirtual void config4cpp::SchemaTypeTuple::validate(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const char*, const char*, const config4cpp::StringVector&, int) constN10config4cpp15SchemaTypeTupleEyou cannot specify arguments when using user-defined type '' in ''SchemaTypeTypedef.cctypeArgs.length() == 0baseTypeDef != 0virtual void config4cpp::SchemaTypeTypedef::validate(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const char*, const char*, const config4cpp::StringVector&, int) constvirtual bool config4cpp::SchemaTypeTypedef::isA(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, int, config4cpp::StringBuffer&) constN10config4cpp17SchemaTypeTypedefEThe '' type should take one or more arguments (denoting units) in rule ''the value should be in the format ' ' where is one of: '',N10config4cpp24SchemaTypeUnitsWithFloatEThe '' type should take one or more arguments (denoting units) in rule ''the value should be in the format ' ' where is one of: '',N10config4cpp22SchemaTypeUnitsWithIntEconfig4cpp::SchemaTypeBoolanbooleanconfig4cpp::SchemaTypeDurationMicrosecondsdurationMicrosecondsconfig4cpp::SchemaTypeDurationMillisecondsdurationMillisecondsconfig4cpp::SchemaTypeDurationSecondsdurationSecondsconfig4cpp::SchemaTypeDummyconfig4cpp::SchemaTypeEnumenumconfig4cpp::SchemaTypeFloatfloatconfig4cpp::SchemaTypeFloatWithUnitsfloat_with_unitsconfig4cpp::SchemaTypeIntintconfig4cpp::SchemaTypeIntWithUnitsint_with_unitsconfig4cpp::SchemaTypeListlistconfig4cpp::SchemaTypeMemorySizeBytesmemorySizeBytesconfig4cpp::SchemaTypeMemorySizeKBmemorySizeKBconfig4cpp::SchemaTypeMemorySizeMBmemorySizeMBconfig4cpp::SchemaTypeScopescopeconfig4cpp::SchemaTypeStringstringconfig4cpp::SchemaTypeTabletableconfig4cpp::SchemaTypeTupletupleconfig4cpp::SchemaTypeTypedefconfig4cpp::SchemaTypeUnitsWithFloatunits_with_floatconfig4cpp::SchemaTypeUnitsWithIntunits_with_intSchemaValidator.cc*result != 0typeDef != 00schema type '' is already registed---- config4cpp::SchemaValidator::parseSchema() %s: start %s: end %s: error: %s ---- config4cpp::SchemaValidator::validate() ignoring '%s' : the '' scope is unknown.' variable is unknown. %s: error: %s uid-: the '' does not existstrstr(nameInRule, "uid-") != 0symbol == SchemaLex::LEX_IGNORE_SCOPES_IN_SYM typeArgs = ["%s", ]typeName = "%s"; typeArgs = [start %s::checkRule() rule = "%s" end %s::checkRule() exception thrown from %s::checkRule(): %s start %s::validate() scope = "%s"; name = "%s" typeName = "%s"; origTypeName = "%s" end %s::validate() exception thrown from %s::validate(): %s start %s::isA() value = "%s" end %s::isA() truefalseresult = %s; errSuffix = "%s" exception thrown from %s::isA(): %s config4cpp::SchemaType* config4cpp::SchemaValidator::findType(const char*) constconfig4cpp::SchemaValidator::SchemaValidator()void config4cpp::SchemaValidator::validate(const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, config4cpp::SchemaValidator::ForceMode) constvoid config4cpp::SchemaValidator::validateRequiredUidEntry(const config4cpp::Configuration*, const char*, config4cpp::SchemaIdRuleInfo*) constbool config4cpp::SchemaValidator::shouldIgnore(const config4cpp::Configuration*, const char*, const char*, const char*) constN10config4cpp15SchemaTypeDummyEN10config4cpp15SchemaValidatorE%d%fStringVector.ccinitialCapacity > 0index < m_currSizem_array[m_currSize] == 0m_currSize > 0config4cpp::StringVector::StringVector(int)void config4cpp::StringVector::replace(int, const char*)void config4cpp::StringVector::replaceWithOwnership(int, char*)void config4cpp::StringVector::c_array(const char**&, int&) constconst char** config4cpp::StringVector::c_array() constvoid config4cpp::StringVector::removeLast()const char* config4cpp::StringVector::operator[](int) constuid-.'' is not a legal identifierUidIdentifierProcessor.ccm_count < 1000 * 1000 * 1000%09ld-count > 0void config4cpp::UidIdentifierProcessor::expandOne(config4cpp::StringBuffer&)N10config4cpp22UidIdentifierProcessorEplatform.ccm_currSize > 1 2>&1rcannot execute '': popen() failed/m_file == 0m_file != 0void config4cpp::StringBuffer::deleteLastChar()bool config4cpp::BufferedFileReader::open(const char*)int config4cpp::BufferedFileReader::getChar()Cache configurations must be of the form sets:ways:blocksizewhere sets, ways, and blocksize are positive integers, withsets and blocksize both powers of two and blocksize at least 8. Bytes Read: Bytes Written: Read Accesses: Write Accesses: Read Misses: Write Misses: Writebacks: Miss Rate: Bbasic_string::_S_construct null not valid14fa_cache_sim_t11cache_sim_t 7clint_t trap_load_address_misalignedtrap_store_address_misalignedoo@o@s${s$@# D@tcs$@D@t$o#&ss$ {#"g0s$@#$s$ {s {hERROR: invalid load from debug module: %zd bytes at 0x%016lx debug_module.cclen == 4ERROR: invalid store to debug module: %zd bytes at 0x%016lx dmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true dmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true vector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)virtual bool debug_module_t::store(reg_t, size_t, const uint8_t*)17trigger_matched_t22trap_load_access_fault29trap_store_address_misaligned28trap_load_address_misaligned10mem_trap_t14debug_module_t Plugin device type "" already registered!map::at5bus_t trap_load_address_misaligneddummy_roccZN19register_dummy_roccC4EvEUlvE_12dummy_rocc_t trap_instruction_address_misaligned0x%04x0x%08x0x%016lx0x%016lx%016lx#Fi;^ 0Sv%Hk=`2Ux'Jm?b4Wz ) L o  A d  6 Y |  + N q C f 8[~ -Ps"Eh:] /Ru$Gj<_1Tw&Il>a3Vy(Kn@c5X{*MpBe7Z} ,Or! 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"."Q"t""""###F#i#####$;$^$$$$$ %0%S%v%%%%&%&H&k&&&&&'='`'''''(2(U(x(((()')J)m)))))*?*b*****+4+W+z++++,),L,o,,,,,-A-d-----.6.Y.|..../+/N/q///// 0C0f00000181[1~1111 2-2P2s22222"3E3h333334:4]44444 5/5R5u55556$6G6j666667<7_77777818T8w88889&9I9l99999:>:a:::::;3;V;y;;;;<(<K<n<<<<<=@=c=====>5>X>{>>>>?*?M?p?????@B@e@@@@@A7AZA}AAAA B,BOBrBBBBB!CDCgCCCCCD9D\DDDDD E.EQEtEEEEF#FFFiFFFFFG;G^GGGGG H0HSHvHHHHI%IHIkIIIIIJ=J`JJJJJK2KUKxKKKKL'LJLmLLLLLM?MbMMMMMN4NWNzNNNNO)OLOoOOOOOPAPdPPPPPQ6QYQ|QQQQR+RNRqRRRRR SCSfSSSSST8T[T~TTTT U-UPUsUUUUU"VEVhVVVVVW:W]WWWWW X/XRXuXXXXY$YGYjYYYYYZ]a]]]]]^3^V^y^^^^_(_K_n_____`@`c`````a5aXa{aaaab*bMbpbbbbbcBcecccccd7dZd}dddd e,eOereeeee!fDfgfffffg9g\ggggg h.hQhthhhhi#iFiiiiiiij;j^jjjjj k0kSkvkkkkl%lHlklllllm=m`mmmmmn2nUnxnnnno'oJomooooop?pbpppppq4qWqzqqqqr)rLrorrrrrsAsdssssst6tYt|ttttu+uNuquuuuu vCvfvvvvvw8w[w~wwww x-xPxsxxxxx"yEyhyyyyyz:z]zzzzz {/{R{u{{{{|$|G|j|||||}<}_}}}}}~1~T~w~~~~&Il>aʀ3Vy(Knׂ@c̃5X{*MpمBeΆ7Z}Ç ,Orۈ!DgЉ9\Ŋ .Qt݋35trap_instruction_address_misaligned trap_illegal_instructiona COP exception was posted, but interrupts are disabled!11extension_t24trap_illegal_instruction lib.socouldn't find extension '%s' (or library '%s') context.ccthis != curcontext_t::~context_t()void context_t::switch_to()%lubcdidentitydevice.cccmd < command_t::MAX_COMMANDSstrlen(name) < IDENTITY_SIZEaddr % IDENTITY_SIZE == 0strlen(identity()) < IDENTITY_SIZEreadwritecould not open could not stat disk size=could not read @ could not write num_devices < command_t::MAX_DEVICESbasic_string::_S_construct null not validvoid device_t::register_command(size_t, device_t::command_func_t, const char*)void device_t::handle_identify(command_t)void device_list_t::register_device(device_t*)St5_BindIFM6disk_tFv9command_tEPS0_St12_PlaceholderILi1EEEESt5_BindIFM5bcd_tFv9command_tEPS0_St12_PlaceholderILi1EEEESt5_BindIFM8device_tFv9command_tEPS0_St12_PlaceholderILi1EEEE13null_device_t6disk_t5bcd_t8device_tSt17_Weak_result_typeIM6disk_tFv9command_tEESt17_Weak_result_typeIM5bcd_tFv9command_tEESt17_Weak_result_typeIM8device_tFv9command_tEESt22_Weak_result_type_implIM6disk_tFv9command_tEESt22_Weak_result_type_implIM5bcd_tFv9command_tEESt22_Weak_result_type_implIM8device_tFv9command_tEEdtm.ccresp_buf.resp == 0program_n <= ram_wordsdata_n <= data_wordsOTHERERROR: %s:%d, Debug Abstract Command Error #%d (%s)ERROR: %s:%d, Should die, but allowing simulation to continue and fail.OKBUSYNOT_SUPPORTEDEXCEPTIONHALT/RESUMEFESVR DTM Does not support 128-bitFESVR DTM can't determine XLEN. Aborting(((hartinfo) & ((0xf << 20))) / (((0xf << 20)) & ~(((0xf << 20)) << 1))) > 0(((hartinfo) & ((0x1 << 16))) / (((0x1 << 16)) & ~(((0x1 << 16)) << 1)))resp_waituint32_t dtm_t::do_command(dtm_t::req)uint32_t dtm_t::run_abstract_command(uint32_t, const uint32_t*, size_t, uint32_t*, size_t)void dtm_t::producer_thread()void dtm_t::tick(bool, bool, dtm_t::resp)5dtm_telfloader.ccfd != -1buf != ((void *) -1)size >= sizeof(Elf64_Ehdr)(((*eh64).e_ident[0] == 0x7f && (*eh64).e_ident[1] == 'E' && (*eh64).e_ident[2] == 'L' && (*eh64).e_ident[3] == 'F') && (*eh64).e_ident[4] == 1) || (((*eh64).e_ident[0] == 0x7f && (*eh64).e_ident[1] == 'E' && (*eh64).e_ident[2] == 'L' && (*eh64).e_ident[3] == 'F') && (*eh64).e_ident[4] == 2)size >= eh->e_phoff + eh->e_phnum*sizeof(*ph)size >= ph[i].p_offset + ph[i].p_fileszsize >= eh->e_shoff + eh->e_shnum*sizeof(*sh)eh->e_shstrndx < eh->e_shnumsize >= sh[eh->e_shstrndx].sh_offset + sh[eh->e_shstrndx].sh_sizesh[i].sh_name < sh[eh->e_shstrndx].sh_sizestrnlen(shstrtab + sh[i].sh_name, max_len) < max_lensize >= sh[i].sh_offset + sh[i].sh_size.strtab.symtabsym[i].st_name < sh[strtabidx].sh_sizestrnlen(strtab + sym[i].st_name, max_len) < max_lenvector::_M_default_appendstd::map, long unsigned int> load_elf(const char*, memif_t*, reg_t*)syscall_proxyhtifnone//riscv64-unknown-elf/bin/could not open (did you misspell it? If VCS, did you forget +permissive/+permissive-off?)tohostfromhostwarning: tohost and fromhost symbols not in ELF; can't communicate with target begin_signatureend_signaturehtif.ccsigs && "can't open signature file!"sig_len % incr == 0helprfbdisksignaturechroot-hUser quered htif_t help text--disk/+disk unsupported (use a ramdisk)Unknown argument (did you mean to enable +permissive parsing?)+rfb+rfb=+disk=+signature=+chroot=+permissive-offFound +permissive-off when not parsing permissively+permissiveFound +permissive when already parsing permissivelyNo binary specified (Did you forget it? Did you forget '+permissive-off' if running with +permissive?)Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]... Run a BINARY on the Rocket Chip emulator. Mandatory arguments to long options are mandatory for short options too. EMULATOR OPTIONS Consult emulator.cc if using Verilator or VCS documentation if using VCS for available options. EMUALTOR VERILOG PLUSARGS Consult generated-src*/*.plusArgs for available options HOST OPTIONS -h, --help Display this help and exit +permissive The host will ignore any unparsed options up until +permissive-off (Only needed for VCS) +permissive-off Stop ignoring options. This is mandatory if using +permissive (Only needed for VCS) --rfb=DISPLAY Add new remote frame buffer on display DISPLAY +rfb=DISPLAY to be accessible on 5900 + DISPLAY (default = 0) --signature=FILE Write torture test signature to FILE +signature=FILE --chroot=PATH Use PATH as location of syscall-servicing binaries +chroot=PATH HOST OPTIONS (currently unsupported) --disk=DISK Add DISK device. Use a ramdisk since this isn't +disk=DISK supported TARGET (RISC-V BINARY) OPTIONS These are the options passed to the program executing on the emulated RISC-V microprocessor. vector::_M_realloc_insert*St5_BindIFZN6htif_t3runEvEUlPSt5queueImSt5dequeImSaImEEEmE_S6_St12_PlaceholderILi1EEEE*ZN6htif_t12load_programEvE21preload_aware_memif_t*St17_Weak_result_typeIZN6htif_t3runEvEUlPSt5queueImSt5dequeImSaImEEEmE_E*St22_Weak_result_type_implIZN6htif_t3runEvEUlPSt5queueImSt5dequeImSaImEEEmE_E*St22_Maybe_get_result_typeIZN6htif_t3runEvEUlPSt5queueImSt5dequeImSaImEEEmE_vEvirtual void htif_t::stop()6htif_t15chunked_memif_t9syscall_thtif_hexwriter.cclen % chunk_align() == 0taddr < width*depthtaddr+len <= width*depth00vector::_M_fill_insertvirtual void htif_hexwriter_t::read_chunk(addr_t, size_t, void*)virtual void htif_hexwriter_t::write_chunk(addr_t, size_t, const void*)16htif_hexwriter_tdeque::_M_new_elements_at_frontdeque::_M_new_elements_at_back14htif_pthread_tmisaligned address7memif_toption_parser.ccargv0no argument allowed for optionargument required for optionunrecognized option%s: %s %s vector::_M_realloc_insertconst char* const* option_parser_t::parse(const char* const*)%drfbconfigureset_addresscould not acquire tcp socketcould not bind to port could not listen on port could not accept connectionRFB 003.003 bad client versionRISC-Vbad pixel formatcould not writecould not readreceived oversized packetyou must only set the rfb configuration oncerfb requires 32 bpp true colorrfb size must be a multiple of could not create threadrfb address must be -byte alignedbasic_string::_S_construct null not validSt5_BindIFM5rfb_tFv9command_tEPS0_St12_PlaceholderILi1EEEE5rfb_tSt17_Weak_result_typeIM5rfb_tFv9command_tEESt22_Weak_result_type_implIM5rfb_tFv9command_tEE%lusyscall_proxysyscallcould not dup stdin/stdout/*** FAILED *** (tohost = )bad syscall #could not chroot to %s vector::_M_default_appendbasic_string::_S_construct null not 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trap_illegal_instructiontrap_load_address_misalignedtrap_store_address_misalignedtrap_store_access_faulttrap_store_page_fault trap_illegal_instructiontrap_load_address_misalignedtrap_store_address_misalignedtrap_store_access_faulttrap_store_page_fault trap_illegal_instructiontrap_load_address_misalignedtrap_store_address_misalignedtrap_store_access_faulttrap_store_page_fault trap_illegal_instructiontrap_load_address_misalignedtrap_store_address_misalignedtrap_store_access_faulttrap_store_page_fault trap_illegal_instructiontrap_load_address_misalignedtrap_store_address_misalignedtrap_store_access_faulttrap_store_page_fault trap_illegal_instructiontrap_load_address_misalignedtrap_store_address_misalignedtrap_store_access_faulttrap_store_page_fault    trap_instruction_address_misaligned trap_instruction_address_misaligned trap_instruction_address_misaligned trap_instruction_address_misaligned trap_instruction_address_misaligned trap_instruction_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_instruction_address_misalignedtrap_illegal_instruction trap_instruction_address_misalignedtrap_illegal_instruction trap_illegal_instructiontrap_breakpoint15trap_breakpoint trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_instruction_address_misalignedtrap_illegal_instruction trap_instruction_address_misalignedtrap_illegal_instruction trap_instruction_address_misalignedtrap_illegal_instruction trap_instruction_address_misalignedtrap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_breakpoint trap_user_ecalltrap_supervisor_ecalltrap_machine_ecall18trap_machine_ecall21trap_supervisor_ecall15trap_user_ecall trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction   trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instructiontrap_store_address_misaligned trap_instruction_address_misaligned trap_instruction_address_misaligned   trap_illegal_instructiontrap_load_address_misaligned trap_load_address_misaligned trap_load_address_misaligned trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instructiontrap_load_address_misaligned  trap_load_address_misaligned trap_illegal_instructiontrap_load_address_misaligned trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction   trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction  trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instruction trap_store_address_misaligned  trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction      trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction  trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction  trap_illegal_instruction trap_store_address_misaligned trap_illegal_instruction   trap_load_address_misalignedtrap_interactive runrrsregfregfregsfregdpcmemstruntilwhilequitqhelph: Unknown command %s Interactive commands: reg [reg] # Display [reg] (all if omitted) in fregs # Display single precision in fregd # Display double precision in pc # Show current PC in mem # Show contents of physical memory str # Show NUL-terminated C string until reg # Stop when in hits until pc # Stop when PC in hits until mem # Stop when memory becomes while reg # Run while in is while pc # Run while PC in is while mem # Run while memory is run [count] # Resume noisy execution (until [count] insns) r [count] Alias for run rs [count] # Resume silent execution (until [count] insns) quit # End the simulation q Alias for quit help # This screen! h Alias for help Note: Hitting enter is the same as: run 1 0x%016lx fflagsfrmfcsrcycletimeinstrethpmcounter3hpmcounter4hpmcounter5hpmcounter6hpmcounter7hpmcounter8hpmcounter9hpmcounter10hpmcounter11hpmcounter12hpmcounter13hpmcounter14hpmcounter15hpmcounter16hpmcounter17hpmcounter18hpmcounter19hpmcounter20hpmcounter21hpmcounter22hpmcounter23hpmcounter24hpmcounter25hpmcounter26hpmcounter27hpmcounter28hpmcounter29hpmcounter30hpmcounter31sstatussiestvecscounterensscratchsepcscausestvalsipsatpmstatusmisamedelegmidelegmiemtvecmcounterenmscratchmepcmcausemtvalmippmpcfg0pmpcfg1pmpcfg2pmpcfg3pmpaddr0pmpaddr1pmpaddr2pmpaddr3pmpaddr4pmpaddr5pmpaddr6pmpaddr7pmpaddr8pmpaddr9pmpaddr10pmpaddr11pmpaddr12pmpaddr13pmpaddr14pmpaddr15tselecttdata1tdata2tdata3dcsrdpcdscratchmcycleminstretmhpmcounter3mhpmcounter4mhpmcounter5mhpmcounter6mhpmcounter7mhpmcounter8mhpmcounter9mhpmcounter10mhpmcounter11mhpmcounter12mhpmcounter13mhpmcounter14mhpmcounter15mhpmcounter16mhpmcounter17mhpmcounter18mhpmcounter19mhpmcounter20mhpmcounter21mhpmcounter22mhpmcounter23mhpmcounter24mhpmcounter25mhpmcounter26mhpmcounter27mhpmcounter28mhpmcounter29mhpmcounter30mhpmcounter31mhpmevent3mhpmevent4mhpmevent5mhpmevent6mhpmevent7mhpmevent8mhpmevent9mhpmevent10mhpmevent11mhpmevent12mhpmevent13mhpmevent14mhpmevent15mhpmevent16mhpmevent17mhpmevent18mhpmevent19mhpmevent20mhpmevent21mhpmevent22mhpmevent23mhpmevent24mhpmevent25mhpmevent26mhpmevent27mhpmevent28mhpmevent29mhpmevent30mhpmevent31mvendoridmarchidmimpidmhartidcyclehtimehinstrethhpmcounter3hhpmcounter4hhpmcounter5hhpmcounter6hhpmcounter7hhpmcounter8hhpmcounter9hhpmcounter10hhpmcounter11hhpmcounter12hhpmcounter13hhpmcounter14hhpmcounter15hhpmcounter16hhpmcounter17hhpmcounter18hhpmcounter19hhpmcounter20hhpmcounter21hhpmcounter22hhpmcounter23hhpmcounter24hhpmcounter25hhpmcounter26hhpmcounter27hhpmcounter28hhpmcounter29hhpmcounter30hhpmcounter31hmcyclehminstrethmhpmcounter3hmhpmcounter4hmhpmcounter5hmhpmcounter6hmhpmcounter7hmhpmcounter8hmhpmcounter9hmhpmcounter10hmhpmcounter11hmhpmcounter12hmhpmcounter13hmhpmcounter14hmhpmcounter15hmhpmcounter16hmhpmcounter17hmhpmcounter18hmhpmcounter19hmhpmcounter20hmhpmcounter21hmhpmcounter22hmhpmcounter23hmhpmcounter24hmhpmcounter25hmhpmcounter26hmhpmcounter27hmhpmcounter28hmhpmcounter29hmhpmcounter30hmhpmcounter31h%-4s: 0x%016lx 0x%016lx%016lx %g vector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)vector::_M_realloc_insert16trap_interactive      trap_instruction_access_faulttrap_load_access_faulttrap_store_access_faulttrap_instruction_page_faulttrap_load_page_faulttrap_store_page_faultvector::_M_realloc_insert16memtracer_list_t11memtracer_t27trap_instruction_page_fault29trap_instruction_access_fault %utrap_illegal_instructionerror: bad --isa option %s imafdqcrv32rv64rvimafdcimafdPC Histogram support has not been properly enabled; please re-build the riscv-isa-run project using "configure --enable-histogram". processor.ccprv <= 3core %3d: exception %s, epc 0x%016lx core %3d: tval 0x%016lx core %3d: Executed %lx times core %3d: 0x%016lx (0x%08lx) %s xlen == max_xlenonly one extension may be registeredvector::_M_realloc_insertbasic_string::_S_construct null not validreg_t processor_t::legalize_privilege(reg_t)int processor_t::paddr_bits()11processor_t zeroraspgptpt0t1t2s0s1a0a1a2a3a4a5a6a7s2s3s4s5s6s7s8s9s10s11t3t4t5t6ft0ft1ft2ft3ft4ft5ft6ft7fs0fs1fa0fa1fa2fa3fa4fa5fa6fa7fs2fs3fs4fs5fs6fs7fs8fs9fs10fs11ft8ft9ft10ft11remote_bitbang failed to make socket: %s (%d) remote_bitbang failed setsockopt: %s (%d) remote_bitbang failed to bind socket: %s (%d) remote_bitbang failed to listen on socket: %s (%d) remote_bitbang getsockname failed: %s (%d) Listening for remote bitbang connection on port %d. failed to accept on socket: %s (%d) remote_bitbang got unsupported command '%c' failed to write to socket: %s (%d) remote_bitbang failed to read on socket: %s (%d) Remote Bitbang received 'Q' Received nothing. Quitting. %luzero bytes of target memory requestedcouldn't allocate bytes of target memoryRV32IMTEST2048vector::_M_realloc_insertbasic_string::_S_construct null not validNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvP5sim_tES4_EEEEEEPFP17abstract_device_tRKSsE5mem_tFP17abstract_device_tRKSsE vector::_M_realloc_insert6rocc_t 12rom_device_t trap_load_address_misalignedtrap_store_address_misalignedNumber of specified hartids doesn't match number of processorsFailed to fork dts child: Failed to write dts: Failed to fork dtb child: dtb-O/usr/bin/dtcFailed to run /usr/bin/dtc: Failed to read dtb: Child dts process failedChild dtb process failed/dts-v1/; / { #address-cells = <2>; #size-cells = <2>; compatible = "ucbbar,spike-bare-dev"; model = "ucbbar,spike-bare"; cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <>; CPU: cpu@ { device_type = "cpu"; reg = <>; status = "okay"; compatible = "riscv"; riscv,isa = ""; mmu-type = "riscv,sv32sv48"; clock-frequency = <>; CPU_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; }; memory@ { device_type = "memory"; reg = <0x 0x>; }; soc { #address-cells = <2>; #size-cells = <2>; compatible = "ucbbar,spike-bare-soc", "simple-bus"; ranges; clint@ { compatible = "riscv,clint0"; interrupts-extended = <&CPU_intc 3 &CPU_intc 7 >; reg = <0x>; }; }; htif { compatible = "ucb,htif0"; }; }; sim.cclen == 8vector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)vector::_M_default_appendvector::_M_range_insertvirtual void sim_t::read_chunk(addr_t, size_t, void*)virtual void sim_t::write_chunk(addr_t, size_t, const void*)5sim_t7simif_tɴ}šC)ڵ퍷ƈm$ấB!-Əx(i\5Rt>Jh+C^co׭ƣz<2~,֡w ۍv;md\]VPUKyFB %d%lu, (fflagsfrmfcsrcycletimeinstrethpmcounter3hpmcounter4hpmcounter5hpmcounter6hpmcounter7hpmcounter8hpmcounter9hpmcounter10hpmcounter11hpmcounter12hpmcounter13hpmcounter14hpmcounter15hpmcounter16hpmcounter17hpmcounter18hpmcounter19hpmcounter20hpmcounter21hpmcounter22hpmcounter23hpmcounter24hpmcounter25hpmcounter26hpmcounter27hpmcounter28hpmcounter29hpmcounter30hpmcounter31sstatussiestvecscounterensscratchsepcscausestvalsipsatpmstatusmisamedelegmidelegmiemtvecmcounterenmscratchmepcmcausemtvalmippmpcfg0pmpcfg1pmpcfg2pmpcfg3pmpaddr0pmpaddr1pmpaddr2pmpaddr3pmpaddr4pmpaddr5pmpaddr6pmpaddr7pmpaddr8pmpaddr9pmpaddr10pmpaddr11pmpaddr12pmpaddr13pmpaddr14pmpaddr15tselecttdata1tdata2tdata3dcsrdpcdscratchmcycleminstretmhpmcounter3mhpmcounter4mhpmcounter5mhpmcounter6mhpmcounter7mhpmcounter8mhpmcounter9mhpmcounter10mhpmcounter11mhpmcounter12mhpmcounter13mhpmcounter14mhpmcounter15mhpmcounter16mhpmcounter17mhpmcounter18mhpmcounter19mhpmcounter20mhpmcounter21mhpmcounter22mhpmcounter23mhpmcounter24mhpmcounter25mhpmcounter26mhpmcounter27mhpmcounter28mhpmcounter29mhpmcounter30mhpmcounter31mhpmevent3mhpmevent4mhpmevent5mhpmevent6mhpmevent7mhpmevent8mhpmevent9mhpmevent10mhpmevent11mhpmevent12mhpmevent13mhpmevent14mhpmevent15mhpmevent16mhpmevent17mhpmevent18mhpmevent19mhpmevent20mhpmevent21mhpmevent22mhpmevent23mhpmevent24mhpmevent25mhpmevent26mhpmevent27mhpmevent28mhpmevent29mhpmevent30mhpmevent31mvendoridmarchidmimpidmhartidcyclehtimehinstrethhpmcounter3hhpmcounter4hhpmcounter5hhpmcounter6hhpmcounter7hhpmcounter8hhpmcounter9hhpmcounter10hhpmcounter11hhpmcounter12hhpmcounter13hhpmcounter14hhpmcounter15hhpmcounter16hhpmcounter17hhpmcounter18hhpmcounter19hhpmcounter20hhpmcounter21hhpmcounter22hhpmcounter23hhpmcounter24hhpmcounter25hhpmcounter26hhpmcounter27hhpmcounter28hhpmcounter29hhpmcounter30hhpmcounter31hmcyclehminstrethmhpmcounter3hmhpmcounter4hmhpmcounter5hmhpmcounter6hmhpmcounter7hmhpmcounter8hmhpmcounter9hmhpmcounter10hmhpmcounter11hmhpmcounter12hmhpmcounter13hmhpmcounter14hmhpmcounter15hmhpmcounter16hmhpmcounter17hmhpmcounter18hmhpmcounter19hmhpmcounter20hmhpmcounter21hmhpmcounter22hmhpmcounter23hmhpmcounter24hmhpmcounter25hmhpmcounter26hmhpmcounter27hmhpmcounter28hmhpmcounter29hmhpmcounter30hmhpmcounter31hunknown_%03lx0xpc 0xunknownlblbulhlhulwlwuldsbshswsdamoadd_wamoswap_wamoand_wamoor_wamoxor_wamomin_wamomax_wamominu_wamomaxu_wamoadd_damoswap_damoand_damoor_damoxor_damomin_damomax_damominu_damomaxu_dlr_wsc_wlr_dsc_dflwfldflqfswfsdfsqjjalbeqzbnezbltzbgezbeqbnebltbgebltubgeuluiauipcretjrjalrnop - limvaddisllisltiseqzsltiunotxorisrlisraioriandisext.waddiwslliwsrliwsraiwaddsubsllsltsnezsltuxorsrlsraorandmulmulhmulhumulhsudivdivuremremuaddwsubwsllwsrlwsrawmulwdivwdivuwremwremuwecallebreakuretsretmretfencefence_icsrrcsrwcsrscsrccsrwicsrsicsrcicsrrwcsrrscsrrccsrrwicsrrsicsrrcifadd_sfsub_sfmul_sfdiv_sfsqrt_sfmin_sfmax_sfmadd_sfmsub_sfnmadd_sfnmsub_sfsgnj_sfsgnjn_sfsgnjx_sfcvt_s_dfcvt_s_qfcvt_s_lfcvt_s_lufcvt_s_wfcvt_s_wufmv_w_xfcvt_l_sfcvt_lu_sfcvt_w_sfcvt_wu_sfclass_sfmv_x_wfeq_sflt_sfle_sfadd_dfsub_dfmul_dfdiv_dfsqrt_dfmin_dfmax_dfmadd_dfmsub_dfnmadd_dfnmsub_dfsgnj_dfsgnjn_dfsgnjx_dfcvt_d_sfcvt_d_qfcvt_d_lfcvt_d_lufcvt_d_wfcvt_d_wufmv_d_xfcvt_l_dfcvt_lu_dfcvt_w_dfcvt_wu_dfclass_dfmv_x_dfeq_dflt_dfle_dfadd_qfsub_qfmul_qfdiv_qfsqrt_qfmin_qfmax_qfmadd_qfmsub_qfnmadd_qfnmsub_qfsgnj_qfsgnjn_qfsgnjx_qfcvt_q_sfcvt_q_dfcvt_q_lfcvt_q_lufcvt_q_wfcvt_q_wufmv_q_xfcvt_l_qfcvt_lu_qfcvt_w_qfcvt_wu_qfclass_qfmv_x_qfeq_qflt_qfle_qbeq (args unknown)bne (args unknown)blt (args unknown)bge (args unknown)bltu (args unknown)bgeu (args unknown)jalr (args unknown)jal (args unknown)lui (args unknown)auipc (args unknown)addi (args unknown)slli (args unknown)slti (args unknown)sltiu (args unknown)xori (args unknown)srli (args unknown)srai (args unknown)ori (args unknown)andi (args unknown)add (args unknown)sub (args unknown)sll (args unknown)slt (args unknown)sltu (args unknown)xor (args unknown)srl (args unknown)sra (args unknown)or (args unknown)and (args unknown)addiw (args unknown)slliw (args unknown)srliw (args unknown)sraiw (args unknown)addw (args unknown)subw (args unknown)sllw (args unknown)srlw (args unknown)sraw (args unknown)lb (args unknown)lh (args unknown)lw (args unknown)ld (args unknown)lbu (args unknown)lhu (args unknown)lwu (args unknown)sb (args unknown)sh (args unknown)sw (args unknown)sd (args unknown)fence (args unknown)fence_i (args unknown)mul (args unknown)mulh (args unknown)mulhsu (args unknown)mulhu (args unknown)div (args unknown)divu (args unknown)rem (args unknown)remu (args unknown)mulw (args unknown)divw (args unknown)divuw (args unknown)remw (args unknown)remuw (args unknown)amoadd_w (args unknown)amoxor_w (args unknown)amoor_w (args unknown)amoand_w (args unknown)amomin_w (args unknown)amomax_w (args unknown)amominu_w (args unknown)amomaxu_w (args unknown)amoswap_w (args unknown)lr_w (args unknown)sc_w (args unknown)amoadd_d (args unknown)amoxor_d (args unknown)amoor_d (args unknown)amoand_d (args unknown)amomin_d (args unknown)amomax_d (args unknown)amominu_d (args unknown)amomaxu_d (args unknown)amoswap_d (args unknown)lr_d (args unknown)sc_d (args unknown)ecall (args unknown)ebreak (args unknown)uret (args unknown)sret (args unknown)mret (args unknown)dret (args unknown)sfence_vma (args unknown)wfi (args unknown)csrrw (args unknown)csrrs (args unknown)csrrc (args unknown)csrrwi (args unknown)csrrsi (args unknown)csrrci (args unknown)fadd_s (args unknown)fsub_s (args unknown)fmul_s (args unknown)fdiv_s (args unknown)fsgnj_s (args unknown)fsgnjn_s (args unknown)fsgnjx_s (args unknown)fmin_s (args unknown)fmax_s (args unknown)fsqrt_s (args unknown)fadd_d (args unknown)fsub_d (args unknown)fmul_d (args unknown)fdiv_d (args unknown)fsgnj_d (args unknown)fsgnjn_d (args unknown)fsgnjx_d (args unknown)fmin_d (args unknown)fmax_d (args unknown)fcvt_s_d (args unknown)fcvt_d_s (args unknown)fsqrt_d (args unknown)fadd_q (args unknown)fsub_q (args unknown)fmul_q (args unknown)fdiv_q (args unknown)fsgnj_q (args unknown)fsgnjn_q (args unknown)fsgnjx_q (args unknown)fmin_q (args unknown)fmax_q (args unknown)fcvt_s_q (args unknown)fcvt_q_s (args unknown)fcvt_d_q (args unknown)fcvt_q_d (args unknown)fsqrt_q (args unknown)fle_s (args unknown)flt_s (args unknown)feq_s (args unknown)fle_d (args unknown)flt_d (args unknown)feq_d (args unknown)fle_q (args unknown)flt_q (args unknown)feq_q (args unknown)fcvt_w_s (args unknown)fcvt_wu_s (args unknown)fcvt_l_s (args unknown)fcvt_lu_s (args unknown)fmv_x_w (args unknown)fclass_s (args unknown)fcvt_w_d (args unknown)fcvt_wu_d (args unknown)fcvt_l_d (args unknown)fcvt_lu_d (args unknown)fmv_x_d (args unknown)fclass_d (args unknown)fcvt_w_q (args unknown)fcvt_wu_q (args unknown)fcvt_l_q (args unknown)fcvt_lu_q (args unknown)fmv_x_q (args unknown)fclass_q (args unknown)fcvt_s_w (args unknown)fcvt_s_wu (args unknown)fcvt_s_l (args unknown)fcvt_s_lu (args unknown)fmv_w_x (args unknown)fcvt_d_w (args unknown)fcvt_d_wu (args unknown)fcvt_d_l (args unknown)fcvt_d_lu (args unknown)fmv_d_x (args unknown)fcvt_q_w (args unknown)fcvt_q_wu (args unknown)fcvt_q_l (args unknown)fcvt_q_lu (args unknown)fmv_q_x (args unknown)flw (args unknown)fld (args unknown)flq (args unknown)fsw (args unknown)fsd (args unknown)fsq (args unknown)fmadd_s (args unknown)fmsub_s (args unknown)fnmsub_s (args unknown)fnmadd_s (args unknown)fmadd_d (args unknown)fmsub_d (args unknown)fnmsub_d (args unknown)fnmadd_d (args unknown)fmadd_q (args unknown)fmsub_q (args unknown)fnmsub_q (args unknown)fnmadd_q (args unknown)c_nop (args unknown)c_addi16sp (args unknown)c_jr (args unknown)c_jalr (args unknown)c_ebreak (args unknown)c_ld (args unknown)c_sd (args unknown)c_addiw (args unknown)c_ldsp (args unknown)c_sdsp (args unknown)c_addi4spn (args unknown)c_fld (args unknown)c_lw (args unknown)c_flw (args unknown)c_fsd (args unknown)c_sw (args unknown)c_fsw (args unknown)c_addi (args unknown)c_jal (args unknown)c_li (args unknown)c_lui (args unknown)c_srli (args unknown)c_srai (args unknown)c_andi (args unknown)c_sub (args unknown)c_xor (args unknown)c_or (args unknown)c_and (args unknown)c_subw (args unknown)c_addw (args unknown)c_j (args unknown)c_beqz (args unknown)c_bnez (args unknown)c_slli (args unknown)c_fldsp (args unknown)c_lwsp (args unknown)c_flwsp (args unknown)c_mv (args unknown)c_add (args unknown)c_fsdsp (args unknown)c_swsp (args unknown)c_fswsp (args unknown)custom0 (args unknown)custom0_rs1 (args unknown)custom0_rs1_rs2 (args unknown)custom0_rd (args unknown)custom0_rd_rs1 (args unknown)custom0_rd_rs1_rs2 (args unknown)custom1 (args unknown)custom1_rs1 (args unknown)custom1_rs1_rs2 (args unknown)custom1_rd (args unknown)custom1_rd_rs1 (args unknown)custom1_rd_rs1_rs2 (args unknown)custom2 (args unknown)custom2_rs1 (args unknown)custom2_rs1_rs2 (args unknown)custom2_rd (args unknown)custom2_rd_rs1 (args unknown)custom2_rd_rs1_rs2 (args unknown)custom3 (args unknown)custom3_rs1 (args unknown)custom3_rs1_rs2 (args unknown)custom3_rd (args unknown)custom3_rd_rs1 (args unknown)custom3_rd_rs1_rs2 (args unknown)vector::_M_realloc_insertbasic_string::_S_construct null not valid*5._125*5._124*5._123*5._122*5._121*5._120*5._119*5._118*5._117*5._116*5._115*5._114*5._113*5._112*5._111*5._110*5._109*5._108*5._107*5._106*5._105*5._104*5._103*5._102*5._101*5._100*4._99*4._98*4._97*4._96*4._95*4._94*4._93*4._92*4._915arg_t trap #%uinterrupt #%u6trap_tŝtNSt6thread6_StateENSt3_V214error_categoryEsystemgenericbasic_string::_M_construct null not valid*N12_GLOBAL__N_121system_error_categoryE*N12_GLOBAL__N_122generic_error_categoryEbasic_string::at: __n (which is %zu) >= this->size() (which is %zu)basic_string::copybasic_string::comparebasic_string::_M_replacebasic_string::_M_replace_auxbasic_string::appendbasic_string::assignbasic_string::insertbasic_string::replacebasic_string::_M_createbasic_string::basic_stringstring::stringSt20bad_array_new_lengthstd::bad_array_new_length0123456789not enough space for format expansion (Please submit full bug report at https://gcc.gnu.org/bugs/): NSt8ios_base7failureB5cxx11Eiostreamiostream errorUnknown error*N12_GLOBAL__N_117io_error_categoryE;t<0PF0DH>@?tRRf<fDzzHpx8HܬPH@< p 4 |0p1x1\HEPEY,YXm`m008xtЯ\د0Ģp8Ģޢ,ޢKNdlddLdfLj`m`mamPaw uH(uhu@إ੣|詣P8ѣѣ|h pT@H x 8 h' ,p'/@;t0H;88U8U@xpNp0foȔHP< <(ĤƤhǤ ئlԺ L((66`QhQt'l,(l*+3@4H9໥>軥F֥K֥N HO(4R R U`&Vh&_At`Af[k[p@v`qHvwz萦8Ʀ\ ƦXD:T:P;x<PxX PH4lI؆ I x]L ]x ]Ԛ ^ @^ ^ ^T _ @_ s4 sX t К ؚ  0 ¨( ¨(, `֨07 h֨P8 ר9 (? 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%P,%P,LT `M?D}\B tH tHHp,p,|,p,p,t, xH,<THDlYG   D          }}A@TDYG   D          }}@QB    ,  @    P }P@eT 4 tt            }}?YG   D          }}?4 hHDDYG   D          }}>t P$t P$!L$         d 7<h8h                                              7<L h      %<p}%<p}%<p}%<p}%<p}%<p}%<p}yoP     G         8  D t*pd      0 `T4 h   )4 M            8Pd !p@L%&2',(4)3+3,3-4/4043`# LH!@LH!@H8xl03       3       4      `, L %P,%P,LTUE}2<H tHHp,p,|,p,p,t,<L,<THDl8Pd !p@L%&2',(4)3+3,3-4/4043`# LH!@LH!@H8xl0/   /   4  `, L %P,%P,LTq^X            }}D. tHtH(p,p,|,p,p,t, xH,<T(Dl 8H\$&'(&*++x&t,x0x0,0((((( l lE8     }$(4(h(Xt|D$(4($(XX$,$($($(   P<7<h                                                     7<L h      8Pd (44/!p@L%&2',(4)3+3,3-4/4043`# LH!@LH!@H8xl03       3       4      `, L %P,%P,LTq^X            }}$! tHtH(p,p,|,p,p,t, xH,<THDl0#&''&*+*`&t,x0x0,0((((( l lE8     }XtH(,$(4(h(4($(XX$,$($($( 7<hI?                                               7<L h      8Pd !p@L%&2',(4)3+3,3-4/4043hx`#!,!x   } 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tHtH(p,p,|,p,p,t, xH,<THDl 7<hP                                               7<L h      .l&8Pd )@t}%<p}%<p}L                            !p@L%&2',(4)3+3,3-4/4043\/0GP     p      /`# LH!@LH!@H8xl03       3       4      `, L %P,%P,LTUE}d tH tHHp,p,|,p,p,t,<L,<THDl]O }) \$&'(&*++x&t,x0,x00((((( l lE8     },$(4(h(Xt|4($(XX$,$($($(   7<h                                              7<L h      B   )  l8Pd !p@L%&2',(4)3+3,3-4/4043`# LH!@LH!@H8xl03       3       4      `, L %P,%P,LTUE}` tHtH(p,p,|,p,p,t, xH,<THDl`                                              7<L h       .X8Pd %<p}%<p}iaHp !p@L%&2',(4)3+3,3-4/40434`# LH!@LH!@H8xl0/   /   4  `, L %P,%P,LTq^X            }}X tHtH(p,p,|,p,p,t, xH,<THDl}m0   }l7<h X08                                                 7<L h      %\}%<p}',  *  `8Pd )@t}                            ! !_     xi_       !p@L%&2',(4)3+3,3-4/4043`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}t(tH(p,p,|,p,p,t,x(, H(Dl 47<h  )H  h    )H  l                               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