## -------------------------------------------------------------- ## Copyright (R) @huawei.com, all rights reserved ## Text File ## FILE: davinci_mini.config ## DESC: Hardware specification for DaVinci-Mini ## CREATED: 2018-07-26 00:19:48 ## MODIFIED: 2018-07-26 00:19:48 ## -------------------------------------------------------------- @include fileToDir( configFile( ) ) + "/common.spec"; davinci { chip_version = ""; platform_type = "DVC_PLATFORM_LINUX"; dec_ddr_latency_to_trigger_barflag_error = "false"; platform_smmu_on = "false"; l2_size = "64 MB"; isa_tag = "6.0"; # ------------------------------------------------------------------- # BIU Specifications # ------------------------------------------------------------------- biu { port_num = "2"; icache_port = "0"; lsu_port = "1"; read_queue_size = "160"; write_queue_size = "64"; total_queue_size = "188"; high_priority_read_port = icache_port; high_priority_write_port = lsu_port; enable_memmap = "true"; ipu_port_width = "128 B"; # 1024/8 mte_data_size = "256 B"; mte_port_width = "128 B"; # 1024/8 mte_read_port_num = "2"; mte_write_port_num = "1"; bus_port_width = "128 B"; # 1024/8 bus_read_port_num = "2"; bus_write_port_num = "1"; write_buffer_depth = "4"; read_buffer_depth = "4"; ifu_read_queue_size = "4"; mem_entry_num = "64"; physical_mem_entry_num = "256"; # `mem_entry_size' will be calculated as l2_size/mem_entry_num }; # ------------------------------------------------------------------- # DDR Specifications # ------------------------------------------------------------------- # The Option 'DEC_DDR_LATENCY_TO_TRIGGER_BARFLAG_ERROR' bellow # is used to trigger Barrier Flag Error dec_ddr_latency_to_trigger_barflag_error = "false"; ddr { @if (dec_ddr_latency_to_trigger_barflag_error == "true") { min_read_latency = "1"; read_latency_diver = "1"; min_write_latency = "1"; write_latency_diver = "1"; } @else { min_read_latency = "150"; read_latency_diver = "180"; min_write_latency = "150"; write_latency_diver = "180"; } bandwidth_limit = "32"; max_credit_num = "4096"; }; # ------------------------------------------------------------------- # L2 Specifications # ------------------------------------------------------------------- l2 { bandwidth_limit = "110"; # read + write bandwidth, 96 B/ns read_bandwidth_limit = "110"; write_bandwidth_limit = "86"; max_credit_num = "4096"; min_read_latency = "60"; # 50ns: This number from Xu Weijia, according to Wu Xiaowen this delay is 23 tick read_latency_diver = "4"; min_write_latency = "60"; # 180ns: This number from Xu Weijia, according to Wu Xiaowen this delay is 26 tick write_latency_diver = "4"; }; # ------------------------------------------------------------------- # Cache Sepcifications # ------------------------------------------------------------------- cache { cache_line_width = "128 B"; # 1024/8 Byte cache_size = "32 KB"; }; # ------------------------------------------------------------------- # PSQ Sepcifications # ------------------------------------------------------------------- psq { buffer_size = "32"; # instr's fetch_size = "16 B"; # 4 * IAS_MAX_BYTES dispatch_size = "2"; # instr's }; # ------------------------------------------------------------------- # Issue Queue Specifications # ------------------------------------------------------------------- issue_queue { size = "32"; ostd_num = "32"; event_queue_size = "32"; event_queue_num = "6"; cube_issue_queue_size = "32"; cube_issue_queue_ostd_num = "16"; vec_issue_queue_size = "32"; vec_issue_queue_ostd_num = "32"; lsu_issue_queue_size = "32"; lsu_issue_queue_ostd_num = "32"; scalar_issue_queue_size = "1"; }; # ------------------------------------------------------------------- # Vector # ------------------------------------------------------------------- vector { scatter_ports = "8"; } # ------------------------------------------------------------------- # Unified Buffer Specifications # ------------------------------------------------------------------- ub { buffer_size = "256 KB"; buffer_line_size = "32 B"; # 256/8 B buffer_bank_count = "64"; # buffer_bank_size can be calcuated as buffer_size/buffer_bank_count vector_access_width = davinci.ub.buffer_line_size; # vector access width is always equals to L0_UB_BUFFER_LINE_SIZE scalar_access_width = davinci.ub.buffer_line_size; # scalar access width is always equals to L0_UB_BUFFER_LINE_SIZE lsu_write_port_num = "2"; # l0_ub_lsu_wr_port_width always euqals to 2*L0_UB_BUFFER_LINE_SIZE }; # ------------------------------------------------------------------- l1 { buffer_size = "1 MB"; buffer_bg_offset = "18"; buffer_bg_num = "4"; buffer_line_size = "16 B"; # 128/8 buffer_bank_count = "16"; # buffer_bank_size can be calculated from buffer_line_size/buffer_bank_count; core_access_width = "512"; # 4096/8 dmac_access_width = "256"; # 2048/8 }; # ------------------------------------------------------------------- # L0 Specifications # ------------------------------------------------------------------- l0 { ab_buffer_size = "64 KB"; ab_buffer_line_size = "512 B"; # 4096/8, no bank conflict in L0AB; don't care too much a_buffer_line_size = "512 B"; # 4096/8, no bank conflict in L0AB; don't care too much b_buffer_line_size = "256 B"; # 2048/8, no bank conflict in L0AB; don't care too much ab_buffer_bank_count = "32"; # ab_buffer_bank_size = l0_ab_buffer_size/l0_ab_buffer_bank_count ab_cube_access_width = "512 B"; # 4096/8, no bank conflict in L0AB; don't care too much ab_lsu_access_width = "512 B"; # 4096/8, no bank conflict in L0AB; don't care too much # l0-c specifications c_buffer_size = "256 KB"; c_buffer_line_size = "32 B"; # 256/8 c_buffer_bank_count = "32"; # c bank_size = l0_c_buffer_size/l0_c_buffer_count, which can be calculated on demand. c_cube_access_width = "1024 B"; c_vector_access_width = "1024 B"; c_vector_write_access_width = "256 B"; c_vector_read_access_width = "128 B"; c_buffer_line_size_ca = "32 B"; # 256/8 c_buffer_bank_count_ca = "16"; }; # ------------------------------------------------------------------- # Scalar Buffer Specifications # ------------------------------------------------------------------- scalar_buffer { base_address = "0x40000"; # 256K size = "16 KB"; @if (davinci.isa_tag == "6.0") { ld_instr_ostd = "0x6"; st_instr_ostd = "0x6"; ld_st_separate_req_port = "true"; ld_st_hazard_check_unit = "32"; } @else { ld_instr_ostd = "0x1"; st_instr_ostd = "0x1"; ld_st_separate_req_port = "true"; ld_st_hazard_check_unit = "32"; } }; # ------------------------------------------------------------------- # CA MTE Specifications # ------------------------------------------------------------------- mte { l1_read_bus_width = "512 B"; #4096/8 biu_write_bus_width = "64 B"; #512/8 unibuf_write_bus_width = "128 B"; #2*512/8 unzip_engine_num = "4"; l0_write_delay = "1"; l1_read_delay = "3"; l1_write_delay = "1"; unibuf_write_delay = "1"; # biu biu_mte_rob_slot_num = "192"; biu_mte_max_trans_size = "256"; #biu_mte_rob_size = biu_mte_rob_slot_num * biu_mte_max_trans_size, can always be calculated on demand biu_mte_read_tags = "160"; biu_mte_write_tags = "64"; biu_mte_read_ostd = "160"; biu_mte_write_ostd = "64"; default_repeat_time = "1"; max_biu_if_trans_size = biu_mte_max_trans_size; max_rd_tagfifo_size = "200"; lsu_biu_align_size = biu_write_bus_width; biu_cmdgen_delay = "1"; # comand scheduler max_crdt_ue_3d = "3"; max_crdt_l1_ue_2d = "3"; max_crdt_biu_ue_2d = "3"; max_crdt_l1_ue_dma = "3"; max_crdt_biu_ue_dma = "3"; max_crdt_ub_ue_dma = "3"; max_crdt_ue_unzip = "3"; max_crdt_ue_fmc = "3"; max_crdt_ue_fmd = "3"; max_crdt_ue_aipp = "3"; max_crdt_ue_ksparse = "3"; cmd_iq_arb_delay_time = "1"; cmd_arb_dispatch_delay_time = "3"; # rob read & write latency l1_read_rob_delay = "4"; ub_read_rob_delay = "3"; l0_read_rob_delay = "4"; uzp_read_rob_delay = "4"; fmd_read_rob_delay = "4"; write_rob_delay = "2"; ktable_read_rob_delay = "6"; # mte fmcd fmc_pad_value = "0x0"; fmcd_engine_num = "4"; fmcd_head_size = "32 B"; fmcd_mask_size = "16 B"; fmcd_ubread_width = "128 B"; #128B fmcd_biuwrite_width = "64 B"; fmcd_biuread_width = "128 B"; #fmc_seg_size (FMCD_UBREAD_WIDTH/FMCD_ENGINE_NUM) //32B #fmd_seg_size (FMCD_BIUREAD_WIDTH/FMCD_ENGINE_NUM) //32B cube_size = "16 B"; #fm_size = cube_size_*cube_size_ * 2; fmc_offset_boundry = "256"; fmc_header_size = "32"; max_fmc_uop_crdt = "3"; max_fmc_wheader_num = "4"; max_fetch_head_num = "64"; fmd_out_buffer_depth = "5"; fmd_mte_wdata_delay = "3"; # aipp min_h_res = "8"; max_h_res = "4096"; byte_per_pixel_in_l1 = "32"; y_dat_buf_size = "64"; uv_dat_buf_size = "64"; rgb_dat_buf_size = "128"; uv_upsample_buf_size = "4096"; # 512bx64 sync_buf_size = "96"; csc_buf_size = "24"; dtc_buf_size = "48"; cpadding_buf_size = "256"; pixels_per_trans = "8"; img_dat_channels = "3"; aipp_dat_buf_bubble = "3"; aipp_max_dtc_lat = "5"; aipp_dtc_u8_fp16_lat = "5"; aipp_dtc_u8_s8_lat = "1"; dma_buffer_size_dc = "8192"; dma_buffer_size_uc = "16384"; dma_y_ping_buf_addr_uc = "0x0"; dma_y_pong_buf_addr_uc = "0x4000"; dma_uv_ping_buf_addr_dc = "0x0"; dma_uv_pong_buf_addr_dc = "0x2000"; dma_y_ping_buf_addr_dc = "0x4000"; dma_y_pong_buf_addr_dc = "0x6000"; # img2col img2col_c0_size = "16"; # l1 interface max_l1_uop_crdt = "5"; l1_to_l0_delay = "3"; l1_to_ub_delay = "4"; l1_to_ub_delay_2 = "2"; # ub interface max_ub_uop_crdt = "3"; ub_to_l1_req_delay = "2"; rtl_delay = "2"; # unzip uop unzip_fm_size = "512"; unzip_pkt_size = "8 B"; unzip_head_size = "8 B"; unzip_dict_size = "34 B"; unzip_out_len = "64 B"; unzip_seg_size = "32 B"; unzip_buffer_size = "32768"; unzip_entry_size = "2"; max_fetch_idx_num = "64"; max_uzp_uop_crdt = "3"; unzip_delay_time = "4"; unzip_bypass_delay_time = "2"; unzip_buffer_depth = "2"; # uop ue_2d_delay = "1"; ue_3d_delay = "5"; ue_dma_delay = "1"; ue_smask_delay = "1"; # biu to buffer bus width biu_to_l1_bus_width = "256 B"; #2048/8 biu_to_l0a_bus_width = "128 B"; #1024/8 biu_to_l0b_bus_width = "128 B"; #1024/8 biu_to_ub_bus_width = "128 B"; #1024/8 #ub2out switch ub2out_read_switch = "1"; }; # ------------------------------------------------------------------- # CA Cube Specifications # ------------------------------------------------------------------- cube { cube_dummy_cycle_number = "8"; cube_spec_npe = "256"; cube_spec_cube_size = "16"; global_sync_pulse_phase_type = "1"; vdrop_tick = "48"; ## from Guo Zhenyi }; # ------------------------------------------------------------------- # dump # ------------------------------------------------------------------- dump { file_print_level = "2"; screen_print_level = "3"; flush_level = "3"; #trace = 0, debug = 1, info = 2, warn = 3, error = 4, critical = 5, off = 6 }; # ------------------------------------------------------------------- # CA Icache Specifications # ------------------------------------------------------------------- icache { ic_addr_width = "46"; ic_asso_num = "2"; ic_size = "32768"; #32*1024 ic_line_size = "128"; #1024/8 ic_entry_num = "128"; #(ic_size/ic_line_size)/ic_asso_num ic_line_num = "256"; #(ic_size/ic_line_size) ic_prefetch_num = "3"; ic_max_otsd_num = "4"; # icache->biu req max num ic_max_preload_num = "3"; # icache->biu preload req max num invalid_cache_line_num = "0xffffffff"; ic_idx_addr_lsb = "7"; ic_idx_addr_mask = "0x7f"; ic_tag_addr_lsb = "14"; ic_tag_addr_mask = "0x1ffffffff"; }; };