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EnumE_ZN10config4cpp15SchemaTypeFloatD2Ev_ZTVN10config4cpp15SchemaTypeFloatE_ZN10config4cpp15SchemaTypeFloatD1Ev_ZN10config4cpp15SchemaTypeFloatD0Ev_ZNK10config4cpp15SchemaTypeFloat9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp15SchemaTypeFloat3isAEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_RKNS_12StringVectorEiRNS_12StringBufferE_ZTIN10config4cpp15SchemaTypeFloatE_ZTSN10config4cpp15SchemaTypeFloatE_ZN10config4cpp24SchemaTypeFloatWithUnitsD2Ev_ZTVN10config4cpp24SchemaTypeFloatWithUnitsE_ZN10config4cpp24SchemaTypeFloatWithUnitsD1Ev_ZN10config4cpp24SchemaTypeFloatWithUnitsD0Ev_ZNK10config4cpp24SchemaTypeFloatWithUnits9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp24SchemaTypeFloatWithUnits3isAEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_RKNS_12StringVectorEiRNS_12StringBufferE_ZTIN10config4cpp24SchemaTypeFloatWithUnitsE_ZTSN10config4cpp24SchemaTypeFloatWithUnitsE_ZN10config4cpp13SchemaTypeIntD2Ev_ZTVN10config4cpp13SchemaTypeIntE_ZN10config4cpp13SchemaTypeIntD1Ev_ZN10config4cpp13SchemaTypeIntD0Ev_ZNK10config4cpp13SchemaTypeInt9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp13SchemaTypeInt3isAEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_RKNS_12StringVectorEiRNS_12StringBufferE_ZTIN10config4cpp13SchemaTypeIntE_ZTSN10config4cpp13SchemaTypeIntE_ZN10config4cpp22SchemaTypeIntWithUnitsD2Ev_ZTVN10config4cpp22SchemaTypeIntWithUnitsE_ZN10config4cpp22SchemaTypeIntWithUnitsD1Ev_ZN10config4cpp22SchemaTypeIntWithUnitsD0Ev_ZNK10config4cpp22SchemaTypeIntWithUnits9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp22SchemaTypeIntWithUnits3isAEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_RKNS_12StringVectorEiRNS_12StringBufferE_ZTIN10config4cpp22SchemaTypeIntWithUnitsE_ZTSN10config4cpp22SchemaTypeIntWithUnitsE_ZN10config4cpp14SchemaTypeListD2Ev_ZTVN10config4cpp14SchemaTypeListE_ZN10config4cpp14SchemaTypeListD1Ev_ZN10config4cpp14SchemaTypeListD0Ev_ZNK10config4cpp14SchemaTypeList9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp14SchemaTypeList8validateEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_S8_S8_RKNS_12StringVectorEi_ZTIN10config4cpp14SchemaTypeListE_ZTSN10config4cpp14SchemaTypeListE_ZN10config4cpp25SchemaTypeMemorySizeBytesD2Ev_ZTVN10config4cpp25SchemaTypeMemorySizeBytesE_ZN10config4cpp25SchemaTypeMemorySizeBytesD1Ev_ZN10config4cpp25SchemaTypeMemorySizeBytesD0Ev_ZNK10config4cpp25SchemaTypeMemorySizeBytes9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp25SchemaTypeMemorySizeBytes3isAEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_RKNS_12StringVectorEiRNS_12StringBufferE_ZTIN10config4cpp25SchemaTypeMemorySizeBytesE_ZTSN10config4cpp25SchemaTypeMemorySizeBytesE_ZN10config4cpp22SchemaTypeMemorySizeKBD2Ev_ZTVN10config4cpp22SchemaTypeMemorySizeKBE_ZN10config4cpp22SchemaTypeMemorySizeKBD1Ev_ZN10config4cpp22SchemaTypeMemorySizeKBD0Ev_ZNK10config4cpp22SchemaTypeMemorySizeKB9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp22SchemaTypeMemorySizeKB3isAEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_RKNS_12StringVectorEiRNS_12StringBufferE_ZTIN10config4cpp22SchemaTypeMemorySizeKBE_ZTSN10config4cpp22SchemaTypeMemorySizeKBE_ZN10config4cpp22SchemaTypeMemorySizeMBD2Ev_ZTVN10config4cpp22SchemaTypeMemorySizeMBE_ZN10config4cpp22SchemaTypeMemorySizeMBD1Ev_ZN10config4cpp22SchemaTypeMemorySizeMBD0Ev_ZNK10config4cpp22SchemaTypeMemorySizeMB9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp22SchemaTypeMemorySizeMB3isAEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_RKNS_12StringVectorEiRNS_12StringBufferE_ZTIN10config4cpp22SchemaTypeMemorySizeMBE_ZTSN10config4cpp22SchemaTypeMemorySizeMBE_ZN10config4cpp15SchemaTypeScopeD2Ev_ZTVN10config4cpp15SchemaTypeScopeE_ZN10config4cpp15SchemaTypeScopeD1Ev_ZN10config4cpp15SchemaTypeScopeD0Ev_ZNK10config4cpp15SchemaTypeScope9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp15SchemaTypeScope8validateEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_S8_S8_RKNS_12StringVectorEi_ZTIN10config4cpp15SchemaTypeScopeE_ZTSN10config4cpp15SchemaTypeScopeE_ZN10config4cpp16SchemaTypeStringD2Ev_ZTVN10config4cpp16SchemaTypeStringE_ZN10config4cpp16SchemaTypeStringD1Ev_ZN10config4cpp16SchemaTypeStringD0Ev_ZNK10config4cpp16SchemaTypeString9checkRuleEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcRKNS_12StringVectorES8__ZNK10config4cpp16SchemaTypeString3isAEPKNS_15SchemaValidatorEPKNS_13ConfigurationEPKcS8_RKNS_12StringVectorEiRNS_12StringBufferE_ZTIN10config4cpp16SchemaTypeStringE_ZTSN10config4cpp16SchemaTypeStringE_ZN10config4cpp15SchemaTypeTableD2Ev_ZTVN10config4cpp15SchemaTypeTableE_ZN10config4cpp15SchemaTypeTableD1Ev_ZN10config4cpp15SchemaTypeTableD0Ev_ZNK10config4c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tract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE3endEv_ZNKSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE8key_compEv_ZNSt23_Rb_tree_const_iteratorISt4pairIKmP17abstract_device_tEEC2ERKSt17_Rb_tree_iteratorIS4_E_ZSt7forwardISt5tupleIJRKmEEEOT_RNSt16remove_referenceIS4_E4typeE_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE14_M_create_nodeIJRKSt21piecewise_construct_tSt5tupleIJRS1_EESF_IJEEEEEPSt13_Rb_tree_nodeIS4_EDpOT__ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE6_S_keyEPKSt13_Rb_tree_nodeIS4_E_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS1__ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE14_M_insert_nodeEPSt18_Rb_tree_node_baseSC_PSt13_Rb_tree_nodeIS4_E_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE12_M_drop_nodeEPSt13_Rb_tree_nodeIS4_E_ZNSt17_Rb_tree_iteratorISt4pairIKmP17abstract_device_tEEC1EPSt18_Rb_tree_node_base_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE8_M_beginEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE6_M_endEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE14_M_upper_boundEPSt13_Rb_tree_nodeIS4_EPSt18_Rb_tree_node_baseRS1__ZN9__gnu_cxx16__aligned_membufISt4pairIKmP17abstract_device_tEE6_M_ptrEv_ZN9__gnu_cxx13new_allocatorISt13_Rb_tree_nodeISt4pairIKSsSt8functionIFP17abstract_device_tRS3_EEEEEC1Ev_ZN9__gnu_cxx13new_allocatorISt13_Rb_tree_nodeISt4pairIKSsSt8functionIFP17abstract_device_tRS3_EEEEED1Ev_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE8_S_rightEPSt18_Rb_tree_node_base_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE7_S_leftEPSt18_Rb_tree_node_base_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE12_M_drop_nodeEPSt13_Rb_tree_nodeIS8_E_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE11lower_boundES5__ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE3endEv_ZNKSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE8key_compEv_ZNSt13_Rb_tree_nodeISt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEEE9_M_valptrEv_ZStltIcSt11char_traitsIcESaIcEEbRKSbIT_T0_T1_ES8__ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE14_M_create_nodeIJRSsRS7_EEEPSt13_Rb_tree_nodeIS8_EDpOT__ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE6_S_keyEPKSt13_Rb_tree_nodeIS8_E_ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE24_M_get_insert_unique_posES5__ZNSt8_Rb_treeISsSt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEESt10_Select1stIS8_ESt4lessISsESaIS8_EE14_M_insert_nodeEPSt18_Rb_tree_node_baseSG_PSt13_Rb_tree_nodeIS8_E_ZNSt4pairISt17_Rb_tree_iteratorIS_IKSsSt8functionIFP17abstract_device_tRS1_EEEEbEC1IS9_bLb1EEEOT_OT0__ZNSt17_Rb_tree_iteratorISt4pairIKSsSt8functionIFP17abstract_device_tRS1_EEEEC1EPSt18_Rb_tree_node_base_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE14_M_lower_boundEPSt13_Rb_tree_nodeIS4_EPSt18_Rb_tree_node_baseRS1__ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE11_M_get_nodeEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE17_M_construct_nodeIJRKSt21piecewise_construct_tSt5tupleIJRS1_EESF_IJEEEEEvPSt13_Rb_tree_nodeIS4_EDpOT__ZNKSt23_Rb_tree_const_iteratorISt4pairIKmP17abstract_device_tEE13_M_const_castEv_ZNKSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE4sizeEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE12_M_rightmostEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE6_S_keyEPKSt18_Rb_tree_node_base_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE24_M_get_insert_unique_posERS1__ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE11_M_leftmostEv_ZNSt17_Rb_tree_iteratorISt4pairIKmP17abstract_device_tEEmmEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE8_S_rightEPSt18_Rb_tree_node_base_ZNSt17_Rb_tree_iteratorISt4pairIKmP17abstract_device_tEEppEv_ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_EE8_S_valueEPKSt13_Rb_tree_nodeIS4_E_ZNKSt10_Select1stISt4pairIKmP17abstract_device_tEEclERKS4__ZNSt8_Rb_treeImSt4pairIKmP17abstract_device_tESt10_Select1stIS4_ESt4lessImESaIS4_E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ְgG"? ְgGB? ְgGb? ְgG? ְgG? ְgG? ְgG? g@ g@" g @B g@b g@ g@ g@ g@ g"@ g&@" g*@B g.@b g2@ g6@ g:@ g>@ gB@ gF@" gJ@B gN@b gR@ gV@ gZ@ g^@ gb@ gf@" gj@B gn@b gr@ gv@ gz@ g~@ g@ g@" g@B g@b g@ g@ g@ g@ g@ g@" g@B g@b g@ g@ g@ g@ g@ g@" g@B g@b g@ g@ g@ g@ g@ g@" g@B g@b g@ g@ g@ g@ gA gA" g AB gAb gA gA gA gA g"A g&A" g*AB g.Ab g2A g6A g:A g>A gBA gFA" gJAB gNAb gRA gVA gZA g^A gbA gfA" gjAB gnAb grA gvA gzA g~A gA gA" gAB gAb gA gA gA gA gA gA" gAB gAb gA gA gA gA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgB ְgB" ְg BB ְgBb ְgB ְgB ְgB ְgB ְg"B ְg&B" ְg*BB ְg.Bb ְg2B ְg6B ְg:B ְg>B ְgBB ְgFB" ְgJBB ְgNBb ְgRB ְgVB ְgZB ְg^B ְgbB ְgfB" ְgjBB ְgnBb ְgrB ְgvB ְgzB ְg~B ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgC ְgC" ְg CB ְgCb ְgC ְgC ְgC ְgC ְg"C ְg&C" ְg*CB ְg.Cb ְg2C ְg6C ְg:C ְg>C ְgBC ְgFC" ְgJCB ְgNCb ְgRC ְgVC ְgZC ְg^C ְgbC ְgfC" ְgjCB ְgnCb ְgrC ְgvC ְgzC ְg~C ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgD ְgD" ְg DB ְgDb ְgD ְgD ְgD ְgD ְg"D! ְg&D"! ְg*DB! ְg.Db! ְg2D! ְg6D! ְg:D! ְg>D! ְgBD" ְgFD"" ְgJDB" ְgNDb" ְgRD" ְgVD" ְgZD" ְg^D" ְgbD# ְgfD"# ְgjDB# ְgnDb# ְgrD# ְgvD# ְgzD# ְg~D# ְgD$ ְgD"$ ְgDB$ ְgDb$ ְgD$ ְgD$ ְgD$ ְgD$ ְgD% ְgD"% ְgDB% ְgDb% ְgD% ְgD% ְgD% ְgD% ְgD& ְgD"& ְgDB& ְgDb& ְgD& ְgD& ְgD& ְgD& ְgD' ְgD"' ְgDB' ְgDb' ְgD' ְgD' ְgD' ְgD' ְgE( ְgE"( ְg EB( ְgEb( ְgE( ְgE( ְgE( ְgE( ְg"E) ְg&E") ְg*EB) ְg.Eb) ְg2E) ְg6E) ְg:E) ְg>E) ְgBE* ְgFE"* ְgJEB* ְgNEb* ְgRE* ְgVE* ְgZE* ְg^E* ְgbE+ ְgfE"+ ְgjEB+ ְgnEb+ ְgrE+ ְgvE+ ְgzE+ ְg~E+ ְgE, ְgE", ְgEB, ְgEb, ְgE, ְgE, ְgE, ְgE, ְgE- ְgE"- ְgEB- ְgEb- ְgE- ְgE- ְgE- ְgE- ְgE. ְgE". ְgEB. ְgEb. ְgE. ְgE. ְgE. ְgE. ְgE/ ְgE"/ ְgEB/ ְgEb/ ְgE/ ְgE/ ְgE/ ְgE/ ְgF0 ְgF"0 ְg FB0 ְgFb0 ְgF0 ְgF0 ְgF0 ְgF0 ְg"F1 ְg&F"1 ְg*FB1 ְg.Fb1 ְg2F1 ְg6F1 ְg:F1 ְg>F1 ְgBF2 ְgFF"2 ְgJFB2 ְgNFb2 ְgRF2 ְgVF2 ְgZF2 ְg^F2 ְgbF3 ְgfF"3 ְgjFB3 ְgnFb3 ְgrF3 ְgvF3 ְgzF3 ְg~F3 ְgF4 ְgF"4 ְgFB4 ְgFb4 ְgF4 ְgF4 ְgF4 ְgF4 ְgF5 ְgF"5 ְgFB5 ְgFb5 ְgF5 ְgF5 ְgF5 ְgF5 ְgF6 ְgF"6 ְgFB6 ְgFb6 ְgF6 ְgF6 ְgF6 ְgF6 ְgF7 ְgF"7 ְgFB7 ְgFb7 ְgF7 ְgF7 ְgF7 ְgF7 ְgG8 ְgG"8 ְg GB8 ְgGb8 ְgG8 ְgG8 ְgG8 ְgG8 ְg"G9 ְg&G"9 ְg*GB9 ְg.Gb9 ְg2G9 ְg6G9 ְg:G9 ְg>G9 ְgBG: ְgFG": ְgJGB: ְgNGb: ְgRG: ְgVG: ְgZG: ְg^G: ְgbG; ְgfG"; ְgjGB; ְgnGb; ְgrG; ְgvG; ְgzG; ְg~G; ְgG< ְgG"< ְgGB< ְgGb< ְgG< ְgG< ְgG< ְgG< ְgG= ְgG"= ְgGB= ְgGb= ְgG= ְgG= ְgG= ְgG= ְgG> ְgG"> ְgGB> ְgGb> ְgG> ְgG> ְgG> ְgG> ְgG? ְgG"? ְgGB? ְgGb? ְgG? ְgG? ְgG? ְgG? ְg@ ְg@" ְg @B ְg@b ְg@ ְg@ ְg@ ְg@ ְg"@ ְg&@" ְg*@B ְg.@b ְg2@ ְg6@ ְg:@ ְg>@ ְgB@ ְgF@" ְgJ@B ְgN@b ְgR@ ְgV@ ְgZ@ ְg^@ ְgb@ ְgf@" ְgj@B ְgn@b ְgr@ ְgv@ ְgz@ ְg~@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְgA ְgA" ְg AB ְgAb ְgA ְgA ְgA ְgA ְg"A ְg&A" ְg*AB ְg.Ab ְg2A ְg6A ְg:A ְg>A ְgBA ְgFA" ְgJAB ְgNAb ְgRA ְgVA ְgZA ְg^A ְgbA ְgfA" ְgjAB ְgnAb ְgrA ְgvA ְgzA ְg~A ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgB ְgB" ְg BB ְgBb ְgB ְgB ְgB ְgB ְg"B ְg&B" ְg*BB ְg.Bb ְg2B ְg6B ְg:B ְg>B ְgBB ְgFB" ְgJBB ְgNBb ְgRB ְgVB ְgZB ְg^B ְgbB ְgfB" ְgjBB ְgnBb ְgrB ְgvB ְgzB ְg~B ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgC ְgC" ְg CB ְgCb ְgC ְgC ְgC ְgC ְg"C ְg&C" ְg*CB ְg.Cb ְg2C ְg6C ְg:C ְg>C ְgBC ְgFC" ְgJCB ְgNCb ְgRC ְgVC ְgZC ְg^C ְgbC ְgfC" ְgjCB ְgnCb ְgrC ְgvC ְgzC ְg~C ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgD ְgD" ְg DB ְgDb ְgD ְgD ְgD ְgD ְg"D! ְg&D"! ְg*DB! ְg.Db! ְg2D! ְg6D! ְg:D! ְg>D! ְgBD" ְgFD"" ְgJDB" ְgNDb" ְgRD" ְgVD" ְgZD" ְg^D" ְgbD# ְgfD"# ְgjDB# ְgnDb# ְgrD# ְgvD# ְgzD# ְg~D# ְgD$ ְgD"$ ְgDB$ ְgDb$ ְgD$ ְgD$ ְgD$ ְgD$ ְgD% ְgD"% ְgDB% ְgDb% ְgD% ְgD% ְgD% ְgD% ְgD& ְgD"& ְgDB& ְgDb& ְgD& ְgD& ְgD& ְgD& ְgD' ְgD"' ְgDB' ְgDb' ְgD' ְgD' ְgD' ְgD' ְgE( ְgE"( ְg EB( ְgEb( ְgE( ְgE( ְgE( ְgE( ְg"E) ְg&E") ְg*EB) ְg.Eb) ְg2E) ְg6E) ְg:E) ְg>E) ְgBE* ְgFE"* ְgJEB* ְgNEb* ְgRE* ְgVE* ְgZE* ְg^E* ְgbE+ ְgfE"+ ְgjEB+ ְgnEb+ ְgrE+ ְgvE+ ְgzE+ ְg~E+ ְgE, ְgE", ְgEB, ְgEb, ְgE, ְgE, ְgE, ְgE, ְgE- ְgE"- ְgEB- ְgEb- ְgE- ְgE- ְgE- ְgE- ְgE. ְgE". ְgEB. ְgEb. ְgE. ְgE. ְgE. ְgE. ְgE/ ְgE"/ ְgEB/ ְgEb/ ְgE/ ְgE/ ְgE/ ְgE/ ְgF0 ְgF"0 ְg FB0 ְgFb0 ְgF0 ְgF0 ְgF0 ְgF0 ְg"F1 ְg&F"1 ְg*FB1 ְg.Fb1 ְg2F1 ְg6F1 ְg:F1 ְg>F1 ְgBF2 ְgFF"2 ְgJFB2 ְgNFb2 ְgRF2 ְgVF2 ְgZF2 ְg^F2 ְgbF3 ְgfF"3 ְgjFB3 ְgnFb3 ְgrF3 ְgvF3 ְgzF3 ְg~F3 ְgF4 ְgF"4 ְgFB4 ְgFb4 ְgF4 ְgF4 ְgF4 ְgF4 ְgF5 ְgF"5 ְgFB5 ְgFb5 ְgF5 ְgF5 ְgF5 ְgF5 ְgF6 ְgF"6 ְgFB6 ְgFb6 ְgF6 ְgF6 ְgF6 ְgF6 ְgF7 ְgF"7 ְgFB7 ְgFb7 ְgF7 ְgF7 ְgF7 ְgF7 ְgG8 ְgG"8 ְg GB8 ְgGb8 ְgG8 ְgG8 ְgG8 ְgG8 ְg"G9 ְg&G"9 ְg*GB9 ְg.Gb9 ְg2G9 ְg6G9 ְg:G9 ְg>G9 ְgBG: ְgFG": ְgJGB: ְgNGb: ְgRG: ְgVG: ְgZG: ְg^G: ְgbG; ְgfG"; ְgjGB; ְgnGb; ְgrG; ְgvG; ְgzG; ְg~G; ְgG< ְgG"< ְgGB< ְgGb< ְgG< ְgG< ְgG< ְgG< ְgG= ְgG"= ְgGB= ְgGb= ְgG= ְgG= ְgG= ְgG= ְgG> ְgG"> ְgGB> ְgGb> ְgG> ְgG> ְgG> ְgG> ְgG? ְgG"? ְgGB? ְgGb? ְgG? ְgG? ְgG? ְgG? ְg@ ְg@" ְg @B ְg@b ְg@ ְg@ ְg@ ְg@ ְg"@ ְg&@" ְg*@B ְg.@b ְg2@ ְg6@ ְg:@ ְg>@ ְgB@ ְgF@" ְgJ@B ְgN@b ְgR@ ְgV@ ְgZ@ ְg^@ ְgb@ ְgf@" ְgj@B ְgn@b ְgr@ ְgv@ ְgz@ ְg~@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְgA ְgA" ְg AB ְgAb ְgA ְgA ְgA ְgA ְg"A ְg&A" ְg*AB ְg.Ab ְg2A ְg6A ְg:A ְg>A ְgBA ְgFA" ְgJAB ְgNAb ְgRA ְgVA ְgZA ְg^A ְgbA ְgfA" ְgjAB ְgnAb ְgrA ְgvA ְgzA ְg~A ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgB ְgB" ְg BB ְgBb ְgB ְgB ְgB ְgB ְg"B ְg&B" ְg*BB ְg.Bb ְg2B ְg6B ְg:B ְg>B ְgBB ְgFB" ְgJBB ְgNBb ְgRB ְgVB ְgZB ְg^B ְgbB ְgfB" ְgjBB ְgnBb ְgrB ְgvB ְgzB ְg~B ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgC ְgC" ְg CB ְgCb ְgC ְgC ְgC ְgC ְg"C ְg&C" ְg*CB ְg.Cb ְg2C ְg6C ְg:C ְg>C ְgBC ְgFC" ְgJCB ְgNCb ְgRC ְgVC ְgZC ְg^C ְgbC ְgfC" ְgjCB ְgnCb ְgrC ְgvC ְgzC ְg~C ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgD ְgD" ְg DB ְgDb ְgD ְgD ְgD ְgD ְg"D! ְg&D"! ְg*DB! ְg.Db! ְg2D! ְg6D! ְg:D! ְg>D! ְgBD" ְgFD"" ְgJDB" ְgNDb" ְgRD" ְgVD" ְgZD" ְg^D" ְgbD# ְgfD"# ְgjDB# ְgnDb# ְgrD# ְgvD# ְgzD# ְg~D# ְgD$ ְgD"$ ְgDB$ ְgDb$ ְgD$ ְgD$ ְgD$ ְgD$ ְgD% ְgD"% ְgDB% ְgDb% ְgD% ְgD% ְgD% ְgD% ְgD& ְgD"& ְgDB& ְgDb& ְgD& ְgD& ְgD& ְgD& ְgD' ְgD"' ְgDB' ְgDb' ְgD' ְgD' ְgD' ְgD' ְgE( ְgE"( ְg EB( ְgEb( ְgE( ְgE( ְgE( ְgE( ְg"E) ְg&E") ְg*EB) ְg.Eb) ְg2E) ְg6E) ְg:E) ְg>E) ְgBE* ְgFE"* ְgJEB* ְgNEb* ְgRE* ְgVE* ְgZE* ְg^E* ְgbE+ ְgfE"+ ְgjEB+ ְgnEb+ ְgrE+ ְgvE+ ְgzE+ ְg~E+ ְgE, ְgE", ְgEB, ְgEb, ְgE, ְgE, ְgE, ְgE, ְgE- ְgE"- ְgEB- ְgEb- ְgE- ְgE- ְgE- ְgE- ְgE. ְgE". ְgEB. ְgEb. ְgE. ְgE. ְgE. ְgE. ְgE/ ְgE"/ ְgEB/ ְgEb/ ְgE/ ְgE/ ְgE/ ְgE/ ְgF0 ְgF"0 ְg FB0 ְgFb0 ְgF0 ְgF0 ְgF0 ְgF0 ְg"F1 ְg&F"1 ְg*FB1 ְg.Fb1 ְg2F1 ְg6F1 ְg:F1 ְg>F1 ְgBF2 ְgFF"2 ְgJFB2 ְgNFb2 ְgRF2 ְgVF2 ְgZF2 ְg^F2 ְgbF3 ְgfF"3 ְgjFB3 ְgnFb3 ְgrF3 ְgvF3 ְgzF3 ְg~F3 ְgF4 ְgF"4 ְgFB4 ְgFb4 ְgF4 ְgF4 ְgF4 ְgF4 ְgF5 ְgF"5 ְgFB5 ְgFb5 ְgF5 ְgF5 ְgF5 ְgF5 ְgF6 ְgF"6 ְgFB6 ְgFb6 ְgF6 ְgF6 ְgF6 ְgF6 ְgF7 ְgF"7 ְgFB7 ְgFb7 ְgF7 ְgF7 ְgF7 ְgF7 ְgG8 ְgG"8 ְg GB8 ְgGb8 ְgG8 ְgG8 ְgG8 ְgG8 ְg"G9 ְg&G"9 ְg*GB9 ְg.Gb9 ְg2G9 ְg6G9 ְg:G9 ְg>G9 ְgBG: ְgFG": ְgJGB: ְgNGb: ְgRG: ְgVG: ְgZG: ְg^G: ְgbG; ְgfG"; ְgjGB; ְgnGb; ְgrG; ְgvG; ְgzG; ְg~G; ְgG< ְgG"< ְgGB< ְgGb< ְgG< ְgG< ְgG< ְgG< ְgG= ְgG"= ְgGB= ְgGb= ְgG= ְgG= ְgG= ְgG= ְgG> ְgG"> ְgGB> ְgGb> ְgG> ְgG> ְgG> ְgG> ְgG? ְgG"? ְgGB? ְgGb? ְgG? ְgG? ְgG? ְgG? ְg@ ְg@" ְg @B ְg@b ְg@ ְg@ ְg@ ְg@ ְg"@ ְg&@" ְg*@B ְg.@b ְg2@ ְg6@ ְg:@ ְg>@ ְgB@ ְgF@" ְgJ@B ְgN@b ְgR@ ְgV@ ְgZ@ ְg^@ ְgb@ ְgf@" ְgj@B ְgn@b ְgr@ ְgv@ ְgz@ ְg~@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְgA ְgA" ְg AB ְgAb ְgA ְgA ְgA ְgA ְg"A ְg&A" ְg*AB ְg.Ab ְg2A ְg6A ְg:A ְg>A ְgBA ְgFA" ְgJAB ְgNAb ְgRA ְgVA ְgZA ְg^A ְgbA ְgfA" ְgjAB ְgnAb ְgrA ְgvA ְgzA ְg~A ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgB ְgB" ְg BB ְgBb ְgB ְgB ְgB ְgB ְg"B ְg&B" ְg*BB ְg.Bb ְg2B ְg6B ְg:B ְg>B ְgBB ְgFB" ְgJBB ְgNBb ְgRB ְgVB ְgZB ְg^B ְgbB ְgfB" ְgjBB ְgnBb ְgrB ְgvB ְgzB ְg~B ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgB ְgB" ְgBB ְgBb ְgB ְgB ְgB ְgB ְgC ְgC" ְg CB ְgCb ְgC ְgC ְgC ְgC ְg"C ְg&C" ְg*CB ְg.Cb ְg2C ְg6C ְg:C ְg>C ְgBC ְgFC" ְgJCB ְgNCb ְgRC ְgVC ְgZC ְg^C ְgbC ְgfC" ְgjCB ְgnCb ְgrC ְgvC ְgzC ְg~C ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgC ְgC" ְgCB ְgCb ְgC ְgC ְgC ְgC ְgD ְgD" ְg DB ְgDb ְgD ְgD ְgD ְgD ְg"D! ְg&D"! ְg*DB! ְg.Db! ְg2D! ְg6D! ְg:D! ְg>D! ְgBD" ְgFD"" ְgJDB" ְgNDb" ְgRD" ְgVD" ְgZD" ְg^D" ְgbD# ְgfD"# ְgjDB# ְgnDb# ְgrD# ְgvD# ְgzD# ְg~D# ְgD$ ְgD"$ ְgDB$ ְgDb$ ְgD$ ְgD$ ְgD$ ְgD$ ְgD% ְgD"% ְgDB% ְgDb% ְgD% ְgD% ְgD% ְgD% ְgD& ְgD"& ְgDB& ְgDb& ְgD& ְgD& ְgD& ְgD& ְgD' ְgD"' ְgDB' ְgDb' ְgD' ְgD' ְgD' ְgD' ְgE( ְgE"( ְg EB( ְgEb( ְgE( ְgE( ְgE( ְgE( ְg"E) ְg&E") ְg*EB) ְg.Eb) ְg2E) ְg6E) ְg:E) ְg>E) ְgBE* ְgFE"* ְgJEB* ְgNEb* ְgRE* ְgVE* ְgZE* ְg^E* ְgbE+ ְgfE"+ ְgjEB+ ְgnEb+ ְgrE+ ְgvE+ ְgzE+ ְg~E+ ְgE, ְgE", ְgEB, ְgEb, ְgE, ְgE, ְgE, ְgE, ְgE- ְgE"- ְgEB- ְgEb- ְgE- ְgE- ְgE- ְgE- ֐gE. ֐gE". ֐gEB. ֐gEb. ֐gE. ֐gE. ֐gE. ֐gE. ֐gE/ ֐gE"/ ֐gEB/ ֐gEb/ ֐gE/ ֐gE/ ֐gE/ ֐gE/ ֐gF0 ֐gF"0 ֐g FB0 ֐gFb0 ֐gF0 ֐gF0 ֐gF0 ֐gF0 ֐g"F1 ֐g&F"1 ֐g*FB1 ֐g.Fb1 ֐g2F1 ֐g6F1 ֐g:F1 ֐g>F1 ֐gBF2 ֐gFF"2 ֐gJFB2 ֐gNFb2 ֐gRF2 ֐gVF2 ֐gZF2 ֐g^F2 ֐gbF3 ֐gfF"3 ֐gjFB3 ֐gnFb3 ֐grF3 ֐gvF3 ֐gzF3 ֐g~F3 ֐gF4 ֐gF"4 ֐gFB4 ֐gFb4 ֐gF4 ֐gF4 ֐gF4 ֐gF4 ֐gF5 ֐gF"5 ֐gFB5 ֐gFb5 ֐gF5 ֐gF5 ֐gF5 ֐gF5 ֐gF6 ֐gF"6 ֐gFB6 ֐gFb6 ֐gF6 ֐gF6 ֐gF6 ֐gF6 ֐gF7 ֐gF"7 ֐gFB7 ֐gFb7 ֐gF7 ֐gF7 ֐gF7 ֐gF7 ֐gG8 ֐gG"8 ֐g GB8 ֐gGb8 ֐gG8 ֐gG8 ֐gG8 ֐gG8 ֐g"G9 ֐g&G"9 ֐g*GB9 ֐g.Gb9 ֐g2G9 ֐g6G9 ֐g:G9 ֐g>G9 ֐gBG: ֐gFG": ֐gJGB: ֐gNGb: ֐gRG: ֐gVG: ֐gZG: ֐g^G: ֐gbG; ֐gfG"; ֐gjGB; ֐gnGb; ֐grG; ֐gvG; ֐gzG; ֐g~G; ֐gG< ֐gG"< ֐gGB< ֐gGb< ֐gG< ֐gG< ֐gG< ֐gG< ֐gG= ֐gG"= ֐gGB= ֐gGb= ֐gG= ֐gG= ֐gG= ֐gG= ֐gG> ֐gG"> ֐gGB> ֐gGb> ֐gG> ֐gG> ֐gG> ֐gG> ֐gG? ֐gG"? ֐gGB? ֐gGb? ֐gG? ֐gG? ֐gG? ֐gG? ְg@ ְg@" ְg @B ְg@b ְg@ ְg@ ְg@ ְg@ ְg"@ ְg&@" ְg*@B ְg.@b ְg2@ ְg6@ ְg:@ ְg>@ ְgB@ ְgF@" ְgJ@B ְgN@b ְgR@ ְgV@ ְgZ@ ְg^@ ְgb@ ְgf@" ְgj@B ְgn@b ְgr@ ְgv@ ְgz@ ְg~@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְg@ ְg@" ְg@B ְg@b ְg@ ְg@ ְg@ ְg@ ְgA ְgA" ְg AB ְgAb ְgA ְgA ְgA ְgA ְg"A ְg&A" ְg*AB ְg.Ab ְg2A ְg6A ְg:A ְg>A ְgBA ְgFA" ְgJAB ְgNAb ְgRA ְgVA ְgZA ְg^A ְgbA ְgfA" ְgjAB ְgnAb ְgrA ְgvA ְgzA ְg~A ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ְgA ְgA" ְgAB ְgAb ְgA ְgA ְgA ְgA ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gB ֐gB" ֐g BB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐g"B ֐g&B" ֐g*BB ֐g.Bb ֐g2B ֐g6B ֐g:B ֐g>B ֐gBB ֐gFB" ֐gJBB ֐gNBb ֐gRB ֐gVB ֐gZB ֐g^B ֐gbB ֐gfB" ֐gjBB ֐gnBb ֐grB ֐gvB ֐gzB ֐g~B ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gC ֐gC" ֐g CB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐g"C ֐g&C" ֐g*CB ֐g.Cb ֐g2C ֐g6C ֐g:C ֐g>C ֐gBC ֐gFC" ֐gJCB ֐gNCb ֐gRC ֐gVC ֐gZC ֐g^C ֐gbC ֐gfC" ֐gjCB ֐gnCb ֐grC ֐gvC ֐gzC ֐g~C ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gD ֐gD" ֐g DB ֐gDb ֐gD ֐gD ֐gD ֐gD ֐g"D! ֐g&D"! ֐g*DB! ֐g.Db! ֐g2D! ֐g6D! ֐g:D! ֐g>D! ֐gBD" ֐gFD"" ֐gJDB" ֐gNDb" ֐gRD" ֐gVD" ֐gZD" ֐g^D" ֐gbD# ֐gfD"# ֐gjDB# ֐gnDb# ֐grD# ֐gvD# ֐gzD# ֐g~D# ֐gD$ ֐gD"$ ֐gDB$ ֐gDb$ ֐gD$ ֐gD$ ֐gD$ ֐gD$ ֐gD% ֐gD"% ֐gDB% ֐gDb% ֐gD% ֐gD% ֐gD% ֐gD% ֐gD& ֐gD"& ֐gDB& ֐gDb& ֐gD& ֐gD& ֐gD& ֐gD& ֐gD' ֐gD"' ֐gDB' ֐gDb' ֐gD' ֐gD' ֐gD' ֐gD' ֐gE( ֐gE"( ֐g EB( ֐gEb( ֐gE( ֐gE( ֐gE( ֐gE( ֐g"E) ֐g&E") ֐g*EB) ֐g.Eb) ֐g2E) ֐g6E) ֐g:E) ֐g>E) ֐gBE* ֐gFE"* ֐gJEB* ֐gNEb* ֐gRE* ֐gVE* ֐gZE* ֐g^E* ֐gbE+ ֐gfE"+ ֐gjEB+ ֐gnEb+ ֐grE+ ֐gvE+ ֐gzE+ ֐g~E+ ֐gE, ֐gE", ֐gEB, ֐gEb, ֐gE, ֐gE, ֐gE, ֐gE, ֐gE- ֐gE"- ֐gEB- ֐gEb- ֐gE- ֐gE- ֐gE- ֐gE- ֐gE. ֐gE". ֐gEB. ֐gEb. ֐gE. ֐gE. ֐gE. ֐gE. ֐gE/ ֐gE"/ ֐gEB/ ֐gEb/ ֐gE/ ֐gE/ ֐gE/ ֐gE/ ֐gF0 ֐gF"0 ֐g FB0 ֐gFb0 ֐gF0 ֐gF0 ֐gF0 ֐gF0 ֐g"F1 ֐g&F"1 ֐g*FB1 ֐g.Fb1 ֐g2F1 ֐g6F1 ֐g:F1 ֐g>F1 ֐gBF2 ֐gFF"2 ֐gJFB2 ֐gNFb2 ֐gRF2 ֐gVF2 ֐gZF2 ֐g^F2 ֐gbF3 ֐gfF"3 ֐gjFB3 ֐gnFb3 ֐grF3 ֐gvF3 ֐gzF3 ֐g~F3 ֐gF4 ֐gF"4 ֐gFB4 ֐gFb4 ֐gF4 ֐gF4 ֐gF4 ֐gF4 ֐gF5 ֐gF"5 ֐gFB5 ֐gFb5 ֐gF5 ֐gF5 ֐gF5 ֐gF5 ֐gF6 ֐gF"6 ֐gFB6 ֐gFb6 ֐gF6 ֐gF6 ֐gF6 ֐gF6 ֐gF7 ֐gF"7 ֐gFB7 ֐gFb7 ֐gF7 ֐gF7 ֐gF7 ֐gF7 ֐gG8 ֐gG"8 ֐g GB8 ֐gGb8 ֐gG8 ֐gG8 ֐gG8 ֐gG8 ֐g"G9 ֐g&G"9 ֐g*GB9 ֐g.Gb9 ֐g2G9 ֐g6G9 ֐g:G9 ֐g>G9 ֐gBG: ֐gFG": ֐gJGB: ֐gNGb: ֐gRG: ֐gVG: ֐gZG: ֐g^G: ֐gbG; ֐gfG"; ֐gjGB; ֐gnGb; ֐grG; ֐gvG; ֐gzG; ֐g~G; ֐gG< ֐gG"< ֐gGB< ֐gGb< ֐gG< ֐gG< ֐gG< ֐gG< ֐gG= ֐gG"= ֐gGB= ֐gGb= ֐gG= ֐gG= ֐gG= ֐gG= ֐gG> ֐gG"> ֐gGB> ֐gGb> ֐gG> ֐gG> ֐gG> ֐gG> ֐gG? ֐gG"? ֐gGB? ֐gGb? ֐gG? ֐gG? ֐gG? ֐gG? ֐g@ ֐g@" ֐g @B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐g"@ ֐g&@" ֐g*@B ֐g.@b ֐g2@ ֐g6@ ֐g:@ ֐g>@ ֐gB@ ֐gF@" ֐gJ@B ֐gN@b ֐gR@ ֐gV@ ֐gZ@ ֐g^@ ֐gb@ ֐gf@" ֐gj@B ֐gn@b ֐gr@ ֐gv@ ֐gz@ ֐g~@ ֐g@ ֐g@" ֐g@B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐g@ ֐g@" ֐g@B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐g@ ֐g@" ֐g@B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐g@ ֐g@" ֐g@B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐gA ֐gA" ֐g AB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐g"A ֐g&A" ֐g*AB ֐g.Ab ֐g2A ֐g6A ֐g:A ֐g>A ֐gBA ֐gFA" ֐gJAB ֐gNAb ֐gRA ֐gVA ֐gZA ֐g^A ֐gbA ֐gfA" ֐gjAB ֐gnAb ֐grA ֐gvA ֐gzA ֐g~A ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gB ֐gB" ֐g BB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐g"B ֐g&B" ֐g*BB ֐g.Bb ֐g2B ֐g6B ֐g:B ֐g>B ֐gBB ֐gFB" ֐gJBB ֐gNBb ֐gRB ֐gVB ֐gZB ֐g^B ֐gbB ֐gfB" ֐gjBB ֐gnBb ֐grB ֐gvB ֐gzB ֐g~B ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gC ֐gC" ֐g CB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐g"C ֐g&C" ֐g*CB ֐g.Cb ֐g2C ֐g6C ֐g:C ֐g>C ֐gBC ֐gFC" ֐gJCB ֐gNCb ֐gRC ֐gVC ֐gZC ֐g^C ֐gbC ֐gfC" ֐gjCB ֐gnCb ֐grC ֐gvC ֐gzC ֐g~C ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gD ֐gD" ֐g DB ֐gDb ֐gD ֐gD ֐gD ֐gD ֐g"D! ֐g&D"! ֐g*DB! ֐g.Db! ֐g2D! ֐g6D! ֐g:D! ֐g>D! ֐gBD" ֐gFD"" ֐gJDB" ֐gNDb" ֐gRD" ֐gVD" ֐gZD" ֐g^D" ֐gbD# ֐gfD"# ֐gjDB# ֐gnDb# ֐grD# ֐gvD# ֐gzD# ֐g~D# ֐gD$ ֐gD"$ ֐gDB$ ֐gDb$ ֐gD$ ֐gD$ ֐gD$ ֐gD$ ֐gD% ֐gD"% ֐gDB% ֐gDb% ֐gD% ֐gD% ֐gD% ֐gD% ֐gD& ֐gD"& ֐gDB& ֐gDb& ֐gD& ֐gD& ֐gD& ֐gD& ֐gD' ֐gD"' ֐gDB' ֐gDb' ֐gD' ֐gD' ֐gD' ֐gD' ֐gE( ֐gE"( ֐g EB( ֐gEb( ֐gE( ֐gE( ֐gE( ֐gE( ֐g"E) ֐g&E") ֐g*EB) ֐g.Eb) ֐g2E) ֐g6E) ֐g:E) ֐g>E) ֐gBE* ֐gFE"* ֐gJEB* ֐gNEb* ֐gRE* ֐gVE* ֐gZE* ֐g^E* ֐gbE+ ֐gfE"+ ֐gjEB+ ֐gnEb+ ֐grE+ ֐gvE+ ֐gzE+ ֐g~E+ ֐gE, ֐gE", ֐gEB, ֐gEb, ֐gE, ֐gE, ֐gE, ֐gE, ֐gE- ֐gE"- ֐gEB- ֐gEb- ֐gE- ֐gE- ֐gE- ֐gE- ֐gE. ֐gE". ֐gEB. ֐gEb. ֐gE. ֐gE. ֐gE. ֐gE. ֐gE/ ֐gE"/ ֐gEB/ ֐gEb/ ֐gE/ ֐gE/ ֐gE/ ֐gE/ ֐gF0 ֐gF"0 ֐g FB0 ֐gFb0 ֐gF0 ֐gF0 ֐gF0 ֐gF0 ֐g"F1 ֐g&F"1 ֐g*FB1 ֐g.Fb1 ֐g2F1 ֐g6F1 ֐g:F1 ֐g>F1 ֐gBF2 ֐gFF"2 ֐gJFB2 ֐gNFb2 ֐gRF2 ֐gVF2 ֐gZF2 ֐g^F2 ֐gbF3 ֐gfF"3 ֐gjFB3 ֐gnFb3 ֐grF3 ֐gvF3 ֐gzF3 ֐g~F3 ֐gF4 ֐gF"4 ֐gFB4 ֐gFb4 ֐gF4 ֐gF4 ֐gF4 ֐gF4 ֐gF5 ֐gF"5 ֐gFB5 ֐gFb5 ֐gF5 ֐gF5 ֐gF5 ֐gF5 ֐gF6 ֐gF"6 ֐gFB6 ֐gFb6 ֐gF6 ֐gF6 ֐gF6 ֐gF6 ֐gF7 ֐gF"7 ֐gFB7 ֐gFb7 ֐gF7 ֐gF7 ֐gF7 ֐gF7 ֐gG8 ֐gG"8 ֐g GB8 ֐gGb8 ֐gG8 ֐gG8 ֐gG8 ֐gG8 ֐g"G9 ֐g&G"9 ֐g*GB9 ֐g.Gb9 ֐g2G9 ֐g6G9 ֐g:G9 ֐g>G9 ֐gBG: ֐gFG": ֐gJGB: ֐gNGb: ֐gRG: ֐gVG: ֐gZG: ֐g^G: ֐gbG; ֐gfG"; ֐gjGB; ֐gnGb; ֐grG; ֐gvG; ֐gzG; ֐g~G; ֐gG< ֐gG"< ֐gGB< ֐gGb< ֐gG< ֐gG< ֐gG< ֐gG< ֐gG= ֐gG"= ֐gGB= ֐gGb= ֐gG= ֐gG= ֐gG= ֐gG= ֐gG> ֐gG"> ֐gGB> ֐gGb> ֐gG> ֐gG> ֐gG> ֐gG> ֐gG? ֐gG"? ֐gGB? ֐gGb? ֐gG? ֐gG? ֐gG? ֐gG? ֐g@ ֐g@" ֐g @B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐g"@ ֐g&@" ֐g*@B ֐g.@b ֐g2@ ֐g6@ ֐g:@ ֐g>@ ֐gB@ ֐gF@" ֐gJ@B ֐gN@b ֐gR@ ֐gV@ ֐gZ@ ֐g^@ ֐gb@ ֐gf@" ֐gj@B ֐gn@b ֐gr@ ֐gv@ ֐gz@ ֐g~@ ֐g@ ֐g@" ֐g@B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐g@ ֐g@" ֐g@B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐g@ ֐g@" ֐g@B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐g@ ֐g@" ֐g@B ֐g@b ֐g@ ֐g@ ֐g@ ֐g@ ֐gA ֐gA" ֐g AB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐g"A ֐g&A" ֐g*AB ֐g.Ab ֐g2A ֐g6A ֐g:A ֐g>A ֐gBA ֐gFA" ֐gJAB ֐gNAb ֐gRA ֐gVA ֐gZA ֐g^A ֐gbA ֐gfA" ֐gjAB ֐gnAb ֐grA ֐gvA ֐gzA ֐g~A ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gA ֐gA" ֐gAB ֐gAb ֐gA ֐gA ֐gA ֐gA ֐gB ֐gB" ֐g BB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐g"B ֐g&B" ֐g*BB ֐g.Bb ֐g2B ֐g6B ֐g:B ֐g>B ֐gBB ֐gFB" ֐gJBB ֐gNBb ֐gRB ֐gVB ֐gZB ֐g^B ֐gbB ֐gfB" ֐gjBB ֐gnBb ֐grB ֐gvB ֐gzB ֐g~B ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gB ֐gB" ֐gBB ֐gBb ֐gB ֐gB ֐gB ֐gB ֐gC ֐gC" ֐g CB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐g"C ֐g&C" ֐g*CB ֐g.Cb ֐g2C ֐g6C ֐g:C ֐g>C ֐gBC ֐gFC" ֐gJCB ֐gNCb ֐gRC ֐gVC ֐gZC ֐g^C ֐gbC ֐gfC" ֐gjCB ֐gnCb ֐grC ֐gvC ֐gzC ֐g~C ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gC ֐gC" ֐gCB ֐gCb ֐gC ֐gC ֐gC ֐gC ֐gD ֐gD" ֐g DB ֐gDb ֐gD ֐gD ֐gD ֐gD ֐g"D! ֐g&D"! ֐g*DB! ֐g.Db! ֐g2D! ֐g6D! ֐g:D! ֐g>D! ֐gBD" ֐gFD"" ֐gJDB" ֐gNDb" ֐gRD" ֐gVD" ֐gZD" ֐g^D" ֐gbD# ֐gfD"# ֐gjDB# ֐gnDb# ֐grD# ֐gvD# ֐gzD# ֐g~D# ֐gD$ ֐gD"$ ֐gDB$ ֐gDb$ ֐gD$ ֐gD$ ֐gD$ ֐gD$ ֐gD% ֐gD"% ֐gDB% ֐gDb% ֐gD% ֐gD% ֐gD% ֐gD% ֐gD& ֐gD"& ֐gDB& ֐gDb& ֐gD& ֐gD& ֐gD& ֐gD& ֐gD' ֐gD"' ֐gDB' ֐gDb' ֐gD' ֐gD' ֐gD' ֐gD' ֐gE( ֐gE"( ֐g EB( ֐gEb( ֐gE( ֐gE( ֐gE( ֐gE( ֐g"E) ֐g&E") ֐g*EB) ֐g.Eb) ֐g2E) ֐g6E) ֐g:E) ֐g>E) ֐gBE* ֐gFE"* ֐gJEB* ֐gNEb* ֐gRE* ֐gVE* ֐gZE* ֐g^E* ֐gbE+ ֐gfE"+ ֐gjEB+ ֐gnEb+ ֐grE+ ֐gvE+ ֐gzE+ ֐g~E+ ֐gE, ֐gE", ֐gEB, ֐gEb, ֐gE, ֐gE, ֐gE, ֐gE, ֐gE- ֐gE"- ֐gEB- ֐gEb- ֐gE- ֐gE- ֐gE- ֐gE- ֐gE. ֐gE". ֐gEB. ֐gEb. ֐gE. ֐gE. ֐gE. ֐gE. ֐gE/ ֐gE"/ ֐gEB/ ֐gEb/ ֐gE/ ֐gE/ ֐gE/ ֐gE/ ֐gF0 ֐gF"0 ֐g FB0 ֐gFb0 ֐gF0 ֐gF0 ֐gF0 ֐gF0 ֐g"F1 ֐g&F"1 ֐g*FB1 ֐g.Fb1 ֐g2F1 ֐g6F1 ֐g:F1 ֐g>F1 ֐gBF2 ֐gFF"2 ֐gJFB2 ֐gNFb2 ֐gRF2 ֐gVF2 ֐gZF2 ֐g^F2 ֐gbF3 ֐gfF"3 ֐gjFB3 ֐gnFb3 ֐grF3 ֐gvF3 ֐gzF3 ֐g~F3 ֐gF4 ֐gF"4 ֐gFB4 ֐gFb4 ֐gF4 ֐gF4 ֐gF4 ֐gF4 ֐gF5 ֐gF"5 ֐gFB5 ֐gFb5 ֐gF5 ֐gF5 ֐gF5 ֐gF5 ֐gF6 ֐gF"6 ֐gFB6 ֐gFb6 ֐gF6 ֐gF6 ֐gF6 ֐gF6 ֐gF7 ֐gF"7 ֐gFB7 ֐gFb7 ֐gF7 ֐gF7 ֐gF7 ֐gF7 ֐gG8 ֐gG"8 ֐g GB8 ֐gGb8 ֐gG8 ֐gG8 ֐gG8 ֐gG8 ֐g"G9 ֐g&G"9 ֐g*GB9 ֐g.Gb9 ֐g2G9 ֐g6G9 ֐g:G9 ֐g>G9 ֐gBG: ֐gFG": ֐gJGB: ֐gNGb: ֐gRG: ֐gVG: ֐gZG: ֐g^G: ֐gbG; ֐gfG"; ֐gjGB; ֐gnGb; ֐grG; ֐gvG; ֐gzG; ֐g~G; ֐gG< ֐gG"< ֐gGB< ֐gGb< ֐gG< ֐gG< ֐gG< ֐gG< ֐gG= ֐gG"= ֐gGB= ֐gGb= ֐gG= ֐gG= ֐gG= ֐gG= ֐gG> ֐gG"> ֐gGB> ֐gGb> ֐gG> ֐gG> ֐gG> ֐gG> ֐gG? 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ù@痡3@a痡3@a 6'@!C`T {S6[ @caD"@7ҿE4 @@q Tq`TqT@@!#!@!@ ?@/@ @Lyu3@@ȸ6'@!C`T@ ո )5.*3@@sD7@`@ SA[B@{Ǩ_ִW8RS5 2*~ մW8RS5`0*? %@痡3@at痡3@am6'@!C`T  {S6[ @caD"@7!E4 @@Kq Tq`TqT@@!#!@!@ ?@/@ @Lt3@@*6Р'@!C`T@ ո )53r*3@@sD7@`@ SA[B@{Ǩ_ִW8RS5`7T*'~ մW8RS55B*? @g痡3@aַ|痡3@aϷ6Р'@!C`To {S6[ @caD"@7҃E4 @@q Tq`TqT@@!#!@!@ ?@j/@ @L=t3@@6Р'@!C`T@ ո )5 9Ԯ*3@r@sD7@`@ SA[B@{Ǩ_ִW8RS5<*9~ մW8RS5:*? @ɂ痡3@a8޳痡3@a16Р'@!C`Tѷ {S6 @aD[c"@GE6 @@qTq!T5B# R6Ry/9 ) )W*~+@@sDG@`@ @SA[B@{ɨ_@@!#!@!@ ?ր@/@C @Ls3@@ж6Р'@!C`T@ 5B`># R6Ry/9 ) )*@Y@9痡+@aM痡3@a6Р'@!C`T@ {S6[ @caD"@7UE5 @@q TLT54 qTW8RS5`"ȭ*g3@`f@sD7@`@ SA[B@{Ǩ_ֿq TqTW8RS5'*~3@@@@!#!@!@ ?@/@ @Lr3@@(6Р'@!C`Tȶ@ յW8RS5 $l*@ յW8RS5 Z*# յW8RS5%H*r痡3@a痡3@aڵ6Р'@!C`Tz{S6 @aD[c"@G~E6 @@qTq!T5B# R6Ry/9 ) )*t~+@@sDG@`@ @SA[B@{ɨ_@@!#!@!@ ?ր@V~/@C @L)r3@@x6Р'@!C`T@ 5B`># R6Ry/9 ) )*@@痡+@aO痡3@aH6Р'@!C`T {S6[ @caD"@7}E5 @@'qTTqTTq` Tqa TW8RS5 l*3@ @q` T Tu5W8RS5`?T*+3@ @sD7@`@ ʠSA[B@{Ǩ_ֵW8RS56* յW8RS5 $*} @5@!#!@!@ ?@}/@ @LYq3@@6Р'@!C`TH@ ո )5 *_ յW8RS5(ܫ* յW8RS5`ʫ*}v յW8RS5*;Bd痡3@aQ3@aE6'@!C`T {S6[ @caD"@7|E5 @@#qTTqTTq` Tqa TW8RS5 h*_3@ @q` T Tu5W8RS5 P*3@ @sD7@`@ ʠSA[B@{Ǩ_ֵW8RS5 2* յW8RS5` *m} @5@w!#!@!@ ?@|/@ @LUp3@@6'@!C`TD@ ո )5` * յW8RS5*ت*+ յW8RS5ƪ*q}v յW8RS5*Ad~痡3@aM3@aA6'@!C`T {S6[ @caD"@7{E5 @@q TTqT+Tq Tq TW8RS5 d**3@`@ տq TLT5W8RS5`?J**h3@@sD7@`@ SA[B@{Ǩ_ յW8RS5*** W8RS5 **}@@w!#!@!@ ?@z{/@ @LMo3@@6'@!C`T<@ ո )5 **W8RS5(Щ**jW8RS5`** }tW8RS5**vAb}痡3@aD3@a86'@!C`Tز{S6[ @caD"@7zE5 @@q TTqT+Tq Tq TW8RS5 \** 3@`@ տq TLT5W8RS5 B**3@߱@sD7@`@ SA[B@{Ǩ_ յW8RS5 "**W8RS5`**|@@w!#!@!@ ?@rz/@ @LEn3@@6'@!C`T4@ ո )5` ڨ**6W8RS5*Ȩ**ƟW8RS5**|tW8RS5**Ab|痡3@a<3@a06'@!C`Tб{S6[ @caD"@7yE5 @@q TTqT+Tq Tq TW8RS5`T**h3@`@ տq TLT5W8RS55:**3@װ@sD7@`@ SA[B@{Ǩ_ յW8RS5`9**TW8RS5>**@|@@w!#!@!@ ?@jy/@ @L=m3@@6'@!C`T,@ ո )57ҧ**W8RS5@%**"W8RS5<**X|tW8RS5 ;**@b{痡3@a4ڬ3@a(6'@!C`TȰ{S6[ @caD"@7xE4 @@qTMTqTq@ TqT@t@w!и#!@!@ ?@x/@ @Ll3@@6'@!C`!T@q TTT5W8RS5`&***3@ï@sD7@`@ ʠSA[B@{Ǩ_ մW8RS5**̠W8RS5**W8RS5 **{ )5 Ҧ**vW8RS5**p@W8RS5`**|@z痡3@aB6'@!C`T߯3@A. {S6[ @caD"@7wE5 @@q TLT54 qTW8RS5 ^*3@`@sD7@`@ SA[B@{Ǩ_ֿq TqTW8RS5`<*C|3@@@@w!и#!@!@ ?@w/@ @Lok3@@6'@!C`T^@ յW8RS5*U@ յW8RS5`* յW8RS5ޥ*Wz痡3@aw痡3@ap6'@!C`T{S6[ @caD"@7#wE5 @@Mq TLT54 qTW8RS5*3@`4@sD7@`@ SA[B@{Ǩ_ֿq TqTW8RS5 $t*|3@@@@w!и#!@!@ ?@v/@ @Lj3@@6'@!C`T@ յW8RS5 :*)@ յW8RS5 (*k յW8RS5`"*+@y痡3@aU痡3@a6'@!C`TH{S6[ @caD"@7[vE6 @@qTq!TW8RS5'ФR*|3@m@sD7@`@ SA[B@{Ǩ_ @@w!и#!@!@ ?֠@$v/@ @Li3@@F6'@!C`T@ նW8RS5%R*@ѭ@x6'@!C``Tĭ©痡3@3@{S6[ @caD"@7uE5 @@q` TTq@TqTW8RS5 +A*n@3@߬@sD7@`@ SA[B@{Ǩ_ տq TqTW8RS5`0*ϟ3@@@@w!и#!@!@ ?@~u/@ @LQi3@@6'@!C`T@@ յW8RS5,*{ ո )5`)ԣ* յW8RS5.£*Cyw痡3@a[痡3@aT6'@!C`T{S6[ @caD"@7uE5 @@1 qTMTqT+TqTW8RS5:x* |3@@ 4qT )53c*P3@@sD7@`@ ʀSA[B@{Ǩ_ յW8RS5 9D* @U@w!#!@!@ ?@t/@ @Lyh3@@ȫ6'@!C`Th@ յW8RS5 2 * յW8RS5`7*? յW8RS55*w痡3@a6'@!C``T!痡3@r {S6[ @caD"@7+tE5 @@Uq` TTq@TqTW8RS5`>*@3@;@sD7@`@ SA[B@{Ǩ_ տq TqTW8RS5z*s3@@@@w!#!@!@ ?@s/@ @Lg3@@6'@!C`T@ յW8RS5 @*u{ ո )5<0* յW8RS5*CxHv痡3@a]痡3@a6'@!C`TP{S6[ @caD"@7csE5 @@q TqTqT@@w!#!@!@ ?@Js/@ @Lg3@@l6'@!C`T@ յW8RS5`*{3@P@sD7@`@ SA[B@{Ǩ_ֵW8RS5* յW8RS5 *z Ǫ@u痡3@a痡3@a6'@!C`T {S6[ @caD"@7rE4 @@q Tq`TqT@@w!#!@!@ ?@r/@ @L}f3@@̩6'@!C`T@ ո )5 *I3@@sD7@`@ SA[B@{Ǩ_ִW8RS5*s{ մW8RS5*> )@ u痡3@ax痡3@aq6'@!C`T {S6[ @caD"@7%rE4 @@Oq Tq`TqT@@w!#!@!@ ?@ r/@ @Le3@@.6'@!C`T@ ո )5`!v*O3@@sD7@`@ SA[B@{Ǩ_ִW8RS5$X*y{ մW8RS5 #F*? @kt痡3@aڨ痡3@aӨ6'@!C`Ts {S6[ @caD"@7҇qE6 @@q`TqT{3@@sD7@`@ SA[B@{Ǩ_ @@w!C!@!@ ?֠@\q/@ @/e3@@~6+@!C`T@ ̟/? @s痡3@aa痡3@aZ6Р+@!C`T {S6[ @caD"@7qE5 @@9q TTqT+Tq Tq TW8RS5`/~R*63@`@ տq TLT5W8RS5&dR*3@@sD7@`@ SA[B@{Ǩ_ յW8RS5 *DR*W8RS582R*g@@w!#!@!@ ?@p/@ @Lgd3@@6Р'@!C`TV@ ո )5`(R*xW8RS5@6R*,W8RS5-؞R*D{tW8RS5+ƞR*>br痡3@a^3@aR6Р'@!C`T{S6[ @caD"@7pE5 @@1q TTqT+Tq Tq TW8RS5`/v**.3@`@ տq TLT5W8RS5&\**3@@sD7@`@ SA[B@{Ǩ_ յW8RS5 *<**W8RS58***f@@w!#!@!@ ?@o/@ @L_c3@@6Р'@!C`TN@ ո )5`(**pW8RS5@6**$W8RS5-Н** յW8RS54* q痡3@ay6Р'@!C``T痡3@j {S6[ @caD"@7#nE5 @@M qTMTqT+TqTW8RS5*{3@@ 4qT )5;*T3@@sD7@`@ ʀSA[B@{Ǩ_ յW8RS5`* @U@w!#!@!@ ?@m/@ @La3@@6Р'@!C`T@ յW8RS59(* յW8RS5 ?*> յW8RS5`=*i.p痡3@a6Р'@!C``T=;痡3@ {S6[ @caD"@7GmE5 @@q qTMTqT+TqTW8RS5 *z3@@ 4qT )5 *83@A@sD7@`@ ʀSA[B@{Ǩ_ յW8RS5` * @U@W!#!@!@ ?@l/@ @L`3@@6'@!C`T@ յW8RS5`L*} յW8RS5 :*> յW8RS5(*KRo痡3@a6'@!C``Ta_痡3@ {S6[ @aD"@?klF5 @@q TMTqT+Tq Tq T5B g8Rc5 'WS՚*#;@ @q T T5 5g8Rc5`?*;@ Z@sD?@`@ `SA[B@{Ȩ_ֵg8Rc5* յ5B g8Rc5`'WS*#v @u@W!c!@!@ ?@k7@ @_;@@ 6/@!C`@T@ ո )5 P* յg8Rc5(>* յg8Rc5`,*%zp յg8Rc5*=^Dn痡;@aY;@a6/@!C`TG {S6[ @aD"@?[kF5 @@q TMTqT+Tq Tq T5B g8Rc5'WSř*#;@ @q T T5 5g8Rc5 *;@ J@sD?@`@ `SA[B@{Ȩ_ֵg8Rc5 *k յ5B`g8Rc5'WSw*#v @u@W!c!@!@ ?@j7@ @^;@@6/@!C`@T@ ո )5` @* յg8Rc5*.* յg8Rc5*zp յg8Rc5 *=^4m痡;@aI;@a6/@!C`T7 {S6[ @caD"@GKjE4@@uq )TTq&TTq`TT5B # R8Ry/9 ) )*4.qTT&q TT5B"# R8Ry/9 ) )*| ոq TT5B# R8Ry/9 ) )*x+@!@sDG@`@ %SA[B@{ɨ_ ՟6q TT:q T5B@# R8Ry/9 ) )\*~ բ5B# R/y9 ) )H*+@5B# R8Ry/9 ) )1*25B# R8Ry/9 ) )*5B# R8Ry/9 ) ) *{@t@5B@# R8Ry/9 ) )*n5B# R8Ry/9 ) )ݗ*Z=Z5B # R8Ry/9 ) )ɗ*R>F5B# R8Ry/9 ) )*v@25B@ # R8Ry/9 ) )*|5B# Ry/8R9g )c*|y5B# Ry/8R9g )cu*?@#W!!@!@ ?֠@h/@C@L\3@@6'@!C` T@}k痡+@a6'@!C`T3@ԟ+@A {6SBD R[@C@cks3y9 #dq@9xhH!D@9c9@@CphI!@@DR#RC ^g@@𗢣7R#RYg@@}M@_T6?:DRҠ;`#_"Q5?qTg@[ D@`#_"Q5?q`Tk@TMu˿" T#hc@@!@w hoJ@` @Qa qATa@!@ ?`@Qaq!Ta@! @ ?` @Qa qATa@!@ ?`@Qaq!Ta@! @ ?k@T?@gK7@w @𗻋Nk@BBBT;@c| `{7uM@˿#TgL"R"9@S7@#RRg@@w@@~痠k@@~6D@@ @SA[BcCkDsE{Ԩ_ a@!@ ?a3 _Q"c4a@!@ ?a3 _Q"4|w@@~痠k@@~d痡g@?j {6[BD RS@C@cks3y9 #pcq@C9bgI!D@9c9@@ZgJ!@@ٕDR#RCtg@@v𗢣7ʕR#RXg@@g@?cM?T6c3ZDRҠ?@gK~bFc@7"Úxb!z _CQ5_q@ Tk@NBBB_ T hs?@uj3@fL"R"9@.k@o@˟ T~7@#RRg@@w@@%~痠k@@"~6D@@ SA[BcCkDsE{Ԩ_ @Q"q!T"@;B@@?֡;@ @Q" qT"@A @ ?ֱ "@;B@@?֡;@"0@_QC4{w@@}痠k@@}痡g@՝^i{6[BD RS@C@cksyS9  bq@C9fH!D@9#9@@CzfI!@@DR#RW_@@c7R#Rs_@@L? T6#{DR9Ҡ?@6fJ~bFw@7#ךxb![ _CQ5_q Tc@M BBB_ T?@s@j3fK"R"9@Sc@g@˟ CT7@#RR_@@Ao@@J}痠c@@G}6D@@ SA[BcCkDsE{Ө_  @Q"qAT"@;B@@?֡;@ @Q" qT"@A @ ?ֲ "@;B@@?֡;@"0@_QC4zo@@}痠c@@ }痡_@h{6[BD R?@C@Scksy9   {)aq@9eH!D@99@ϜR#?@DR#RWW@@#7?@R#RW@@K?T6C|DR%  _CQ5_q@ TW@A`D _CQ5_q` T[@&sL*B?T`H38K˿ B T@QeS@@3@~KeI@s  @Q"qAT"@;B@@?֡;@ @Q" qT"@A @ ? @Q"qT"@;B@@?֡;@ @Q" qT"@A @ ?ָ "@;B@@?֡;@"0@_QC4"@;B@@?֡;@"0@_QC4@dJ"R"9@)7@$R?@RW@@g@@&|痠[@@#|痠6D@@ ʀSA[BcCkDsE{Ҩ_֠yg@@|痠[@@ |痡W@g {S6[ @caD"@7ҵdE5@@ߛVq TTfq@ T(T^qTH T-VFq TTNq@T T ˴  տnqTC TrqT3@@sD7@`@ SA[B@{Ǩ_o  S  տ>q`TBq!Tܒ Ԓ ̒3 Ē M   @5@W!C!@!@ ?@d/@@W3@@26+@!C`aT@xЛ@tf痡3@a6+@!C``T痡3@a{[6ScDcC@Ң3ks;G>RCR@@ۚG@1;@DR#RCU@@ΚG@$;@R#RU@@@ R9cy_ccI!D@9c9@@cJ!@_@@xcK!@9@@#pcL!X@9@Q?`T6?`DcҠCm#_"Q5?qT{@X`D#_"Q5?qT@4cw@`TFӢ{@8xa#ÚB`D@ _#Q5?q`T QBBBXTR BBB_ITOdU!kBBAB|?BTRaht@?@~G@`|S痡+@a3@ {S6[ @caD"@GG_E4 @@qq T T q@Tq T5B R# ) R/y9 )v<+@@UsDG@`@ SA[B@{ɨ_5B` R# ) R/y9 ) Ք55B> R# ) R/y9 )@@W!#!@!@ ?֠@^/@C @LR3@@6Р'@!C`T@ 5B # R/y )9 )L(@sa6Р'@!C``T痡+@a֕3@Е {S6[ @caD"@Gҍ^E4 @@q T T q@Tq T5B R# ) R/y9 )x=+@@sDG@`@ SA[B@{ɨ_5B` R# ) R/y9 )݌ Ք55B R# ) R/y9 )Ȍ&@@W!#!@!@ ?֠@,^/@C @LQ3@@N6Р'@!C`T@ 5B # R/y )9 )ٕ@`6Р'@!C``T̕ʑ痡+@a3@ {S6[ @caD"@G]E4 @@q T T q@Tq T5B* R# ) R/y9 )B6+@@sDG@`@ SA[B@{ɨ_5B`( R# ) R/y9 )# Ք55B# R# ) R/y9 ){@@W!#!@!@ ?֠@r]/@C @LEQ3@@6Р'@!C`T@ 5B &# R/y )9 )؋:@_6Р'@!C``T痡+@ab3@\ {S6[ @caD"@G]E4 @@Cq T T q@Tq T5B3 R# ) R/y9 )6+@@'sDG@`@ SA[B@{ɨ_5B`1 R# ) R/y9 )i Ք55B, R# ) R/y9 )TB|@@7!#!@!@ ?֠@\/@C @LP3@@ړ6'@!C`T@ 5B /# R/y )9 )e@E_6'@!C``TXV痡+@a3@ {S6[ @caD"@G_\3@@@Y\E5 @@6qTTBq TTJq TTNqTC R )5@ Ɋa3@@hsDG@`@ SA[B@{ɨ_ տ*qTLT"qT&qA T5B? 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                                                                           վ  ռ  պ  ո  ն  մ  ղ  հ  ծ  լ  ժ  ը  զ  դ  բ  ՠ  ՞  ՜  ՚  ՘  Ֆ  Ք  Ւ  Ր  Վ  Ռ  Պ  Ո  Ն  Մ  Ղ  Հ  ~  |  z  x  v  t  r  p  n  l  j  h  f  d  b  `  ^  \  Z  X  V  T  R  P  N  L  J  H  F  D  B  @  >  <  :  8  6  4  2  0  .  ,  *  (  &  $  "                                                                                                    վ  ռ  պ  ո  ն  մ  ղ  հ  ծ  լ  ժ  ը  զ  դ  բ  ՠ  ՞  ՜  ՚  ՘  Ֆ  Ք  Ւ  Ր  Վ  Ռ  Պ  Ո  Ն  Մ  Ղ  Հ  ~  |  z  x  v  t  r  p  n  l  j  h  f  d  b  `  ^  \  Z  X  V  T  R  P  N  L  J  H  F  D  B  @  >  <  :  8  6  4  2  0  .  ,  *  (  &  $  "                                                                                                    վ  ռ  պ  ո  ն  մ  ղ  հ  ծ  լ  ժ  ը  զ  դ  բ  ՠ  ՞  ՜  ՚  ՘  Ֆ  Ք  Ւ  Ր  Վ  Ռ  Պ  Ո  Ն  Մ  Ղ  Հ  ~  |  z  x  v  t  r  p  n  l  j  h  f  d  b  `  ^  \  Z  X  V  T  R  P  N  L  J  H  F  D  B  @  >  <  :  8  6  4  2  0  .  ,  *  (  &  $  "                                                                    վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                                                     վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                                                     վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                                                     վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                                                     վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                                                     վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                                                     վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                                                     վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                                                     վ ռ պ ո ն մ ղ հ ծ լ ժ ը զ դ բ ՠ ՞ ՜ ՚ ՘ Ֆ Ք Ւ Ր Վ Ռ Պ Ո Ն Մ Ղ Հ ~ | z x v t r p n l j h f d b ` ^ \ Z X V T R P N L J H F D B @ > < : 8 6 4 2 0 . , * ( & $ "                    ՠ#@@ T#@ TT @!R@9@@ޗ@@##@@ޗ@#@@c@A@!@@@ ˠTcT`T ޗޗ7#@7@@ޗ@@Dq@T@R@%ޗ8ޗًޗ3@ @ @ TT@ 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R9@@@ݗ{Ĩ_{ #D@/Ҡ@ޗ ޗ#!D/@!@A?@TWݗ @{ƨ_{ #D@Ҡ#@ݗ#!ݗ#@ݗ#ݗ#@ݗ#ݗbݗ#!D@!@A?@T%ݗ @{Ѩ_{@@ B@T@~@@ݗ@~ӡ@ {Ĩ_{@@ B@T@~ˡ@#@~@ݗ@~ˡ@ {Ĩ_{ @Eݗ @{è_{ @9ݗ @{è_{ #D@Wҿ9#@%ݗ@"ݗ#@ݗ##ݗ#!DW@!@A?@Tݗ @{˨_{S@@ޗ''@MT@> ޗݗ@: ޗ`@ @5ݗ@3ݗ'@Ѡ'@ݗSA{Ũ_C@C_@@T@A@@_  _{S['#RW@RW@ KA RW@@K (/'@ݗ Qޗ'@ݗ ޗ`ݗ@'@ݗ ޗWݗ@`RW@ KA RW@@K (ݗ#@aҠ'@/@SA[B{ƨ_{S['#RW@RW@ KA RW@@K (/'@ݗ  ޗ'@ݗ  ޗݗ@'@ݗ ~ޗݗ@`RW@ KA RW@@K (dݗ#@aҠ'@w/@SA[B{ƨ_{RR@ݗ{¨_{RR@ݗ{¨_{RR@ݗ{¨_C@@@!$@@  C_C@}@ C_  @T@ @@x! _@@T@A@@_  _{S'#RW@RW@ KA RW@@K (/'@ݗ pޗ'@ݗ " ޗݗ@ݗ`RW@ KA RW@@K (ݗ#@aҠ'@/@SA@{ƨ_{S'#RW@RW@ KA RW@@K (/'@ݗ 3ޗ'@ݗ  ޗBݗ@ݗ`RW@ KA RW@@K (ݗ#@aҠ'@/@SA@{ƨ_C@@TC_@@T@A@@_  _{S['#RW@RW@ KA RW@@K (/W@q@T?ݗޗ#C% ޗ'@Oݗ ޗMݗ*'@Fݗ s ޗݗ@ |@)ݗ#@aҠ'@/@SA[B{ƨ_{S['#RW@RW@ KA RW@@K (/W@q@Tݗޗ#Cޗ'@ݗ {ޗݗ*'@ݗ * ޗݗ@ |@ݗ#@aҠ'@m/@SA[B{ƨ_@@T@A@@_  _{S['#RW@RW@ KA RW@@K (/W@q@Tҕݗmޗ#C{ޗ'@ݗ ޗ'@ݗ  ޗ)ݗ@*'@ݗ ޗݗ@ |@xݗ#@aҠ'@/@SA[B{ƨ_{S['#RW@RW@ KA RW@@K (/W@q@TEݗޗ#C+ޗ'@Uݗ ޗ'@Oݗ | ޗݗ@*'@Eݗ :ޗݗ@ |@(ݗ#@aҠ'@_/@SA[B{ƨ_@@T@A@@_  _{ @@@ݗ @@ޗݗ@@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K 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Cyޗݗ@cC|(ݗ/@+@7@SA[BcC{Ǩ_{S@@Tݗ@ݗ#\Gޗ@@ޗ''@@@ݗ'@GT Tޗxݗ/ݗ/@/@@@@ ?Bݗ#Fޗbݗ+ݗ+@+@@@@ ?( ޗ# Aޗݗݗ]ޗݗݗTޗSA{ƨ_{S@@Tҙݗ@]ݗ#\Gޗ@@ޗ''@@@lݗ'@GT T&ޗ ݗ/uݗ/@/@@@@ ?ݗ#FTޗݗ+_ݗ+@+@@@@ ?ޗ# A>ޗCݗ7ݗޗ:ݗ.ݗޗSA{ƨ_@@T@A@@_  _{S''@@@@3ݗ @@'ݗݗ@`SA{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ#Cޗ/@ݗ Clݗ/@ݗ/@ݗ Cޗxݗ@cC|@ݗ/@+@7@SA[BcC{Ǩ_{S''@@@@ݗ @@ݗMݗ@`SA{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTxݗPݗ#C^ޗ/@ݗ Cݗ/@nݗ/@ݗ Cޗ ݗ@cC}|@Zݗ/@+@"7@SA[BcC{Ǩ_{S@@T7ݗ@ݗ#\Gޗ@@rݗOO@*@@ݗO@GT Tޗݗ/ݗ/@/@@@@ ?tݗ#Fޗݗ+ݗ+@+@@@@ ?Zޗ# AޗݗݗޗݗݗޗSA{ƨ_{S@@Tݗ@ݗ#\Gޗ@@ݗOO@ *@@ݗO@GT TXޗ>ݗ/ҧݗ/@/@@@@ ?ݗ#Fޗ(ݗ+ґݗ+@+@@@@ ?ޗ# Apޗuݗiݗ#ޗlݗ`ݗޗSA{ƨ_@@T@A@@_  _{ #D@Ҡ@@@aݗ @@Uݗݗ@eݗ@#!D@!@A?@Tݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qT ݗݗ#Cݗg@q@Tݗݗ#Cݗ/@ݗ C{ݗ/@ݗ/@ݗ C*ޗݗ@cCݗ/@+@o7@SA[BcC{Ǩ_{ #D@Ҡ@@@ݗ @@ݗYݗ@ݗ@#!D@!@A?@T/ݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTxݗPݗ#C^ݗg@q@Teݗ=ݗ#CKݗ/@uݗ Cݗ/@[ݗ/@lݗ Cޗݗ@cC|Hݗ/@+@7@SA[BcC{Ǩ_{S@@T%ݗ@ݗ#\G ݗ@@ޗ''@@@ݗ'@GT Tޗݗ/ݗ/@/@@@@ ?bݗ#Fݗݗ+ݗ+@+@@@@ ?Hޗ# Aݗݗݗ}ޗݗݗtޗSA{ƨ_{S@@Tҹݗ@}ݗ#\Gݗ@@4ޗ''@@@ݗ'@GT TFޗ,ݗ/ҕݗ/@/@@@@ ?ݗ#Ftݗݗ+ݗ+@+@@@@ ?ޗ# A^ݗcݗWݗޗZݗNݗޗSA{ƨ_C@@@@?jT@@C_@@T@A@@_  _{ '#D@Ҡ@@@Aݗ @@5ݗݗ@7ݗ@#!D@!@A?@Tݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ#Cݗ/@ݗ Cnݗ/@ݗ/@ݗ Cޗzݗ@cC|@ݗ/@+@7@SA[BcC{Ǩ_{ '#D@Ҡ@@@ݗ @@ݗKݗ@7Jݗ@#!D@!@A?@T!ݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!R ݗR@qTjݗBݗ#CPݗ/@zݗ Cݗ/@`ݗ/@qݗ Cޗݗ@cC}|@Lݗ/@+@7@SA[BcC{Ǩ_{S@@T)ݗ@ݗ#\Gݗ@@dݗOO@*@@ݗO@GT Tݗݗ/ݗ/@/@@@@ ?fݗ#Fݗݗ+ݗ+@+@@@@ ?Lޗ# AݗݗݗݗݗݗxݗSA{ƨ_{S@@Tҽݗ@ݗ#\Gݗ@@ݗOO@*@@ݗO@GT TJݗ0ݗ/ҙݗ/@/@@@@ ?ݗ#Fxݗݗ+҃ݗ+@+@@@@ ?ޗ# Abݗgݗ[ݗݗ^ݗRݗ ݗSA{ƨ_C@@@@?kjT@@C_@@T@A@@_  _{ @@@Jݗ @@>ݗݗݗ@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ#Cݗg@q@Tݗݗ#Cݗ/@ݗ Cnݗ/@ݗ/@ݗ Cݗzݗ@cCݗ/@+@~7@SA[BcC{Ǩ_{ @@@ݗ @@ݗQݗ"ݗ@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTzݗRݗ#C`ݗg@q@Tgݗ?ݗ#CMݗ/@wݗ Cݗ/@]ݗ/@nݗ Cݗݗ@cC|Jݗ/@+@7@SA[BcC{Ǩ_{S@@T'ݗ@ݗ#\G ݗ@@ݗ''@@@ݗ'@GT Tݗݗ/ݗ/@/@@@@ ?dݗ#Fݗݗ+ݗ+@+@@@@ ?Jޗ# AݗݗݗݗݗݗvݗSA{ƨ_{S@@Tһݗ@ݗ#\Gݗ@@6ݗ''@@@ݗ'@GT THݗ.ݗ/җݗ/@/@@@@ ?ݗ#Fvݗݗ+ҁݗ+@+@@@@ ?ޗ# A`ݗeݗYݗݗ\ݗPݗ ݗSA{ƨ_@@T@A@@_  _{ '#D@Ҡ@@@Qݗ @@Eݗݗ@7ݗ@#!D@!@A?@Tݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ#Cݗ/@ ݗ C~ݗ/@ݗ/@ݗ C-ݗݗ@cC|@ݗ/@+@7@SA[BcC{Ǩ_{ '#D@Ҡ@@@ݗ @@ݗ[ݗ@7^ݗ@#!D@!@A?@T1ݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTzݗRݗ#C`ݗ/@ݗ Cݗ/@pݗ/@ݗ Cݗ ݗ@cC}|@\ݗ/@+@7@SA[BcC{Ǩ_{S@@T9ݗ@ݗ#\Gݗ@@tݗOO@*@@ݗO@GT Tݗݗ/ݗ/@/@@@@ ?vݗ#Fݗݗ+ݗ+@+@@@@ ?\ݗ# AݗݗݗݗݗݗݗSA{ƨ_{S@@Tݗ@ݗ#\Gݗ@@ݗOO@*@@ݗO@GT TZݗ@ݗ/ҩݗ/@/@@@@ ? ݗ#Fݗ*ݗ+ғݗ+@+@@@@ ?ݗ# Arݗwݗkݗ%ݗnݗbݗݗSA{ƨ_C@@@@?kbT@@C_@@T@A@@_  _{ #D@Ҡ@@@Uݗ @@Iݗݗ@ݗ@#!D@!@A?@Tݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ#Cݗg@q@Tݗݗ#Cݗ/@ݗ Coݗ/@ݗ/@ݗ Cݗ{ݗ@cCݗ/@+@o7@SA[BcC{Ǩ_{ #D@Ҡ@@@ݗ @@ݗMݗ@tݗ@#!D@!@A?@T#ݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!R ݗR@qTlݗDݗ#CRݗg@q@TYݗ1ݗ`#C?ݗ/@iݗ Cݗ/@Oݗ/@`ݗ Cݗݗ@cC|<ݗ/@+@7@SA[BcC{Ǩ_{S@@Tݗ@ݗ#\Gݗ@@ݗ''@@@ݗ'@GT Tݗݗ/ݗ/@/@@@@ ?Vݗ#Fݗvݗ+ݗ+@+@@@@ ?<ݗ# AݗݗݗqݗݗݗhݗSA{ƨ_{S@@Tҭݗ@qݗ#\Gݗ@@(ݗ''@@@ݗ'@GT T:ݗ ݗ/҉ݗ/@/@@@@ ?ݗ#Fhݗ ݗ+sݗ+@+@@@@ ?ݗ# ARݗWݗKݗݗNݗBݗݗSA{ƨ_@@T@A@@_  _{ '`#D@Ҡ@@@Cݗ @@7ݗݗ@7ݗ@a#!D@!@A?@Tݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ`#Cݗ/@ݗ Cpݗ/@ݗ/@ݗ Cݗ|ݗ@cC|@ݗ/@+@7@SA[BcC{Ǩ_{ '`#D@Ҡ@@@ݗ @@ݗMݗ@7ݗ@a#!D@!@A?@T#ݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!R ݗR@qTlݗDݗ`#CRݗ/@|ݗ Cݗ/@bݗ/@sݗ Cݗݗ@cC}|@Nݗ/@+@7@SA[BcC{Ǩ_{S@@T+ݗ@ݗ#\Gݗ@@fݗOO@*@@ ݗO@GT Tݗݗ/ݗ/@/@@@@ ?hݗ#Fݗݗ+ݗ+@+@@@@ ?Nݗ# AݗݗݗݗݗݗzݗSA{ƨ_{S@@Tҿݗ@ݗ#\Gݗ@@ݗOO@*@@ݗO@GT TLݗ2ݗ/қݗ/@/@@@@ ?ݗ#Fzݗݗ+҅ݗ+@+@@@@ ?ݗ# Adݗiݗ]ݗݗ`ݗTݗݗSA{ƨ_C@@@@?kjT@@C_@@T@A@@_  _{ @@@Lݗ @@@ݗݗݗ@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ`#Cݗg@q@Tݗݗ`#Cݗ/@ݗ Cpݗ/@ݗ/@ݗ Cݗ|ݗ@cCݗ/@+@~7@SA[BcC{Ǩ_{ @@@ݗ @@ݗSݗ<ݗ@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qT|ݗTݗ`#Cbݗg@q@TiݗAݗ`#COݗ/@yݗ Cݗ/@_ݗ/@pݗ Cݗݗ@cC|Lݗ/@+@7@SA[BcC{Ǩ_{S@@T)ݗ@ݗ`#\Gݗ@@ݗ''@@@ݗ'@GT Tݗݗ/ݗ/@/@@@@ ?fݗ`#Fݗݗ+ݗ+@+@@@@ ?Lݗ`# AݗݗݗݗݗݗxݗSA{ƨ_{S@@Tҽݗ@ݗ`#\Gݗ@@8ݗ''@@@ݗ'@GT TJݗ0ݗ/ҙݗ/@/@@@@ ?ݗ`#Fxݗݗ+҃ݗ+@+@@@@ ?ݗ`# Abݗgݗ[ݗݗ^ݗRݗ ݗSA{ƨ_@@T@A@@_  _{ '`#D@Ҡ@@@Sݗ @@Gݗݗ@7?ݗ@a#!D@!@A?@Tݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ`#Cݗ/@ ݗ Cݗ/@ݗ/@ݗ C/ݗݗ@cC|@ݗ/@+@7@SA[BcC{Ǩ_{ '`#D@Ҡ@@@ݗ @@ݗ]ݗ@7ݗ@a#!D@!@A?@T3ݗ @{Ĩ_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qT|ݗTݗ`#Cbݗ/@ݗ Cݗ/@rݗ/@ݗ Cݗ ݗ@cC}|@^ݗ/@+@7@SA[BcC{Ǩ_{S@@T;ݗ@ݗ`#\G!ݗ@@vݗOO@*@@ݗO@GT Tݗݗ/ݗ/@/@@@@ ?xݗ`#Fݗݗ+ݗ+@+@@@@ ?^ݗ`# AݗݗݗݗݗݗݗSA{ƨ_{S@@Tݗ@ݗ`#\Gݗ@@ ݗOO@*@@ݗO@GT T\ݗBݗ/ҫݗ/@/@@@@ ? ݗ`#Fݗ,ݗ+ҕݗ+@+@@@@ ?ݗ`# Atݗyݗmݗ'ݗpݗdݗݗSA{ƨ_C@@@@?kbT@@C_@@T@A@@_  _{ @@@\ݗ @@Pݗݗ@@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ`#Cݗg@q@Tݗݗ`#Cݗ/@ ݗ Cݗ/@ݗ/@ݗ C0ݗݗ@cCݗ/@+@7@SA[BcC{Ǩ_{ @@@ݗ @@ݗdݗ@@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!R-ݗR@qTҎݗfݗ`#Ctݗg@q@T{ݗSݗ`#Caݗ/@ݗ Cݗ/@qݗ/@ݗ Cݗ ݗ@cC|^ݗ/@+@7@SA[BcC{Ǩ_{S@@T;ݗ@ݗ`#\G!ݗ@@ݗ''@@@ݗ'@GT Tݗݗ/ݗ/@/@@@@ ?xݗ`#Fݗݗ+ݗ+@+@@@@ ?^ݗ`# AݗݗݗݗݗݗݗSA{ƨ_{S@@Tݗ@ݗ`#\Gݗ@@Jݗ''@@@ݗ'@GT T\ݗBݗ/ҫݗ/@/@@@@ ? ݗ`#Fݗ,ݗ+ҕݗ+@+@@@@ ?ݗ`# Atݗyݗmݗ'ݗpݗdݗݗSA{ƨ_@@T@A@@_  _{S''@@@@iݗ @@]ݗݗ@`SA{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ`#Cݗ/@-ݗ Cݗ/@ݗ/@$ݗ CQݗݗ@cC|@ݗ/@+@7@SA[BcC{Ǩ_{S''@@@@ݗ @@ݗݗ@`SA{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RMݗR@qTҮݗݗ`#Cݗ/@ݗ C3ݗ/@ݗ/@ݗ Cݗ?ݗ@cC}|@ݗ/@+@"7@SA[BcC{Ǩ_{S@@Tmݗ@1ݗ`#\GSݗ@@ݗOO@*@@LݗO@GT Tݗݗ/Iݗ/@/@@@@ ?ݗ`#F(ݗʿݗ+3ݗ+@+@@@@ ?ݗ`# Aݗݗ ݗݗݗݗݗSA{ƨ_{S@@Tݗ@ݗ`#\Gݗ@@<ݗOO@ *@@ݗO@GT Tݗtݗ/ݗ/@/@@@@ ?>ݗ`#Fݗ^ݗ+ݗ+@+@@@@ ?$ݗ`# AݗݗݗYݗݗݗPݗSA{ƨ_@@T@A@@_  _{ @@@ݗ @@ݗ%ݗ@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTQݗ)ݗ`#C7ݗg@q@T>ݗݗ`#C$ݗ/@Nݗ Cݗ/@4ݗ/@Eݗ Crݗϻݗ@cC!ݗ/@+@7@SA[BcC{Ǩ_{ @@@ݗ @@ݗݗ@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RqݗR@qTݗݗ`#Cݗg@q@Tҿݗݗ`#Cݗ/@ݗ CDݗ/@ݗ/@ݗ CݗPݗ@cC|ݗ/@+@7@SA[BcC{Ǩ_{S@@Tݗ@Cݗ`#\Geݗ@@ݗ''@@@Rݗ'@GT T ݗݗ/[ݗ/@/@@@@ ?ݗ`#F:ݗܽݗ+Eݗ+@+@@@@ ?ݗ`# A$ݗ)ݗݗݗ ݗݗݗSA{ƨ_{S@@Tݗ@ݗ`#\Gݗ@@ݗ''@@@ݗ'@GT Tݗݗ/ݗ/@/@@@@ ?Pݗ`#Fݗpݗ+ٿݗ+@+@@@@ ?6ݗ`# AݗݗݗkݗݗݗbݗSA{ƨ_@@T@A@@_  _{ '@@@ݗ @@ݗ7ݗ@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTcݗ;ݗ`#CIݗ/@sݗ Cݗ/@Yݗ/@jݗ Cݗݗ@cC~|@Eݗ/@+@7@SA[BcC{Ǩ_{ '@@@Aݗ @@5ݗʹݗ@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ`#Cݗ/@ݗ C{ݗ/@ݗ/@ݗ C*ݗݗ@cC}|@ػݗ/@+@&7@SA[BcC{Ǩ_{S@@Tҵݗ@yݗ`#\Gݗ@@ݗOO@ *@@ݗO@GT TBݗ(ݗ/ґݗ/@/@@@@ ?ݗ`#Fpݗݗ+{ݗ+@+@@@@ ?ݗ`# AZݗ_ݗSݗ ݗVݗJݗݗSA{ƨ_{S@@TIݗ@ ݗ`#\G/ݗ@@ݗOO@ *@@(ݗO@GT Tݗݗ/%ݗ/@/@@@@ ?ݗ`#Fݗݗ+ݗ+@+@@@@ ?lݗ`# AݗݗݗݗݗݗݗSA{ƨ_@@T@A@@_  _{ @@@ݗ @@ݗmݗ@@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!R6ݗR@qTҗݗoݗ`#C}ݗg@q@T҄ݗ\ݗ`#Cjݗ/@ݗ C ݗ/@zݗ/@ݗ Cݗݗ@cCgݗ/@+@7@SA[BcC{Ǩ_{ @@@cݗ @@Wݗݗ@@ @{è_{S[c/+'Rg'@Rg@ KA Rg@@K (7/@!RݗR@qTݗݗ`#Cݗg@q@Tݗݗ`#Cݗ/@ݗ Cݗ/@ݗ/@ ݗ C7ݗݗ@cC|ݗ/@+@7@SA[BcC{Ǩ_{S@@Tüݗ@ݗ`#\Gݗ@@>ݗ''@@@ݗ'@GT TPݗ6ݗ/ҟݗ/@/@@@@ ?ݗ`#F~ݗ ݗ+҉ݗ+@+@@@@ ?ݗ`# AhݗmݗaݗݗdݗXݗݗSA{ƨ_{S@@TWݗ@ݗ`#\G=ݗ@@ݗ''@@@*ݗ'@GT Tݗʹݗ/3ݗ/@/@@@@ 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R/@ݗR@qTݗ;ݗ"C>ݗ/@1ݗAs@qTݗ;ݗ"C>ݗC=ݗkk@qT/@1ݗ\Dkk@qTҼݗ;ݗ"C>ݗk@" D9/@1ݗ C<8ݗ/@1ݗ CAݗ<ݗ@0ݗ/@1ݗ C9ݗs<ݗ@0ݗ ݗ&ݗ&<ݗ/@1ݗ"Ao@qT "E@9qT/@1ݗ"Ao@qT /@1ݗXD"BEB@9!*X"E9+@a /@h;@"!D?@!@A?@TݗSA[B@{Ȩ_@@T@A@@_  _{S['#"D@7R_@R_@ KA R_@@K (3R'@ݗR@qTݗ:ݗ"C=ݗ'@1ݗAs@qTݗ:ݗ"C=ݗ<ݗ[[@qT'@0ݗ\D[[@qTݗ:ݗ"C=ݗ[@" D9'@0ݗ U7ݗ'@0ݗ Aݗ;ݗ@*ݗ*'@0ݗ 8ݗ;ݗ@*ݗ**0ݗ3,ݗB;ݗ'@0ݗ"A_@qT "E@9qT'@0ݗ"A_@qT '@0ݗXD"BEB@9!*X"E9#@a '@<3@"!D7@!@A?@T ݗSA[B{Ǩ_{S['#"D@7R_@R_@ KA R_@@K (3R'@ݗR@qT<ݗ:ݗ"C"=ݗ'@L0ݗAs@qT#ݗ9ݗ"C =ݗ/<ݗ[[@qT'@-0ݗ\D[[@qT ݗ9ݗ"C<ݗ[@" D9'@0ݗ 6ݗ'@0ݗ <@ݗ:ݗ@)ݗ*'@0ݗ 7ݗ:ݗ@)ݗ**/ݗh+ݗw:ݗ'@/ݗ"A_@qT "E@9qT'@/ݗ"A_@qT '@/ݗXD"BEB@9!*X"E9#@a '@q3@"!D7@!@A?@T- ݗSA[B{Ǩ_@@T@A@@_  _{S'#"D@7R_@R_@ KA R_@@K (3R'@ ݗR@qTYݗ19ݗ"C?<ݗ_@q@TFݗ9ݗ"C,<ݗ'@V/ݗAs@qT-ݗ9ݗ"C<ݗ'@=/ݗ 5ݗ'@7/ݗ d?ݗ ݗ@@ݗ-ݗ9ݗ'@'/ݗ"A_@qT #@a @'@s3@"!D7@!@A?@T ݗSA@{Ǩ_{S'#"D@7R_@R_@ KA R_@@K (3R'@d ݗR@qTݗ8ݗ"C;ݗ_@q@TҲݗ8ݗ"C;ݗ'@.ݗAs@qTҙݗq8ݗ"C;ݗ'@.ݗ 5ݗ'@.ݗ >ݗ- ݗ@@ݗ,ݗ9ݗ'@.ݗ"A_@qT #@a @'@3@"!D7@!@A?@T ݗSA@{Ǩ_@@T@A@@_  _{S'#"D@7R_@R_@ KA R_@@K (3R'@ ݗR@qTݗ7ݗ"C:ݗ'@).ݗAs@qTݗ7ݗ"C:ݗ'@.ݗ 4ݗ'@ .ݗ 7>ݗ ݗ@ݗq)ݗ8ݗ'@-ݗ"A_@qT #@a '@3@"!D7@!@A?@TT ݗSA@{Ǩ_{S'#"D@7R_@R_@ KA R_@@K (3R'@7 ݗR@qTҘݗp7ݗ"C~:ݗ'@-ݗAs@qTݗW7ݗ"Ce:ݗ'@-ݗ 4ݗ'@-ݗ =ݗ ݗ@ݗ(ݗ7ݗ'@y-ݗ"A_@qT #@a '@3@"!D7@!@A?@T ݗSA@{Ǩ_@@T@A@@_  _{S'#RW@RW@ KA RW@@K (/R'@ ݗR@qTݗ6ݗ"C9ݗW@q@Tݗ6ݗ"C9ݗ'@-ݗAs@qTݗ6ݗ"C9ݗ'@,ݗ ]3ݗ'@,ݗ =ݗ7ݗ@ ݗ#@a @'@/@SA@{ƨ_{S'#RW@RW@ KA RW@@K (/R'@- ݗR@qTҎݗf6ݗ"Ct9ݗW@q@T{ݗS6ݗ"Ca9ݗ'@,ݗAs@qTbݗ:6ݗ"CH9ݗ'@r,ݗ 2ݗ'@l,ݗ <ݗ*7ݗ@Q ݗ#@a @'@/@SA@{ƨ_@@T@A@@_  _{S'#RW@RW@ KA RW@@K (/R'@ ݗR@qTݗ5ݗ"C8ݗ'@,ݗAs@qT ݗ5ݗ"C8ݗ'@+ݗ l2ݗ'@+ݗ <ݗ6ݗ@|@ ݗ#@a '@/@SA@{ƨ_{S'#RW@RW@ KA RW@@K (/R'@; ݗR@qTҜ ݗt5ݗ"C8ݗ'@+ݗAs@qT҃ ݗ[5ݗ"Ci8ݗ'@+ݗ 2ݗ'@+ݗ ;ݗK6ݗ@|@q ݗ#@a '@7/@SA@{ƨ_@@T@A@@_  _{S[/+'"D@?Ro'@Ro@ KA Ro@@K (;R/@ ݗR@qT ݗ4ݗ"C8ݗ/@*+ݗAs@qT ݗ4ݗ"C7ݗC 7ݗkk@qT/@ +ݗ\Dkk@qT ݗ4ݗ"C7ݗk@" D9/@*ݗ Ch1ݗ/@*ݗ C;ݗ5ݗ@ݗAc<ݗ/@*ݗ C2ݗ5ݗ@ݗ/@*ݗ C2ݗ5ݗ@ݗAK<ݗ6ݗ(ݗE5ݗ/@*ݗ"Ao@qT "E@9qT/@*ݗ"Ao@qT /@*ݗXD"BEB@9!*X"E9+@ @/@+;@"!D?@!@A?@TݗSA[B@{Ȩ_{S[/+'"D@?Ro'@Ro@ KA Ro@@K (;R/@ݗR@qT= ݗ4ݗ!C#7ݗ/@M*ݗAs@qT$ ݗ3ݗ!C 7ݗC06ݗkk@qT/@.*ݗ\Dkk@qT ݗ3ݗ!C6ݗk@! D9/@*ݗ C0ݗ/@*ݗ C=:ݗ4ݗ@ܗA҆;ݗ/@*ݗ C1ݗ4ݗ@ܗ/@)ݗ CUݗ4ݗ@ܗAn;ݗ5ݗ'ݗh4ݗ/@)ݗ"Ao@qT "E@9qT/@)ݗ"Ao@qT /@)ݗXD"BEB@9!*X"E9+@ @/@N;@!!D?@!@A?@TݗSA[B@{Ȩ_@@T@A@@_  _{S[c#73/!D@GR/@R@ KA R@@K (C! R7@ݗR@qTG ݗ3ݗ!C-6ݗ7@W)ݗAs@qT. ݗ3ݗ!C6ݗ:5ݗ{{@qT7@8)ݗ\D{{@qT ݗ2ݗ!C5ݗ{@! D97@ )ݗ /ݗ7@)ݗ G9ݗ3ݗ@F(ݗ:ݗ7@ )ݗ 1ݗ3ݗ@9(ݗ7@)ݗ ^ݗ3ݗ@-(ݗ:ݗݗݗo3ݗ7@(ݗ"A@qT "E@9qT7@(ݗ"A@qT 7@(ݗXD"BEB@9!*X"E93@ 7@'C@!!DG@!@A?@T%ݗSA[BcC#@{ɨ_{S[c#73/!D@GR/@R@ KA R@@K (C! R7@ݗR@qTe ݗ=2ݗ!CK5ݗ7@u(ݗAs@qTL ݗ$2ݗ!C25ݗX4ݗ{{@qT7@V(ݗ\D{{@qT3 ݗ 2ݗ!C5ݗ{@! D97@>(ݗ .ݗ7@8(ݗ e8ݗ2ݗ@d'ݗ9ݗ7@+(ݗ  0ݗ2ݗ@W'ݗ7@(ݗ |ݗ2ݗ@K'ݗ9ݗݗݗ2ݗ7@(ݗ"A@qT "E@9qT7@'ݗ"A@qT 7@'ݗXD"BEB@9!*X"E93@ 7@EC@!!DG@!@A?@TCݗSA[BcC#@{ɨ_@@T@A@@_  _{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@ ݗR@qTl ݗD1ݗ!CR4ݗ/@|'ݗAs@qTS ݗ+1ݗ!C94ݗC_3ݗkk@qT/@]'ݗ\Dkk@qT: ݗ1ݗ!C 4ݗk@! D9/@E'ݗ C-ݗ/@?'ݗ Cl7ݗ1ݗ@ ݗREܗ*/@2'ݗ C'/ݗ1ݗ@ ݗ*/@''ݗ Cݗ1ݗ@ ݗR-ܗ***-ݗ"ݗ1ݗ/@'ݗ"Ao@qT "E@9qT/@&ݗ"Ao@qT /@&ݗXD"BEB@9!*X"E9+@ Ҡ/@,;@!!D?@!@A?@TNݗSA[B@{Ȩ_{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@/ݗR@qTҐݗh0ݗ!Cv3ݗ/@&ݗAs@qTwݗO0ݗ!C]3ݗC2ݗkk@qT/@&ݗ\Dkk@qT^ݗ60ݗ!CD3ݗk@! D9/@i&ݗ C,ݗ/@c&ݗ C6ݗ!1ݗ@# ݗRiܗ*/@V&ݗ CK.ݗ1ݗ@ ݗ*/@K&ݗ Cݗ 1ݗ@ ݗRQܗ***Qݗ!ݗ0ݗ/@5&ݗ"Ao@qT !E@9qT/@"&ݗ"Ao@qT /@&ݗXD!BEB@9!*X!E9+@ Ҡ/@P;@!!D?@!@A?@TrݗSA[B@{Ȩ_@@T@A@@_  _{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@;ݗR@qTҜݗt/ݗ!C2ݗ/@%ݗAs@qT҃ݗ[/ݗ!Ci2ݗC1ݗkk@qT/@%ݗ\Dkk@qTjݗB/ݗ!CP2ݗk@! D9/@u%ݗ C+ݗ/@o%ݗ C5ݗ-0ݗ@OܗA6ݗ/@b%ݗ CW-ݗ 0ݗ@Bܗ/@W%ݗ Cܗ0ݗ@7ܗ'1ݗ:#ݗ/ݗ/@C%ݗ"Ao@qT !E@9qT/@0%ݗ"Ao@qT /@"%ݗXD!BEB@9!*X!E9+@a @/@-;@!!D?@!@A?@TݗSA[B@{Ȩ_{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@`ݗR@qTݗ.ݗ!C1ݗ/@$ݗAs@qTҨݗ.ݗ!C1ݗC0ݗkk@qT/@$ݗ\Dkk@qTҏݗg.ݗ!Cu1ݗk@! D9/@$ݗ C+ݗ/@$ݗ C4ݗR/ݗ@tܗA 6ݗ/@$ݗ C|,ݗE/ݗ@gܗ/@|$ݗ Cܗ:/ݗ@\ܗL0ݗ_"ݗ.ݗ/@h$ݗ"Ao@qT !E@9qT/@U$ݗ"Ao@qT /@G$ݗXD!BEB@9!*X!E9+@a @/@R;@!!D?@!@A?@TݗSA[B@{Ȩ_@@T@A@@_  _{S[c#73/!D@GR/@R@ KA R@@K (C! R7@lݗR@qTݗ-ݗ!C0ݗ7@#ݗAs@qTҴݗ-ݗ!C0ݗ/ݗ{{@qT7@#ݗ\D{{@qTқݗs-ݗ!C0ݗ{@! D97@#ݗ *ݗ7@#ݗ 3ݗ^.ݗ@"ݗ_5ݗ7@#ݗ +ݗQ.ݗ@"ݗ7@#ݗ ܗE.ݗ@"ݗݗ_ݗ-ݗ7@p#ݗ"A@qT !E@9qT7@]#ݗ"A@qT 7@O#ݗXD!BEB@9!*X!E93@a 7@(C@!!DG@!@A?@TݗSA[BcC#@{ɨ_{S[c#73/!D@GR/@R@ KA R@@K (C! R7@ݗR@qTݗ,ݗ!C/ݗ7@"ݗAs@qTݗ,ݗ!C/ݗ.ݗ{{@qT7@"ݗ\D{{@qTҺݗ,ݗ!C/ݗ{@! D97@"ݗ :)ݗ7@"ݗ 2ݗ}-ݗ@!ݗ~4ݗ7@"ݗ *ݗp-ݗ@!ݗ7@"ݗ ܗd-ݗ@!ݗ3ܗ~ݗ-ݗ7@"ݗ"A@qT !E@9qT7@|"ݗ"A@qT 7@n"ݗXD!BEB@9!*X!E93@a 7@GC@!!DG@!@A?@TܗSA[BcC#@{ɨ_@@T@A@@_  _{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@ݗR@qTݗ+ݗ!C.ݗ/@"ݗAs@qTݗ+ݗ!C.ݗC-ݗkk@qT/@!ݗ\Dkk@qTݗ+ݗ!C.ݗk@! D9/@!ݗ CB(ݗ/@!ݗ C1ݗ,ݗ@ݗRܗ*/@!ݗ C)ݗx,ݗ@zݗ*/@!ݗ C ܗm,ݗ@oݗ***ܗݗ!,ݗ/@!ݗ"Ao@qT !E@9qT/@!ݗ"Ao@qT /@z!ݗXD!BEB@9!*X!E9+@a Ҡ/@.;@!!D?@!@A?@TܗSA[B@{Ȩ_{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@ܗR@qTݗ*ݗ!C.ݗ/@*!ݗAs@qTݗ*ݗ!C-ݗC -ݗkk@qT/@ !ݗ\Dkk@qTݗ*ݗ!C-ݗk@! D9/@ ݗ Ch'ݗ/@ ݗ C1ݗ+ݗ@ݗRܗ*/@ ݗ C(ݗ+ݗ@ݗ*/@ ݗ C2ܗ+ݗ@ݗ***ܗ8ݗG+ݗ/@ ݗ"Ao@qT !E@9qT/@ ݗ"Ao@qT /@ ݗXD!BEB@9!*X!E9+@a Ҡ/@T;@!!D?@!@A?@TܗSA[B@{Ȩ_@@T@A@@_  _{S'#RW@RW@ KA RW@@K (/R'@ܗR@qT.ݗ*ݗ!C-ݗ'@> ݗAs@qTݗ)ݗ!C,ݗ'@ݗ'@" ݗ O0ݗܗ@ݗs'@ ݗ  (ݗ*ݗ@ݗ#@Ҡ'@/@SA@{ƨ_{S'#RW@RW@ KA RW@@K (/R'@bܗR@qTݗ)ݗ!C,ݗ'@ݗAs@qTҪݗ)ݗ!C,ݗ'@ݗ'@ݗ /ݗAܗ@rݗs'@ݗ 'ݗi*ݗ@lݗ#@Ҡ'@)/@SA@{ƨ_{ RR@!ݗR!R@ܗ{` @{è_@@T@A@@_  _{S['#!D@7R_@R_@ KA R_@@K (3R'@ܗR@qT)ݗ)ݗ!C,ݗ'@9ݗAs@qTݗ(ݗ!C+ݗ'@ ݗ %ݗ'@ݗ G/ݗ)ݗ@ܗ@'@ݗ 'ݗ)ݗ@ܗA`0ݗݗ)ݗ'@ݗ"A_@qT #@a @'@x3@!!D7@!@A?@TVܗSA[B{Ǩ_{S['#!D@7R_@R_@ KA R_@@K (3R'@9ܗR@qTҚݗr(ݗ!C+ݗ'@ݗAs@qTҁݗY(ݗ!Cg+ݗ'@ݗ %ݗ'@ݗ .ݗI)ݗ@kܗ@'@ݗ u&ݗ>)ݗ@`ܗA`/ݗdݗ(ݗ'@mݗ"A_@qT #@a @'@3@!!D7@!@A?@TܗSA[B{Ǩ_@@T@A@@_  _{S['#!D@7R_@R_@ KA R_@@K (3! R'@ܗR@qTܗ'ݗ!C*ݗ'@ݗAs@qTܗ'ݗ!C*ݗ'@ݗ _$ݗ'@ݗ .ݗ(ݗ'@ݗ %ݗ(ݗRR @@%ݗݗN(ݗ'@ݗ"A_@qT #@a '@z3@!!D7@!@A?@T"ܗSA[B{Ǩ_{S['#!D@7R_@R_@ KA R_@@K (3! R'@ܗR@qTfܗ>'ݗ!CL*ݗ'@vݗAs@qTMܗ%'ݗ!C3*ݗ'@]ݗ #ݗ'@Wݗ -ݗ(ݗ'@Nݗ C%ݗ (ݗRR @@+%ݗ*ݗ'ݗ'@;ݗ"A_@qT #@a '@3@!!D7@!@A?@TܗSA[B{Ǩ_{9{9!D@'Ҡ@@{@9q`T@@9q`TҢ@A C!BD'@B@b_@Tkܗ{Ũ_@@T@A@@_  _{S['#!D@7R_@R_@ KA R_@@K (3R'@8ܗR@qTҙܗq&ݗ!C)ݗ'@ݗAs@qTҀܗX&ݗ!Cf)ݗ'@ݗ #ݗ'@ݗ ,ݗH'ݗ@Jݗx'@ݗ t$ݗ='ݗ@?ݗ`*ܗݗ&ݗ'@lݗ"A_@qT #@a '@x3@!!D7@!@A?@TܗSA[B{Ǩ_{S['#!D@7R_@R_@ KA R_@@K (3R'@ܗR@qT ܗ%ݗ!C(ݗ'@ݗAs@qTܗ%ݗ!C(ݗ'@ݗ v"ݗ'@ݗ (,ݗ&ݗ@ݗx'@ݗ #ݗ&ݗ@ݗ`*ܗTݗc&ݗ'@ݗ"A_@qT #@a '@3@!!D7@!@A?@T7ܗSA[B{Ǩ_@@T@A@@_  _{S['#!D@7R_@R_@ KA R_@@K (3R'@ܗR@qTcܗ;%ݗ!CI(ݗ'@sݗAs@qTJܗ"%ݗ!C0(ݗ'@Zݗ !ݗ'@Tݗ +ݗ&ݗ@4ܗ@'@Iݗ >#ݗ&ݗ@)ܗ A`,ݗ,ݗ%ݗ'@5ݗ"A_@qT #@a @'@w3@!!D7@!@A?@TܗSA[B{Ǩ_{S['#!D@7R_@R_@ KA R_@@K (3R'@rܗR@qTܗ$ݗ!C'ݗ'@ݗAs@qTҺܗ$ݗ!C'ݗ'@ݗ ?!ݗ'@ݗ *ݗ%ݗ@ܗ@'@ݗ "ݗw%ݗ@ܗ A`-,ݗݗ+%ݗ'@ݗ"A_@qT #@a @'@3@!!D7@!@A?@TܗSA[B{Ǩ_@@T@A@@_  _{S['#!D@7R_@R_@ KA R_@@K (3! R'@ܗR@qT+ܗ$ݗ!C'ݗ'@;ݗAs@qTܗ#ݗ!C&ݗ'@"ݗ  ݗ'@ݗ I*ݗ$ݗ'@ݗ "ݗ$ݗR$R @@!ݗݗ$ݗ'@ݗ"A_@qT #@a '@z3@!!D7@!@A?@TZܗSA[B{Ǩ_{S['#!D@7R_@R_@ KA R_@@K (3! R'@=ܗR@qTҞܗv#ݗ!C&ݗ'@ݗAs@qT҅ܗ]#ݗ!Ck&ݗ'@ݗ  ݗ'@ݗ )ݗM$ݗ'@ݗ {!ݗD$ݗR$R @@c!ݗbݗ#ݗ'@sݗ"A_@qT #@a '@3@!!D7@!@A?@TܗSA[B{Ǩ_@@T@A@@_  _{S['#!D@7R_@R_@ KA R_@@K (3R'@ܗR@qTܗ"ݗ!C%ݗ'@ ݗAs@qTܗ"ݗ!C%ݗ'@ݗ eݗ'@ݗ )ݗ#ݗ@ݗx'@ݗ  ݗ#ݗ@ݗ *`*ܗBݗQ#ݗ'@ݗ"A_@qT #@a '@w3@!!D7@!@A?@T%ܗSA[B{Ǩ_{S['#!D@7R_@R_@ KA R_@@K (3R'@ܗR@qTiܗA"ݗ!CO%ݗ'@yݗAs@qTPܗ("ݗ!C6%ݗ'@`ݗ ݗ'@Zݗ (ݗ#ݗ@ݗx'@Oݗ D ݗ #ݗ@ݗ *`*Sܗݗ"ݗ'@;ݗ"A_@qT #@a '@3@!!D7@!@A?@TܗSA[B{Ǩ_@@T@A@@_  _{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@_ܗR@qTܗ!ݗ!C$ݗ/@ݗAs@qTҧܗ!ݗ!C$ݗ/@ݗ C,ݗ/@ݗ C'ݗo"ݗ@ܗ@/@ݗ C'ݗd"ݗ@ܗ/@ݗ CݗY"ݗ@{ܗA`)ݗ~ݗ "ݗ/@ݗ"Ao@qT +@a @/@k;@!!D?@!@A?@TܗSA[B@{Ȩ_{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@ܗR@qT#ܗ ݗ!C $ݗ/@3ݗAs@qT ܗ ݗ!C#ݗ/@ݗ Cݗ/@ݗ CA'ݗ!ݗ@ܗ@/@ ݗ C6'ݗ!ݗ@ܗ/@ݗ Cݗ!ݗ@ܗA`r(ݗݗp!ݗ/@ݗ"Ao@qT +@a @/@;@!!D?@!@A?@TDܗSA[B@{Ȩ_@@T@A@@_  _{S['#!D@7R_@R_@ KA R_@@K (3! R'@ܗR@qToܗG ݗ!CU#ݗ'@ݗAs@qTVܗ. ݗ!C<#ݗ'@fݗ ݗ'@`ݗ &ݗ!ݗ'@Wݗ Lݗ!ݗ%RR @@4ݗ3 ݗ ݗ'@Dݗ"A_@qT #@a '@z3@!!D7@!@A?@TܗSA[B{Ǩ_{S['#!D@7R_@R_@ KA R_@@K (3! R'@ܗR@qTܗݗ!C"ݗ'@ݗAs@qTܗݗ!C"ݗ'@ݗ Nݗ'@ݗ &ݗ ݗ'@ݗ ݗ ݗ%RR @@ݗ ݗ= ݗ'@ݗ"A_@qT #@a '@3@!!D7@!@A?@TܗSA[B{Ǩ_@@T@A@@_  _{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@ܗR@qT<ܗݗ!C""ݗ/@LݗAs@qT#ܗݗ!C "ݗ/@3ݗ Cݗ/@-ݗ CZ%ݗݗ@ݗx/@"ݗ CO%ݗݗ@ݗ*/@ݗ C ݗݗ@ݗJ`*ܗzݗݗ/@ݗ"Ao@qT +@a /@k;@!!D?@!@A?@T]ܗSA[B@{Ȩ_{S[/+'!D@?Ro'@Ro@ KA Ro@@K (;R/@>ܗR@qTҟܗwݗ!C!ݗ/@ݗAs@qT҆ܗ^ݗ!Cl!ݗ/@ݗ C ݗ/@ݗ C$ݗNݗ@Pݗx/@ݗ C$ݗCݗ@Eݗ*/@zݗ Coݗ8ݗ@:ݗJ`*~ܗݗݗ/@fݗ"Ao@qT +@a /@;@!!D?@!@A?@TܗSA[B@{Ȩ_@@T@A@@_  _{S'#RW@RW@ KA RW@@K (/! R'@ܗR@qTܗݗ!C ݗ'@ݗAs@qTܗݗ!C ݗ'@ ݗ'@ݗ $ݗnܗ@ݗs'@ݗ ݗݗ @ݗ#@Ҡ'@/@SA@{ƨ_{S'#RW@RW@ KA RW@@K (/! R'@%ܗR@qT҆ܗ^ݗ!Cl ݗ'@ݗAs@qTmܗEݗ!CS ݗ'@i ݗ'@zݗ #ݗܗ@5ݗs'@nݗ cݗ,ݗ @ݗ#@Ҡ'@+/@SA@{ƨ_{ @ @T3ܗ@ ݗ!\G ݗ@@@ ݗ@ @@ݗ  @{Ĩ_@@T@A@@_  _{S'#!D@7R_@R_@ KA R_@@K (3R'@xܗR@qTܗݗ!Cݗ'@ݗAs@qTܗݗ!Cݗݗ[[@qT'@ݗ\D[[@qTҧܗݗ!Cݗ[@! D9'@ݗ 'ݗ'@ݗ "ݗjݗ@ܗk&ݗݗ!ݗ'@ݗ"A_@qT !E@9qT'@ݗ"A_@qT '@zݗXD!BEB@9!*X!E9#@a @'@I3@!!D7@!@A?@TܗSA@{Ǩ_{S'#!D@7R_@R_@ KA R_@@K (3R'@ܗR@qTܗݗ!Cݗ'@+ݗAs@qTܗݗ!Cݗݗ[[@qT'@ ݗ\D[[@qTܗݗ!Cݗ[@! D9'@ݗ iݗ'@ݗ "ݗݗ@ܗ%ݗݗcݗ'@ݗ"A_@qT !E@9qT'@ݗ"A_@qT '@ݗXD!BEB@9!*X!E9#@a @'@3@!!D7@!@A?@TܗSA@{Ǩ_@@T@A@@_  _{S'#!D@7R_@R_@ KA R_@@K (3! R'@ܗR@qTEܗݗ!C+ݗ'@UݗAs@qT,ܗݗ!Cݗ8ݗ[[@qT'@6ݗ\D[[@qTܗݗ!Cݗ[@! D9'@ݗ ݗ'@ݗ E!ݗݗ@Dݗ{ݗݗݗ'@ݗ"A_@qT !E@9qT'@ݗ"A_@qT '@ݗXD!BEB@9!*X!E9#@a '@I3@!!D7@!@A?@TCܗSA@{Ǩ_{S'#!D@7R_@R_@ KA R_@@K (3! R'@&ܗR@qT҇ܗ_ݗ!Cmݗ'@ݗAs@qTnܗFݗ!CTݗzݗ[[@qT'@xݗ\D[[@qTUܗ-ݗ!C;ݗ[@! D9'@`ݗ ݗ'@Zݗ  ݗݗ@ݗݗ8ݗݗ'@Iݗ"A_@qT !E@9qT'@6ݗ"A_@qT '@(ݗXD!BEB@9!*X!E9#@a '@3@!!D7@!@A?@TܗSA@{Ǩ_@@T@A@@_  _{S'#!D@7R_@R_@ KA R_@@K (3R'@PܗR@qTұܗݗ!Cݗ'@ݗAs@qTҘܗpݗ!C~ݗݗ[[@qT'@ݗ\D[[@qTܗWݗ!Ceݗ[@! D9'@ݗ ݗ'@ݗ ݗBݗ@D ݗGݗ ݗݗ'@sݗ"A_@qT !E@9qT'@`ݗ"A_@qT '@RݗXD!BEB@9!*X!E9#@a '@I3@!!D7@!@A?@TܗSA@{Ǩ_{S'#!D@7R_@R_@ KA R_@@K (3R'@ܗR@qTܗݗ!Cݗ'@ݗAs@qTܗݗ!Cݗݗ[[@qT'@ݗ\D[[@qTܗݗ!Cݗ[@! D9'@ݗ Aݗ'@ݗ ݗݗ@ݗݗ, ݗ;ݗ'@ݗ"A_@qT !E@9qT'@ݗ"A_@qT '@ݗXD!BEB@9!*X!E9#@a '@3@!!D7@!@A?@TܗSA@{Ǩ_@@T@A@@_  _{S['#!D@7R_@R_@ KA R_@@K (3R'@ܗR@qTܗݗ!Cݗ'@-ݗAs@qTܗݗ!Cݗݗ[[@qT'@ݗ\D[[@qTܗݗ!Cݗ[@! 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RۗGۗ@ }ۗ@ Jۗ@ vۗ RRۗGۗ@ gۗ@ 4ۗ@ `ۗ `RRۗGؓۗ@ Qۗ@ ۗ@ Jۗ RbRiۗG“ۗ@ ;ۗ@ ۗ@ 4ۗ RrbRRۗGۗ@ $ۗ@ ۗ@ ۗ RbR<ۗGۗ@ ۗ@ ێۗ@ ۗ RbR&ۗGۗ@ ۗ@ Ŏۗ@ ۗ @RbRۗGiۗ@ ۗ@ ۗ@ ۬ۗ RrbRۗGRۗ@ ˍۗ@ ۗ@ Ĭۗ RrbRrۗG:ۗ@ ۗ@ ۗ@ Ҭۗ `RbRۗG$ۗ@ ۗ@ jۗ@ Җۗ RbRۗGۗ@ ۗ@ Tۗ@ Ҁۗ RrbRۗGۗ@ pۗ@ =ۗ@ iۗ RrbRrۗGߒۗ@ Xۗ@ %ۗ@ Qۗ RrbRoۗGȒۗ@ Aۗ@ ۗ@ :ۗ @RrbRXۗGۗ@ *ۗ@ ۗ@ #ۗ RrbRAۗGۗ@ ۗ@ ۗ@  ۗ RrbR*ۗGۗ@ ۗ@ ɍۗ@ ۗ `RrbRۗGlۗ@ ۗ@ ۗ@ ޫۗ RrbRrۗGTۗ@ ͌ۗ@ ۗ@ ƫۗ RrbRۗG=ۗ@ ۗ@ ۗ@ үۗ RrbRۗG&ۗ@ ۗ@ lۗ@ Ҙۗ RbRۗGۗ@ ۗ@ Vۗ@ ҂ۗ @ RrbRۗGۗ@ rۗ@ ?ۗ@ kۗ RrbRۗGۗ@ [ۗ@ (ۗ@ Tۗ RrbRrqۗGʑۗ@ Cۗ@ ۗ@ <ۗ ` RrbRZۗGۗ@ ,ۗ@ ۗ@ %ۗ RrbRrBۗGۗ@ ۗ@ ۗ@  ۗ RrbR+ۗGۗ@ ۗ@ ʌۗ@ ۗ RrbRۗGmۗ@ ۗ@ ۗ@ ߪۗ RrbRrۗGUۗ@ ΋ۗ@ ۗ@ Ǫۗ @ RbRۗG?ۗ@ ۗ@ ۗ@ ұۗ RbRۗG)ۗ@ ۗ@ oۗ@ қۗ RbRۗGۗ@ ۗ@ Yۗ@ ҅ۗ `RbRۗGۗ@ vۗ@ Cۗ@ oۗ RbRۗGۗ@ `ۗ@ -ۗ@ Yۗ RbRxۗGѐۗ@ Jۗ@ ۗ@ Cۗ RbRbۗGۗ@ 4ۗ@ ۗ@ -ۗ RbRLۗGۗ@ ۗ@ ۗ@ ۗ @RbR6ۗGۗ@ ۗ@ Ջۗ@ ۗ RbR ۗGyۗ@ ۗ@ ۗ@ ۗ RbR ۗGcۗ@ ܊ۗ@ ۗ@ թۗ `RRۗGMۗ@ Ɗۗ@ ۗ@ ҿۗ RRۗG7ۗ@ ۗ@ }ۗ@ ҩۗ RrbR@rۗGۗ@ ۗ@ eۗ@ ґۗ RrbR@rۗGۗ@ ۗ@ Mۗ@ yۗ RrbR@rۗGۗ@ hۗ@ 5ۗ@ aۗ @RrbR@r~ۗG׏ۗ@ Pۗ@ ۗ@ Iۗ RrbR@rfۗGۗ@ 8ۗ@ ۗ@ 1ۗ RrbR@rNۗGۗ@ ۗ@ ۗ@ ۗ `RrbR@r6ۗGۗ@ ۗ@ Պۗ@ ۗ RrbR@rۗGwۗ@ ۗ@ ۗ@ ۗ RrbR@rۗG_ۗ@ ؉ۗ@ ۗ@ Ѩۗ RrbR@rۗGGۗ@ ۗ@ ۗ@ ҹۗ RrbR@rۗG/ۗ@ ۗ@ uۗ@ ҡۗ @RrbR@rۗGۗ@ ۗ@ ]ۗ@ ҉ۗ RrbR@rۗGۗ@ xۗ@ Eۗ@ qۗ RrRۗGۗ@ aۗ@ .ۗ@ Zۗ `RrRrwۗGЎۗ@ Iۗ@ ۗ@ Bۗ RrRr_ۗGۗ@ 1ۗ@ ۗ@ *ۗ RrRrGۗGۗ@ ۗ@ ۗ@ ۗ RrRr/ۗGۗ@ ۗ@ Ήۗ@ ۗ RrRrۗGpۗ@ ۗ@ ۗ@ ۗ @RrRrۗGXۗ@ шۗ@ ۗ@ ʧۗ RrRrۗG@ۗ@ ۗ@ ۗ@ Ҳۗ @RrRrϿۗG(ۗ@ ۗ@ nۗ@ Қۗ R>rRrۗGۗ@ ۗ@ Vۗ@ ҂ۗ RrRrۗGۗ@ qۗ@ >ۗ@ jۗ RrRۗGۗ@ Zۗ@ 'ۗ@ Sۗ RrRrpۗGɍۗ@ Bۗ@ ۗ@ ;ۗ @RrRrXۗGۗ@ *ۗ@ ۗ@ #ۗ RrRr@ۗGۗ@ ۗ@ ߈ۗ@  ۗ RrRr(ۗGۗ@ ۗ@ Ljۗ@ ۗ `RrRrۗGiۗ@ ۗ@ ۗ@ ۦۗ RrRrۗGQۗ@ ʇۗ@ ۗ@ æۗ @RrRrۗG9ۗ@ ۗ@ ۗ@ ҫۗ RrRrȾۗG!ۗ@ ۗ@ gۗ@ ғۗ @R>rRrۗG ۗ@ ۗ@ Oۗ@ {ۗ RrRrۗGۗ@ jۗ@ 7ۗ@ cۗ bRۗGیۗ@ Tۗ@ !ۗ@ Mۗ ` bRrkۗGČۗ@ =ۗ@ ۗ@ 6ۗ bRrTۗGۗ@ &ۗ@ ۗ@ ۗ !bRr=ۗGۗ@ ۗ@ ܇ۗ@ ۗ !bRr&ۗGۗ@ ۗ@ Ňۗ@ ۗ !bRdrۗGhۗ@ ۗ@ ۗ@ ڥۗ @"W2bR@rۗGQۗ@ ʆۗ@ ۗ@ åۗ "bR rۗG:ۗ@ ۗ@ ۗ@ Ҭۗ #RbR˽ۗG$ۗ@ ۗ@ jۗ@ Җۗ #RbRۗGۗ@ ۗ@ Tۗ@ Ҁۗ #RbRۗGۗ@ qۗ@ >ۗ@ jۗ @$RbRۗGۗ@ [ۗ@ (ۗ@ Tۗ $RbRsۗG̋ۗ@ Eۗ@ ۗ@ >ۗ %RbR]ۗGۗ@ /ۗ@ ۗ@ (ۗ `%72b RGۗGۗ@ ۗ@ ۗ@ ۗ %72b Rr0ۗGۗ@ ۗ@ φۗ@ ۗ &72b RrۗGrۗ@ ۗ@ ۗ@ ۗ &72b RrۗG[ۗ@ ԅۗ@ ۗ@ ͤۗ &Rrb RrۗGCۗ@ ۗ@ ۗ@ ҵۗ @'Rrb RrҼۗG+ۗ@ ۗ@ qۗ@ ҝۗ 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Rr߸ۗG8ۗ@ ۗ@ ~ۗ@ Ҫۗ 8Rrb RrǸۗG ۗ@ ۗ@ fۗ@ Ғۗ `8Rrb RrۗGۗ@ ۗ@ Nۗ@ zۗ 8K 2b R@rۗGۗ@ jۗ@ 7ۗ@ cۗ 9K 2b RBrۗGچۗ@ Sۗ@ ۗ@ Lۗ 9K 2b RDrjۗGÆۗ@ <ۗ@ ۗ@ 5ۗ :K 2b RFrSۗGۗ@ %ۗ@ ۗ@ ۗ :Rrb R@r;ۗGۗ@ ۗ@ ځۗ@ ۗ :Rrb R@r#ۗG|ۗ@ ۗ@ ۗ@ ۗ @;K 2b Rr ۗGeۗ@ ހۗ@ ۗ@ ןۗ ;K 2b R¸rۗGNۗ@ ǀۗ@ ۗ@ ۗ <K 2b Rĸr޷ۗG7ۗ@ ۗ@ }ۗ@ ҩۗ <K 2b RƸrǷۗG ۗ@ ۗ@ fۗ@ Ғۗ =Rrb RrۗGۗ@ ۗ@ Nۗ@ zۗ `=Rrb RrۗGۗ@ iۗ@ 6ۗ@ bۗ =K 2b RrۗGمۗ@ Rۗ@ ۗ@ Kۗ >K 2b RriۗG…ۗ@ ;ۗ@ ۗ@ 4ۗ >K 2b RrRۗGۗ@ $ۗ@ ۗ@ ۗ ?K 2b Rr;ۗGۗ@ ۗ@ ڀۗ@ ۗ ?Rrb Rr#ۗG|ۗ@ ۗ@ €ۗ@ ۗ ?K 2b R@r ۗGeۗ@ ۗ@ ۗ@ מۗ @K 2b RBrۗGNۗ@ ۗ@ ۗ@ ۗ K 2b RDr޶ۗG7ۗ@ ۗ@ }ۗ@ ҩۗ K 2b RFrǶۗG ۗ@ ۗ@ fۗ@ Ғۗ Rrb R@rۗGۗ@ ۗ@ Nۗ@ zۗ K 2b RrۗGۗ@ jۗ@ 7ۗ@ cۗ `K 2b RºrۗGڄۗ@ Sۗ@ ۗ@ Lۗ K 2b RĺrjۗGÄۗ@ <ۗ@ ۗ@ 5ۗ @K 2b RƺrSۗGۗ@ %ۗ@ ۗ@ ۗ Rrb Rr;ۗGۗ@ ۗ@ ۗ@ ۗ RR%ۗG~ۗ@ ~ۗ@ ۗ@ ۗ RRۗGhۗ@ ~ۗ@ ۗ@ ڝۗ RRۗGRۗ@ ~ۗ@ ۗ@ ĝۗ @RRۗG<ۗ@ ~ۗ@ ۗ@ Үۗ RR͵ۗG&ۗ@ ~ۗ@ lۗ@ Ҙۗ RRۗGۗ@ ~ۗ@ Vۗ@ ҂ۗ `RrbRۗGۗ@ r~ۗ@ ?ۗ@ kۗ RrRۗGۗ@ [~ۗ@ (ۗ@ Tۗ Rrb RrۗG˃ۗ@ D~ۗ@ ۗ@ =ۗ Rr R[ۗGۗ@ -~ۗ@ ~ۗ@ &ۗ RrbR@rCۗGۗ@ ~ۗ@ ~ۗ@ ۗ @RrR@r+ۗGۗ@ }ۗ@ ~ۗ@ ۗ Rrb R@rۗGlۗ@ }ۗ@ ~ۗ@ ޜۗ Rr R@rۗGTۗ@ }ۗ@ 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p+ŝSG6j%p o^&L&ϫ ^FۄEk0SE# ś[[ڔQ+(ٳ'z8TfAX\$~sީqK3?#Db;uj= bڸC 7 RzRCK,΁2^_B?;5I~t۝Xv%RӮS;uD(m,{tPd弦a}J]J62w\Mľڬ:|\ 5$KB.̈Po ̼$ 믿ۘ6A_paw̫BzՔֶil7$GGŧ,eX= _Nm (which is %zu)%Y-%m-%d %H:%M:%S[*** LOG ERROR #%04zu ***] [%s] [%s] %s Rethrowing unknown exception in loggerPMAM %s:%d: assertion failed: %sinvalid fill character '{'invalid fillcannot switch from manual to automatic argument indexinginvalid number of digitsvalue is negative0123456789ABCDEFnumber is too biginvalid digit count00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899empty bufferexponent out of rangewidth/precision is not integercompile-time checks for named arguments require C++20 supportinvalid format stringcannot switch from automatic to manual argument indexingmissing precision specifierprecision not allowed for this argument typenaninfINFNANnegative widthwidth is not integernegative precisionprecision is not integerformat specifier requires numeric argumentformat specifier requires signed argument{} [{}({})]{:02}unmatched '}' in format stringinvalid type specifierunknown format specifiermissing '}' in format stringstring pointer is nullinvalid format specifier for chartruenegative valueunaligned bigintsriscv_plugin.ccargument not foundn is too largek is out of rangeshifting error detected0123456789abcdefRISCV plugin: hwts ISR called DESTROY RISCV PLUGIN RISCV plugin trace: 0x%x CREATE RISCV PLUGIN SPR_PCSPR_BLK_IDSPR_STATUSSPR_CTRLSPR_PARA_BASESPR_DATA_MAIN_BASESPR_DATA_UB_BASESPR_DATA_SIZESPR_LPCNTSPR_BLOCKDIMSPR_FMATRIXSPR_Condition_FlagSPR_DEQSCALESPR_LRELU_ALPHASPR_PADDINGSPR_L2_vaddr_baseSPR_L0_SET_VALUESPR_CORE_IDSPR_VMS4_SRSPR_L2_IN_MAINSPR_RPN_COR_IRSPR_ARCH_VERSPR_SMMU_TAG_VERSPR_L1_3D_SIZESPR_AIPP_SPR_0SPR_AIPP_SPR_1SPR_AIPP_SPR_2SPR_AIPP_SPR_3SPR_AIPP_SPR_4SPR_AIPP_SPR_5SPR_AIPP_SPR_6SPR_AIPP_SPR_7SPR_AIPP_SPR_8SPR_AIPP_SPR_9SPR_AIPP_SPR_10SPR_AIPP_SPR_11SPR_AIPP_SPR_12SPR_AIPP_SPR_13SPR_AIPP_SPR_14SPR_AIPP_SPR_15SPR_AIPP_SPR_16SPR_AIPP_SPR_17SPR_AIPP_SPR_18SPR_AIPP_SPR_19SPR_AIPP_SPR_20SPR_AIPP_SPR_21SPR_AIPP_SPR_22SPR_AIPP_SPR_23SPR_AIPP_SPR_24SPR_DATA_EXP_0SPR_DATA_EXP_1SPR_DATA_EXP_2SPR_DATA_EXP_3SPR_LOW_PRE_TBLSPR_SMASK_INDEXSPR_K_NUMSPR_RPN_OFFSETSPR_FCOL2IMGSPR_RSVD_CNTSPR_TIDSPR_CONDSPR_PNT_COESPR_VPIPESPR_MAX_MIN_CNTSPR_MASK1SPR_MASK2SPR_MASK3SPR_MASK4SPR_MASK5SPR_MASK6SPR_MASK7SPR_MASK8SPR_UNZIP_INDEX_BASESPR_UNZIP_INDEX_LENSPR_CMP_MASK1SPR_CMP_MASK2SPR_CMP_MASK3SPR_CMP_MASK4SPR_CMP_MASK5SPR_CMP_MASK6SPR_CMP_MASK7SPR_CMP_MASK8SPR_CONVSPR_SMMU_STREAMIDSPR_RUN_STALLSPR_SMMU_SUBSTREAMIDSPR_MEMMAP_0SPR_MEMMAP_1SPR_MEMMAP_2SPR_MEMMAP_3SPR_MEMMAP_4SPR_MEMMAP_5SPR_MEMMAP_6SPR_MEMMAP_7SPR_MEMMAP_8SPR_MEMMAP_9SPR_MEMMAP_10SPR_MEMMAP_11SPR_MEMMAP_12SPR_MEMMAP_13SPR_MEMMAP_14SPR_MEMMAP_15SPR_MEMMAP_16SPR_MEMMAP_17SPR_MEMMAP_18SPR_MEMMAP_19SPR_MEMMAP_20SPR_MEMMAP_21SPR_MEMMAP_22SPR_MEMMAP_23SPR_MEMMAP_24SPR_MEMMAP_25SPR_MEMMAP_26SPR_MEMMAP_27SPR_MEMMAP_28SPR_MEMMAP_29SPR_MEMMAP_30SPR_MEMMAP_31SPR_MEMMAP_32SPR_MEMMAP_33SPR_MEMMAP_34SPR_MEMMAP_35SPR_MEMMAP_36SPR_MEMMAP_37SPR_MEMMAP_38SPR_MEMMAP_39SPR_MEMMAP_40SPR_MEMMAP_41SPR_MEMMAP_42SPR_MEMMAP_43SPR_MEMMAP_44SPR_MEMMAP_45SPR_MEMMAP_46SPR_MEMMAP_47SPR_MEMMAP_48SPR_MEMMAP_49SPR_MEMMAP_50SPR_MEMMAP_51SPR_MEMMAP_52SPR_MEMMAP_53SPR_MEMMAP_54SPR_MEMMAP_55SPR_MEMMAP_56SPR_MEMMAP_57SPR_MEMMAP_58SPR_MEMMAP_59SPR_MEMMAP_60SPR_MEMMAP_61SPR_MEMMAP_62SPR_MEMMAP_63SPR_LITERAL_SRC_BASESPR_LITERAL_DST_BASESPR_LITERAL_SIZESPR_L2_PHYS_ADDR_BASESPR_MTE_CTRLSPR_BIU_CTRL8SPR_L2_SIZESPR_L2_PAGE_SIZESPR_CCU_STALL_ENSPR_L2_REMAP_CFG0SPR_L2_REMAP_CFG1SPR_L2_REMAP_CFG2SPR_L2_REMAP_CFG3SPR_L2_REMAP_CFG4SPR_L2_REMAP_CFG5SPR_L2_REMAP_CFG6SPR_L2_REMAP_CFG7SPR_L2_REMAP_PADDR_BASESPR_CUBE_RESERVED_REG01SPR_L3D_RPTVPR_SHARED_0VPR_SHARED_1VPR_SHARED_2VPR_SHARED_3VPR_SHARED_4VPR_SHARED_5VPR_SHARED_6VPR_SHARED_7VPR_SHARED_8VPR_SHARED_9VPR_SHARED_10VPR_SHARED_11VPR_SHARED_12VPR_SHARED_13VPR_SHARED_14VPR_SHARED_15VPR_SHARED_16VPR_SHARED_17VPR_SHARED_18VPR_SHARED_19VPR_SHARED_20VPR_SHARED_21VPR_SHARED_22VPR_SHARED_23VPR_SHARED_24VPR_SHARED_25VPR_SHARED_26VPR_SHARED_27VPR_SHARED_28VPR_SHARED_29VPR_SHARED_30VPR_SHARED_31VPR_SHARED_32VPR_SHARED_33VPR_SHARED_34VPR_SHARED_35VPR_SHARED_36VPR_SHARED_37VPR_SHARED_38VPR_SHARED_39VPR_SHARED_40VPR_SHARED_41VPR_SHARED_42VPR_SHARED_43VPR_SHARED_44VPR_SHARED_45VPR_SHARED_46VPR_SHARED_47VPR_SHARED_48VPR_SHARED_49VPR_SHARED_50VPR_SHARED_51VPR_SHARED_52VPR_SHARED_53VPR_SHARED_54VPR_SHARED_55VPR_SHARED_56VPR_SHARED_57VPR_SHARED_58VPR_SHARED_59VPR_SHARED_60VPR_SHARED_61VPR_SHARED_62VPR_SHARED_63Loop_I1Loop_I2Loop_I3Loop_I4Address_Reg_A0Address_Reg_A1Address_Reg_A2Address_Reg_A3Address_Reg_A4Address_Reg_A5Address_Reg_A6Address_Reg_A7VPR_VPCVPR_VPC_BASEVPR_VPARA_PTRVPR_VRPTVPR_VLVPR_VCBVPR_VCTRLVPR_VSTATUSVPR_VSPVPR_VTIDVPR_DEQSCALEVPR_VMS4_SRVPR_RPN_COR_IRVPR_LRELU_ALPHAAIC_UB_BASE_OFFSETFAST_CTX_SW_THR1FAST_CTX_SW_THR2FAST_CTX_SW_WIN_CYCFAST_CTX_SW_THR2_DISSYS_VA_BASESTACK_PHY_BASEMOV_PAD_VALVPR_SQZNVPR_ARVPR_LTNSYS_CNTSAFETY_CRC_ENSAFETY_CRC_DATASAFETY_CRC_EXCPJanuaryFebruaryMarchAprilMayJuneJulyAugustSeptemberOctoberNovemberDecemberJanFebMarAprJunJulAugSeptOctNovDecSundayMondayTuesdayWednesdayThursdayFridaySaturdaySunMonTueWedThuFriSatIOdebuginfowarningcriticaloff?26%5 -=#3 +;'WW77ww %5 -=#3 +;'WW77ww Ȩ@  $"' $error. origin_data_len is not big than origin_index non quant char, change to BYPASS mode output_len is not equal to decmp len engin decompress failedinvalid circulant matrix mode circulant matrix data is invalid.circulant matrix data check is invalid.compress_circulant_matrix failed. input len is ,and should be n * input_len is invalid: %d input_len shoud be CMP_BLOCK_SIZE*N decompress data len %d shoud not be more than output_len %d compress block data len %d shoud not be more than 64bit decompress input_len is invalid, [error] not supported head_mode quant code error!null ptr err!input_size is not multiple of fractal_sizecompress data failed! tiny mode only support tight mode tiny mode do not support CIRCLE compress default mode not support CIRCLE mode, change to BYPASS mode compress radio = tiny mode not support store offset Compress failed, change to BYPASS mode decompress data failed! St23_Sp_counted_ptr_inplaceI17VirtualBusPortTbsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEgetHwtsgetCorehwtsWriteRegisterWithAddrhwtsWrite32bitRegisterWithAddrhwtsReadRegisterWithAddrhwtsRead32bitRegisterWithAddrbusDirectReadbusDirectWritegetBusgetHwtsvwriteBinaryFilestopModelmodel_tickstartAICRiscvModelstartAIVRiscvModelmodelInitmodelSetupBusmodelSetupCoresmodelSetupSchedulerstartModel@ -+   model_api_ca.ccERROR[%s] %s:%d %s chip idx %u is too big [%s] %s:%d %s param is too big [%s] %s:%d %s core id %u is too big [%s] %s:%d %s registerValue ptr is null [%s] %s:%d %s ptr from outside is null [%s] %s:%d %s memory is null [%s] %s:%d %s infile is null [%s] %s:%d %s totalsize is too big, while totalsize = %lu, it should less than %lu %s open failed! [%s] %s:%d %s Model stopped successfully. [%s] %s:%d %s g_hwts run errors [%s] %s:%d %s core run errors [%s] %s:%d %s chip num %u is too big, while NUM_CHIP is %u [%s] %s:%d %s pc_addr is null [%s] %s:%d %s size array is null [%s] %s:%d %s Memory alloc failed %uhwtsriscvfw_aic_.elf[%s] %s:%d %s mem alloc failed hwtsvriscvfw_aiv_[%s] %s:%d %s fileName is null [%s] %s:%d %s Model config file not found. [%s] %s:%d %s Model config file: %s [%s] %s:%d %s Model setting up scheduler... [%s] %s:%d %s Model setting up bus... [%s] %s:%d %s Task scheduler failed to initialize. [%s] %s:%d %s Model bus failed to initialize. [%s] %s:%d %s Model setting up cores... [%s] %s:%d %s init errors [%s] %s:%d %s Model corec failed to initialize. [%s] %s:%d %s Configuring... =============================================================================== >>>> <<<< >>>> CA Model Init Suc <<<< [%s] %s:%d %s Parameter invalid, chip_num=%u Error: Model is already running and cannot be started. 15SlaveAccessPort8BasicBIUSt23_Sp_counted_ptr_inplaceI14BIUSlaveRDPortSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14BIUSlaveWRPortSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15BIUMasterRDPortSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15BIUMasterWRPortSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9MtePacketSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12BIUAccessReqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@            @                              @                                      ????????? ?          -+   basic_biu.ccmap::atVifu_rd_portIcache_rd_portDcache_rd_portMte_rd_portDcache_wr_portMte_wr_portBIU_rd_portBIU_wr_portWRRDN10config4cpp22ConfigurationExceptionE9BasicCoreN13ascend_spdlog5sinks4sinkEN13ascend_spdlog5sinks14ansicolor_sinkINS_7details13console_mutexEEEN13ascend_spdlog5sinks21ansicolor_stdout_sinkINS_7details13console_mutexEEESt23_Sp_counted_ptr_inplaceIN13ascend_spdlog5sinks21ansicolor_stdout_sinkINS0_7details13console_mutexEEESaIS5_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18HSetWaitEventTableSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEconfigureget_config_file@  0@P`p 0@                 @                              @                                               ( 0 8 @ H P X ` h p x        ????????? ?                      0<1>//4-. 9/90<1>//-./ 0  9< 1 > / / - . 0   /  99990<>1//-./ 004400<1>//-./ 449  : < 1 > / / - .  0   /  9  : < 1 > / / - . 0   /              0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- --@(( ((@%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./@@) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @- -(( @( (%% %@%@&& &@&@< < < =@=@>@ >@ > > 1 1 1 ) )@'' '@' ** * *@++ + +@,, , ,@    22 2 3 3@          @      0@//.@.   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0 * $  ! " # 894@)@-./@ @ ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @     99 ::;$   !!""##FGE@E JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO P@PP P Q@QQ Q RRR R SSS S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- - -(( ( (%% %@%&& &@&< < < =@=@> >@> > 1 1 1 ) )'' '' ** * *++ + +,, , ,    22 2 3  3@                   0@//.8.  8 <445 5 55 66@87@DD@3%&'(2<=>?1+756:;0 * $  ! " # 894)@- . /,  @C@@MMM MMMMMMM M M M M MM        9 9 ::;$   !!""##FGEEJJKKLL66AAA@? ??BBCCI@H N NN@N@O O OPPP P QQQ Q RRR R SSS S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                       @ @@@                                                                                                                                    B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                       -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             *ZN9BasicCore13ChangeLogPathESsbEUlSt10shared_ptrIN13ascend_spdlog6loggerEEE_%+pipe: %d, mem_id: %d, unmatched set wait ! COLORTERMTERMbasic_core.cc scalar_psq_ or tbs is nullenum_platform_typeplatform_typedavinciplatform_smmu_onl2_sizesystem_cache_sizel1.l1_switchl0.l0_switchcube.cube_switchub.ub_switchmte.mte_switchvector.aic_vec_switchvector.aiv_vec_switcharch.sc_numarch.ifu_numarch.ccu_numbiu.port_numbiu.icache_portbiu.lsu_portbiu.dcache_portbiu.read_queue_sizebiu.write_queue_sizebiu.total_queue_sizebiu.high_priority_read_portbiu.high_priority_write_portbiu.enable_memmapbiu.ipu_port_widthbiu.mte_data_sizebiu.mte_port_widthbiu.mte_read_port_numbiu.mte_write_port_numbiu.bus_port_widthbiu.read_bus_port_widthbiu.write_bus_port_widthbiu.bus_read_port_numbiu.bus_write_port_numbiu.read_buffer_depthbiu.write_buffer_depthbiu.ifu_read_queue_sizebiu.dcache_port_widthbiu.dcache_read_queue_sizebiu.dcache_write_queue_sizebiu.addr_interleave_unitbiu.vifu_read_queue_sizebiu.mem_entry_numbiu.physical_mem_entry_numbiu.is_chi_bus_infbiu.biu_esl_req_switchbuffer.aic_buffer_ini_valueddr.min_read_latencyddr.read_latency_diverddr.min_write_latencyddr.write_latency_diverl2.min_read_latencyl2.read_latency_diverl2.min_write_latencyl2.write_latency_diverddr.bandwidth_limitddr.max_credit_numl2.bandwidth_limitl2.read_bandwidth_limitl2.write_bandwidth_limitl2.max_credit_numsys.base_addrsys.min_read_latencysys.read_latency_diversys.min_write_latencysys.write_latency_diversys.bandwidth_limitsys.read_bandwidth_limitsys.write_bandwidth_limitsys.max_credit_numpsq.buffer_sizepsq.fetch_sizepsq.dispatch_sizeissue_queue.sizeissue_queue.cube_issue_queue_sizeissue_queue.vec_issue_queue_sizeissue_queue.vec_issue_queue_numissue_queue.vec_issue_ib_enableissue_queue.vec_issue_ib_sizeissue_queue.mte1_issue_queue_sizeissue_queue.mte1_issue_queue_ostd_numissue_queue.mte2_issue_queue_sizeissue_queue.mte2_issue_queue_ostd_numissue_queue.mte3_issue_queue_sizeissue_queue.mte3_issue_queue_ostd_numissue_queue.mte4_issue_queue_sizeissue_queue.mte4_issue_queue_ostd_numissue_queue.mte5_issue_queue_sizeissue_queue.mte5_issue_queue_ostd_numissue_queue.scalar_issue_queue_sizeissue_queue.event_queue_sizeissue_queue.event_queue_numissue_queue.ostd_numissue_queue.cube_issue_queue_ostd_numissue_queue.vec_issue_queue_ostd_numissue_queue.vec_issue_queue_conflictvector.scatter_portsvector.dma_versionvector.double_ctrlvector.ub_rd_wr_modevector.instr_fusionvector.new_versionvector.vcmpv_ctrlvector.vgather_block_sizevector.fp16_inf_procscalar_core.ld_st_bypass_enscalar_core.m0_stall_numscalar_core.s0_stall_numscalar_core.sys_va_base_configscalar_core.sys_va_basescalar_core.stack_phy_base_configscalar_core.stack_phy_baseub.addr_shiftub.buffer_sizeub.buffer_line_sizeub.bank_group_numberub.bank_numberub.one_line_bank_numberub.one_col_bank_numberub.support_eccl1.buffer_sizel1.buffer_bg_numl1.buffer_line_sizel1.buffer_bank_countl1.core_access_widthl1.round_robbin_switchl1.bank_cnt_per_bgl1.l1_ecc_enl1.l1_read_port_numl1.l1_write_port_numl1.l1_read_port_arbiter_switchl1.l1_read_port_weightscalar_buffer.base_addressscalar_buffer.sizescalar_buffer.ld_instr_ostdscalar_buffer.st_instr_ostdscalar_buffer.ld_st_separate_req_portscalar_buffer.ld_st_hazard_check_unitscalar_buffer.scalar_buffer_ecc_enmte.l1_read_bus_widthmte.l12l0c_max_bus_widthmte.biu_write_bus_widthmte.unibuf_write_bus_widthmte.unzip_engine_nummte.l0_write_delaymte.l1_read_delaymte.l1_write_delaymte.unibuf_write_delaymte.biu_mte_rob_slot_nummte.biu_mte_max_trans_sizemte.biu_mte_read_tagsmte.biu_mte_write_tagsmte.biu_mte_read_ostdmte.biu_mte_write_ostdmte.default_repeat_timemte.max_biu_if_trans_sizemte.max_rd_tagfifo_sizemte.lsu_biu_align_sizemte.biu_cmdgen_delaymte.reoder_buffer_switchmte.max_crdt_ue_3dmte.max_crdt_l1_ue_2dmte.max_crdt_biu_ue_2dmte.max_crdt_l1_ue_dmamte.max_crdt_biu_ue_dmamte.max_crdt_ue_unzipmte.max_crdt_ue_fmcmte.max_crdt_ue_fmdmte.max_crdt_ue_aippmte.max_crdt_ue_ksparsemte.max_crdt_ue_winogradmte.max_crdt_ue_depthwisemte.cmd_iq_arb_delay_timemte.cmd_arb_dispatch_delay_timemte.l1_read_rob_delaymte.ub_read_rob_delaymte.uzp_read_rob_delaymte.fmd_read_rob_delaymte.write_rob_delaymte.ktable_read_rob_delaymte.fmc_pad_valuemte.fmcd_engine_nummte.fmcd_head_sizemte.fmcd_mask_sizemte.fmcd_ubread_widthmte.fmcd_seg_sizemte.cube_sizemte.fmc_wdata_sizemte.fmc_write_bus_widthmte.max_fmc_uop_crdtmte.max_fmc_wheader_nummte.max_fetch_head_nummte.fmd_mte_wdata_delaymte.fmcd_header_len_unitmte.fmcd_interleave_sizemte.fmc_rdata_fifo_depthmte.min_h_resmte.max_h_resmte.byte_per_pixel_in_l1mte.y_dat_buf_sizemte.uv_dat_buf_sizemte.rgb_dat_buf_sizemte.uv_upsample_buf_sizemte.sync_buf_sizemte.csc_buf_sizemte.dtc_buf_sizemte.cpadding_buf_sizemte.pixels_per_transmte.img_dat_channelsmte.aipp_dat_buf_bubblemte.aipp_max_dtc_latmte.aipp_dtc_u8_fp16_latmte.aipp_dtc_u8_s8_latmte.pixels_per_batchmte.dma_uc_rd_sizemte.dma_dc_rd_sizemte.dma_buf_size_dcmte.dma_buf_size_ucmte.dma_pl0_ping_buf_addr_ucmte.dma_pl0_pong_buf_addr_ucmte.dma_pl1_ping_buf_addr_dcmte.dma_pl1_pong_buf_addr_dcmte.dma_pl0_ping_buf_addr_dcmte.dma_pl0_pong_buf_addr_dcmte.aipp_input_buf_bandwidthmte.unibuf_read_bus_widthmte.unibuf_trans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Failed to read in options from spec file. Exception: %s davinci_vec_core.spec[%s] %s:%d %s Core=%u, core_type=%u, spec_file=%s exec#file#[%s] %s:%d %s Core config file not found. [%s] %s:%d %s Failed to parse config file %s: %s! MTE1_READMTE3_READFIXP_READMTE3_WRITEMTE2_WRITEFIXP_WRITEvloopvloopnvpdvstopvbarvagvloopcvldvsldvgathervgatherbvldnoppldvldavzupgevbrvcivlduvnopvaddvsubvmulvmulavmaxvminvshlvshrvabsdifvadifvadd3vsadvrndvmaddvdivvselvaddreluvsubreluvmaddreluvlreluvpreluvsaddvssubvsaddsvshrivshlivrndivdupivavgvcbmaxvcbminvandvorvxorvnandvintlvvdintlvvslidevaxpyvcmpvaddsvmulsvmaxsvminsvshlsvshrsvrndsvcmpspslidepandporpxorpnandpselpintlvpdintlvvabsvclsvnegvcaddvcmaxvcminvrsqrtvsqrtvrecvlnvcpaddvbcntvreluvexpvdupsvdupvnotvmovvreducevsqzvusqzvldspvstsppldsppstspvpackvzunpackvsunpackpsetvbreakpltpltmvselrpnotvextvextfappackpunpackvdupmvfcvtvsfcvtdhist0dhist1dhist2dhist3chist0chist1chist2chist3prpnsetvintegrals1vintegrals2vintegrals3vdeqvtrcvcvtvscvtwpackwpackswpackiwaddwaddawsubwsubawmulwmulawaddsubwcvt48wmulswmulasvstvstnopvsstvscattervstuvstapstvsturvstarwfifrwfifrawfifrsDVC_PLATFORM_LINUXDVC_PLATFORM_ESLansicolorconsolecygwingnomekonsolektermlinuxmsysputtyrxvtscreenvt100xtermalacrittyvt102@ -+   BasicCrossBarBasicCrossBar13BasicCrossBarSt23_Sp_counted_ptr_inplaceI13WritePortMaskSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEbasic_cross_bar.cc[%s] %s:%d %s mem alloc size out of range [%s] %s:%d %s MakeShared mem alloc failed 15BasicCrossBarGP@ -+   basic_cross_bar_group.ccvector::_M_default_append@ -+   17BasicL0ABCrossBarbasic_l0_ab_cross_bar.ccvector::_M_fill_insertL0_AB_BufferL0_A_BufferL0_A_WINO_BufferL0_B_BufferL0_B_WINO_BufferL0_A_CrossBarL0_B_CrossBarL0_B_WINO_CrossBar{0:s} get_frac_index: error! BUFFER WRAP AROUNDset_buffer_w_req : tick: {0:d}, addr:0x{1:x}, size:0x{2:x}, start_index:{3:d}, end_index:{4:d}, port: {5:d}, buffer:{6:s}.set_buffer_r_req : tick: {0:d}, addr:0x{1:x}, size:0x{2:x}, start_index:{3:d}, end_index:{4:d}, port: {5:d}, buffer:{6:s}.set_req_complete : tick: {0:d}, addr:0x{1:x}, size:0x{2:x}, port: {3:d}, name:{4:s}.16BasicL0CCrossBarSt23_Sp_counted_ptr_inplaceIN13l0c_namespace13WritePortMaskESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN13l0c_namespace10L0CReqInfoESaIS1_ELN9__gnu_cxx12_Lock_policyE2EE@             -+   basic_l0_c_cross_bar.ccL0_C_BufferBasic_BufferL0_C_Crossbarbank_conflict_ck : tick: {0:d}, cube_bank_mask:{1:x}, fpipe_bank_mask:{2:x}, bank_conflicit:{3:x}.l0c exe_req: tick: {0:d}, port:{1:x}, req id: 0x{2:x}.l0c get write req: tick: {0:d}, port:{1:x}, addr: 0x{2:x}.l0c get read req: tick: {0:d}, port:{1:x}, addr: 0x{2:x}.l0c get read req: tick: {0:d}, port:{1:x}, addr: 0x{2:x}, conv_relu:{3:d}, elmt_len:{4:d}, is_dpf_r:{5:d}, is_shift:{6:d}, update_cube_rd_bank_mask : tick: {0:d}, cube_bank_mask:0x{1:x}, list_size: 0x{2:x}.get_fpipe_rd_bank_mask : tick: {0:d}, addr:0x{1:x}, bank_mask:0x{2:x}.get_cube_start_rd_bank : tick: {0:d}, addr:0x{1:x}, bank_mask:0x{2:x}.set_unit_flag : tick: {0:d}, addr:0x{1:x}, size:0x{2:x}, val:0x{3:x}, start_addr:0x{4:x}, instr_id:{5:d}.{0:s} get_frac_index: BUFFER WRAP AROUND start_addr: 0x{1:x}15BasicL1CrossBaruint32_t BasicL1CrossBar::computeLatency(L1AccessPorts)void BasicL1CrossBar::access_pmu(uint32_t, uint32_t)void BasicL1CrossBar::get_uop_arbiter_level(L1AccessReq&)bool BasicL1CrossBar::need_dmux(uint32_t)@ void BasicL1CrossBar::initial_arbitration()void BasicL1CrossBar::erase_record_id(uint32_t, uint32_t)void L1Request::dec_count()-+   void BasicL1CrossBar::bank_conflict_dump(std::string, uint32_t, uint32_t)bool L1Arbiter::push_arbiter(uint32_t)void BasicL1CrossBar::access_memory(uint32_t, uint32_t)L1Status::L1Status(uint32_t, uint32_t)deque::_M_new_elements_at_backdeque::_M_new_elements_at_frontbasic_l1_cross_bar.cccount > 0L1Buffertick: {0:d}, {1:s} get_read_priority, id: {2:d}tick: {0:d}, {1:s} wino_instr id: {2:d}tick: {0:d}, {1:s} read_last id: {2:d}tick: {0:d}, L1 Buffer: bank: {1:d}, bank_group: {2:d} {3:s} bank_conflict!read_readread_writewrite_writetick: {0:d}, L1_cache match: bank: {1:d}, bank_group: {2:d}, cache_addr: 0x{3:08x}, uop_addr: 0x{4:08x}!tick: {0:d}, L1 Buffer: bank: {1:d}, bank_group: {2:d} request_id: {3:d}. access!tick: {0:d}, {1:s} bank_num: {2:d}, bank_group: {3:d}, request_id: {4:d}, addr: 0x{5:08x}arbiter_switch < 318BasicSystemControlwrite@ -+   basic_system_control.ccaddr 2 spr error12BIUBasicPort14BIUSlaveRDPort15BIUMasterRDPort14BIUSlaveWRPort15BIUMasterWRPortN3fmt2v96detail9formatbufISt15basic_streambufIcSt11char_traitsIcEEEE@  0@P`p 0@            -+   void BIUMasterWRPort::esl_send_data()ca_biu_element.cctick: {0:d}. update_req_info addr: {1:x}, size: {2:x}, scache_ctrl_bit: {3:d}tick: {0:d}. {1:s}{2:d} axi_send_req 0x{3:x}.tick: {0:d}. {1:s}{2:d} complete_req 0x{3:x}.tick: {0:d}. {1:s}{2:d} axi send_data 0x{3:x}.cmd->trans_num_ > 0tick: {0:d}. {1:s}{2:d} chi_get_req 0x{3:x}.tick: {0:d}. {1:s}: {2:d} get_req 0x{3:x}tick: {0:d}. {1:s}{2:d} send_req 0x{3:x}.tick: {0:d}. {1:s}{2:d} send_data 0x{3:x}.tick: {0:d}. {1:s}{2:d} axi_get_data 0x{3:x}.tick: {0:d}. {1:s}{2:d} chi_send_req 0x{3:x}.tick: {0:d}. {1:s}: {2:d} send_req 0x{3:x}tick: {0:d}. {1:s}{2:d} req_rsp_to_slv 0x{3:x} to slv {4:x}.tick: {0:d}. {1:s}{2:d} axi up_data_to_slv 0x{3:x} to slv {4:x}.tick: {0:d}. {1:s}{2:d} axi update_data_rsp 0x{3:x} to slv {4:x}.tick: {0:d}. {1:s}{2:d} axi data_rsp 0x{3:x}.tick: {0:d}. {1:s}{2:d} chi_req_rsp 0x{3:x}.tick: {0:d}. {1:s}: {2:d} complete_req 0x{3:x}6CaCoreSt23_Sp_counted_ptr_inplaceI14BasicSequencerSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16urgent_request_tSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEvoid CaCore::vector_vl_reg_inital()@  0@P`p 0@                 @                              @                                                ( 0 8 @ H P X ` h p x        ????????? ?                      0<1>//4-. 9/90<1>//-./ 0  9< 1 > / / - . 0   /  99990<>1//-./ 004400<1>//-./ 449  : < 1 > / / - .  0   /  9  : < 1 > / / - . 0   /              0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- --@(( ((@%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./@@) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 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" # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @- -(( @( (%% %@%@&& &@&@< < < =@=@>@ >@ > > 1 1 1 ) )@'' '@' ** * *@++ + +@,, , ,@    22 2 3 3@          @      0@//.@.   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0 * $  ! " # 894@)@-./@ @ ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @     99 ::;$   !!""##FGE@E JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO P@PP P Q@QQ Q RRR R SSS S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- - -(( ( (%% %@%&& &@&< < < =@=@> >@> > 1 1 1 ) )'' '' ** * *++ + +,, , ,    22 2 3  3@                   0@//.8.  8 <445 5 55 66@87@DD@3%&'(2<=>?1+756:;0 * $  ! " # 894)@- . /,  @C@@MMM MMMMMMM M M M M MM        9 9 ::;$   !!""##FGEEJJKKLL66AAA@? ??BBCCI@H N NN@N@O O OPPP P QQQ Q RRR R SSS S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                       @ @@@                                                                                                                                    B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                       p`P@0 `@ -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             ca_core.ccunit_set_ != nullptrL0_A_WINO_CrossBar@  0@P`p 0@-+   void UBAccessRequest::mark_uop_done(uint32_t)14CAL0UBCrossBarSt23_Sp_counted_ptr_inplaceI7UB_PARASaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15UBAccessRequestSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5UBUopSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEca_l0_ub_cross_bar.ccL0_UB_Buffertick: {0:d}, buf start addr: 0x{1:x}, address: 0x{2:x}tick: {0:d}, check_vec_perf_dble, port_id: {1:d}, address: 0x{2:x}.tick: {0:d}, port: {1:x}, delay: {2:d}.tick: {0:d}, directRead port: {1:d}, size: 0x{2:x}, addr: 0x{3:x}tick: {0:d}, directWrite port: {1:d}, size: 0x{2:x}, addr: 0x{3:x}tick: {0:d}, gen_uop req_id: {1:d}, uop_id: {2:d}, bank_id: {3:d}, port_id: {4:d}, addr: 0x{5:x}, 32B_addr: 0x{6:x}.tick: {1:d}, done_req_id: {0:d}tick: {0:d}, check_wr_latency start_addr: {1:x}, 32B_addr: {2:x},size: {3:d}, bank_grp: {4:d}, port_grp: {5:d}.tick: {0:d}, blk_grp: {1:d}, bank_cf_lt: {2:d}.tick: {0:d}, wr_latency: {1:d}.tick: {6:d}, PROCESS_DATA req_id: {5:d}, at port: 0x{0:x}, address: 0x{1:x}, size: 0x{2:x}, access_type: {3:s}, scatter_number: 0x{4:x}tick: {0:d}, req_passed_conflict_check: {1:d}it != uop_map_.end()tick: {2:d}, req: {3:d} {0:s}_BANK_CONFLICT at bank: {1:d}tick: {2:d}, req: {3:d} {0:s}_PORT_CONFLICT at port: {1:d}tick: {0:d}, generate_req_id: {1:d}tick: {0:d}, gen_uop req_id: {1:d}, uop_id: {2:d}, bank_mask: {3:x}.ERROR: ub_mask size should not be larger than 512. tick: {2:d}, req: {3:d} VECTOR_{0:s}_BANK_CONFLICT at bank: {1:d}tick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}. ERR:line_size_aligned tick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}. ERR:is_same_line_type tick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}. ERR:is_addr_continstick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}. ERR:is_line_size_alignedtick: {0:d}, check_vec_perf_dble,port_id: {1:d}, is_suprt_mode1: {2:d}.8BasicCCUSt23_Sp_counted_ptr_inplaceI11BasicBufferSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          -+   basic_ccu.ccSCALAR_BUFFER10CaDispatch@ isWritePortConflict 0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          -+   ca_dispatch.ccDEBUG[%s] %s:%d %s Tick: %u, %s, Write Reg X%u: operation time. tick {0:d}: Scalar_Sqrt_Resources_Hazard.tick {0:d}: Scalar_ALU_Resources_Hazard.tick {0:d}: {1:s} Scalar_Fpu_Resources_Hazard.tick {0:d}: Scalar_Div_Resources_Hazard.tick {0:d}: isa: {1:s} dCache_before_DCCI_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} dCache_after_DCCI_Hazard. pc: {2:x}tick {0:d}: isa: {1:s} dCache_resource_Hazard - Dcache Back Pressue. pc: {2:x}tick {0:d}: isa: {1:s} I1 issue Single_Issue_Hzd or Resource_Hzd, pc: {2:x}.tick {0:d}: isa: {1:s} I1 issue Resource_Hzd, pc: {2:x}.11CaSequencerSt23_Sp_counted_ptr_inplaceI10instBinarySaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          -+   get_predict_pcput_icache_data_to_instr_bufinitca_sequencer.cctick: {0:d}, CCU update BP, br pc: 0x{1:08x}, is_branch_taken: {2:x}, pht_index: {3:x}, ghr_value: {4:x}, need_update_ghr: {5:d}.tick: {0:d}, set branch xn: 0x{1:x}[%s] %s:%d %s fetch_size_ is smaller than fetch_start_position * ISA_MAX_BYTES [%s] %s:%d %s memcpy failed, errno_t: %d. [%s] %s:%d %s MakeShared alloc failed [%s] %s:%d %s memcpy failed [%s] %s:%d %s inst binary initialize failed tick: {0:d}, fill addr: 0x{1:x} to IB: {2:d}tick: {0:d}, WAITING_FOR_ICACHE_INSTR pc: 0x{1:08x}.11PrfMapTable14ReserveStationset_occupyvoid PhyReg::dec_count()assign_physical_index@             -+   physical_reg.cc[%s] %s:%d %s Physical register %d is already occupied count >= 1[%s] %s:%d %s No more physical registers available tick: {0:d}, write physical gpr reg: {1:d}, value: {2:x}12EventQueue32checkEventsEmpty@ -+   event_queue32.cc[%s] %s:%d %s unmatched setevent: src_pipe: %s, dest_pipe: %s, event_id: %u. N7aic_vec5ldvadEN7aic_vec10vtransposeEN7aic_vec16vmovemask_xd_cmpEN7aic_vec16vmovemask_cmp_xnEN7aic_vec12rpn_cor_diagE11SubDispatchSt23_Sp_counted_ptr_inplaceI10PhyRegFileSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11PrfMapTableSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14ReserveStationSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12mte_set_flagSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13mte_wait_flagSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14cube_hset_flagSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17cube_hset_flag_xtSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15cube_hwait_flagSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18cube_hwait_flag_xtSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13scalar_ld_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13scalar_st_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10depth_wiseSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEget_mte_issq_id @ getGPRWriteCyclegetGPRReadCyclecheckIllegalInstrgetScalarGPRWriteCyclegetFlowCtrlGPRWriteCyclegetScalarGPRReadCyclegetCubeGPRReadCyclegetLsuGPRReadCyclegetFlowCtrlGPRReadCycle 0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          -+   is_flowctrl_evtque_fullgetVectorGPRCycleincCallStackCountervec_instr_set_q_idsub_dispatch.ccSCALAR ISSUE[%s] %s:%d %s DMAC_MOV_SRC_TO_DST. src L0C buffer is not a DMA instruction. This should be implemented in vector. [%s] %s:%d %s DMAC_MOV_SRC_TO_DST. src_ID is invalid. [%s] %s:%d %s SET_2D. dst_ID is invalid. [%s] %s:%d %s Invalid DMA inst name. SCALARVECTORCUBEMTE1MTE2MTE3ALLMTE4MTE5VECTOR_V2TypeFLOWCTRLunknown instr type:[%s] %s:%d %s Invalid Opcode Type. [%s] %s:%d %s Do not support writing spr: %lu. Instr: pc: %lx, binary: %x. [%s] %s:%d %s Do not support reading spr: %lu. Instr: pc: %lx, binary: %x. [%s] %s:%d %s Invalid OP1. [%s] %s:%d %s Invalid OP. [%s] %s:%d %s Invalid OP1. pc: 0x%lx tick {0:d}: flowctrl: {1:s} DMAC_L1_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} DMAC_L2_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} DMAC_L3_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} DMAC_L4_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} DMAC_L5_EVENT_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} VECTOR_EVENT_QUEUE0_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} VECTOR_EVENT_QUEUE1_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} CUBE_EVENT_QUEUE_FULL. pc: {2:x}[%s] %s:%d %s ALL_PIPE should exist only in FLOWCTR_BAR unknown flowctrl pipetick {0:d}: flowctrl: {1:s} DMAC_L1_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} DMAC_L2_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} DMAC_L3_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} DMAC_L4_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} DMAC_L5_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} VECTOR_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: flowctrl: {1:s} CUBE_ISSUE_QUEUE_FULL. pc: {2:x}tick {0:d}: isa: {1:s} SPR RAW stall. pc: {2:x}.tick {0:d}: isa: {1:s} SPR WAW stall. pc: {2:x}.tick {0:d}: I1 set ctrl spr single issue hazard: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte1 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte2 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte3 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte4 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to mte5 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to vector issque 0 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to vector issque 1 instr: {1:s}, pc: {2:x}.tick {0:d}: attach barrier instr to cube instr: {1:s}, pc: {2:x}.MTE3 ISSUEMTE4 ISSUEMTE2 ISSUEMTE5 ISSUEtick {0:d}: discard mte1 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte1 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard mte2 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte2 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard mte3 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte3 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard mte4 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte4 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard mte5 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: mte5 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard vector issque 0 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: vector issque 0 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard vector issque 1 barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: vector issque 1 barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: discard cube barrier instr: {1:s}, pc: {2:x} because barrier instr already at import of queue.tick {0:d}: cube barrier instr: {1:s}, pc: {2:x} attach at import of queue.tick {0:d}: branch isa: {1:s}, pc: {2:x} execute update predictortick {0:d}, MTE34 ISSQUE SINGLE PORT HZD, isa: {1:s}, pc: {2:x}.tick {0:d}, MTE25 ISSQUE SINGLE PORT HZD, isa: {1:s}, pc: {2:x}.tick {0:d}: isa: {1:s} slot1 cond_flag get SKEW, pc: {2:x}.tick {0:d}: I1 condition_flag hzd: {1:s}. pc: {2:x}tick {0:d}: push mte1 isa: {1:s} to queue, pc: {2:x}.tick {0:d}: d1 scalar bar wait: {1:s}, pc: {2:x}.tick {0:d}: unsupported bar.s instruction : {1:s}, pc: {2:x}. treated as a NOP instructiontick {0:d}: I1 scalar dsb stall, isa: {1:s}, pc: {2:x}.tick {0:d}: push isa: {1:s} mov_xd_status_pre_barrier_all. tick {0:d}: push isa: {1:s} mte_mov_xd_spr_barrier. tick {0:d}: push isa: {1:s} scalar_mov_xd_spr_barrier. tick {0:d}: scalar I1 stage dsb/wait_flag/wfe stall. isa: {1:s}, pc: {2:x}tick {0:d}: branch isa: {1:s}, pc: {2:x} execute ret instr, next_pc: {3:x}, destAddr: {4:x}.tick {0:d}: branch isa: {1:s}, pc: {2:x} execute jump instr, next_pc: {3:x}, destAddr: {4:x}.tick {0:d}: branch isa: {1:s}, pc: {2:x} execute flush, next_pc: {3:x}, destAddr: {4:x}.tick {0:d}: push mte1 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte2 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte3 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte4 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push mte5 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push vector0 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push vector1 isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: push cube isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}CCU: {0:s}: BS9SX1AA_illegal_instr. Instruction Binary is wrong: pc: {1:x}, binary: {2:x}.[%s] %s:%d %s call stack overflow, nested call number %d is larger than threshold: %u. CCU: {0:s}: ccu_call_depth_ovrflw. Nested calls more than T+1. pc: {1:x}CCU: {0:s}: ccu_addr_err. Scalar ld/st addr overflow/unalign error. pc: {1:x}[%s] %s:%d %s vpipe_value: %lu. num_vec_isq_: %u. pc: %lx, binary: %x. tick {0:d}: push pushQ isa: {1:s} to sequencer, pc: {2:x}. event_id: {3:d}unknown mte issque type:tick {0:d}: push vector isa: {1:s} to queue, pc: {2:x}. event_id: {3:d}tick {0:d}: isa: {1:s} RAW stall. pc: {2:x}, src_reg: {3:d}.tick {0:d}: isa: {1:s} alu slot1 get SKEW, pc: {2:x}, src_reg: {3:d}.tick {0:d}: isa: {1:s} alu get lsu SKEW. pc: {2:x}, src_reg: {3:d}.tick {0:d}: isa: {1:s} st get ld BYPASS. pc: {2:x}, src_reg: {3:d}.tick {0:d}: fpu isa: {1:s} fp OVERWRITE, pc: {2:x}, src_reg: {3:d}.tick {0:d}: alu isa: {1:s} alu slot1 OVERWRITE, pc: {2:x}, src_reg: {3:d}.tick {0:d}: alu isa: {1:s} multicycle OVERWRITE, pc: {2:x}, src_reg: {3:d}.tick {0:d}: isa: {1:s} WAW stall. pc: {2:x}, dst_reg: {3:d}.tick {0:d}: add spr commit table, spr binary: {1:d}. isa: {2:s}, pc: {3:x}.tick {0:d}: add xd commit table, xd: {1:d}. isa: {2:s}, pc: {3:x}.tick {0:d}: del spr commit table, binary: {1:d}.tick {0:d}: del xd commit table, xd: {1:d}.tick {0:d}: del xd commit table fail (multicycle instr xd overwrite), xd: {1:d}.tick {0:d}: push slot {1:d} scalar isa to scalar unit: {2:s}, pc: {3:x}.tick {0:d}: Update register: Buf_type_: {1:d} reg: x{2:d} value: 0x{3:x} reg_port_use: {4:d} reg_value_map_.size: {5:d} tick {0:d}: CCU_I1 ld_hit_st_bypass, isa: {1:s}, pc: {2:x}, src_reg: x{3:d}, skew_gpr_value: 0x{4:x}.tick {0:d}: CCU_I1 ld_miss_st_bypass, isa: {1:s}, pc: {2:x}, src_reg: x{3:d}, skew_gpr_value: 0x{4:x}.tick {0:d}: set divide_0 ld_st_bypass. isa: {1:s}, pc: {2:x}.tick {0:d}: set divide_1 ld_st_bypass. isa: {1:s}, pc: {2:x}.tick {0:d}: push scalar ldst divide_0 and divide_1 to lsu unit. isa: {1:s}, pc: {2:x}.tick {0:d}: push scalar ldst to lsu unit. isa: {1:s}, pc: {2:x}.tick {0:d}: push slot {1:d} flowctrl isa to scalar unit: {2:s}, pc: {3:x}.tick {0:d}: isa: {1:s} the instruction is not support by v200e scalar core. pc: {2:x}.tick {0:d}: branch isa: {1:s}, pc: {2:x} execute call instr, next_pc: {3:x}, destAddr: {4:x}.tick {0:d}: CCU d1 wait flush, not to send instr to I1tick {0:d}: CCU d1 wait set loop instr retire, not to send instr to I1tick {0:d}: CCU_d1_detect_ISA: {1:s} type: {2:x}. pc: {3:x} tick {0:d}: push error instr to error_instr_queue. ISA: {1:s} type: {2:x}. pc: {3:x} tick {0:d}: push d1 to I1 in-order success. ISA: {1:s} type: {2:x}. pc: {3:x} tick {0:d}: push d1 to I1 in-order fail. ISA: {1:s} type: {2:x}. pc: {3:x} tick {0:d}, {1:s} QUEUE FULL, isa: {2:s}, pc: {3:x}.tick {0:d}: I1 scalar wait_flag stall, isa: {1:s}, pc: {2:x}. event_id: {3:d}tick {0:d}: d1 scalar exe scalar set flag: {1:s}, pc: {2:x}, event_id: {3:d}.error execute.tick {0:d}: push {1:s} isa: {2:s} to queue, pc: {3:x}.tick {0:d}: I1 branch unit issue condflag_hzd_ hazard: {1:s}, pc: {2:x}.unknown flowctrl opcode nametick {0:d}: isa: {1:s} branch limit one instr issue. pc: {2:x}.tick {0:d}: CCU_I1 lsu_to_alu_skew STALL.tick {0:d}: CCU_I1_detect_ISA: {1:s} type: {2:x}. pc: {3:x} 12SubSequencerSt23_Sp_counted_ptr_inplaceI3ISASaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11error_instrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEstart@ fillinitSubSequencer 0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          -+   fetchpass2dispatchsub_sequencer.ccthis->icache_ is null[%s] %s:%d %s req is nullptr tick: {0:d}, clear_ifu_read_req_queuetick: {0:d}, clear_is_branchtick: {0:d}, set_is_branchtick: {0:d}, fetch addr: 0x{1:x}, buf_ptr: 0x{2:x}CCU: {0:s}: ccu_cnt_err. loopend detected without loop instr. pc: {1:x}CCU: {0:s}: ccu_loop_cnt_error. loop count == 0 when execute loopend instruction. pc: {1:x}scalar_psq: Instruction Address 0x. pass 2 psq2dispath_queue.parseConfigFilesetupIndependentOptionsdvcConfig.cc[%s] %s:%d %s create config failed, file name is %s [ERROR]: Failed to parse config file %s! %s dump.dump_l0a_rd_statusdump.dump_l0a_wr_statusdump.dump_l0b_rd_statusdump.dump_l0b_wr_statusdump.dump_l0c_rd_statusdump.dump_l0c_wr_statusdump.dump_ub_rd_statusdump.dump_ub_wr_statusdump.dump_l1_rd_statusdump.dump_l1_wr_status[%s] %s:%d %s parseConfigFile failed, file name is %s [%s] %s:%d %s readinOptionsFromCfg failed 9CubeIssueSt23_Sp_counted_ptr_inplaceI7CubeISASaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@             -+   cube_issque.ccCUBE ISSUE8LsuIssue@             -+   lsu_issque.ccLSU ISSUE11ScalarIssueSt15_Sp_counted_ptrIP9ScalarISALN9__gnu_cxx12_Lock_policyE2EE@             -+   scalar_issque.cc16VecIssQueArbiter@             -+   vector_arbiter.cctick: {0:d}, vector isq_ib_: {1:d}, front_isq_counter_: {2:d} [{0:08d}]({1:s}): vec arb pop instr_id: {2:d}, isa: {3:s}, pc: {4:x}, from vec queue 0[{0:08d}]({1:s}): vec arb pop instr_id: {2:d}, isa: {3:s}, pc: {4:x}, from vec queue 1[{0:08d}]({1:s}): get_next_instr, isa: {2:s}, pc: {3:x}[{0:08d}]({1:s}): retire instr_id: {2:d}, thread_id: {3:d}[{0:08d}]({1:s}): get_instr_after_next instr_id: {2:d}, isa: {3:s}, pc: {4:x}11VectorIssue@             -+   vector_issque.ccVECTOR ISSUE17VirtualBusPortTbsaicpu_kickstartdirectReaddirectWritebus_memory_dup@ initinitinit 0@P`p 0@                 @                              @                                                ( 0 8 @ H P X ` h p x        ????????? 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" # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @- -(( @( (%% %@%@&& &@&@< < < =@=@>@ >@ > > 1 1 1 ) )@'' '@' ** * *@++ + +@,, , ,@    22 2 3 3@          @      0@//.@.   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0 * $  ! " # 894@)@-./@ @ ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @     99 ::;$   !!""##FGE@E JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO P@PP P Q@QQ Q RRR R SSS S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- - -(( ( (%% %@%&& &@&< < < =@=@> >@> > 1 1 1 ) )'' '' ** * *++ + +,, , ,    22 2 3  3@                   0@//.8.  8 <445 5 55 66@87@DD@3%&'(2<=>?1+756:;0 * $  ! " # 894)@- . /,  @C@@MMM MMMMMMM M M M M MM        9 9 ::;$   !!""##FGEEJJKKLL66AAA@? ??BBCCI@H N NN@N@O O OPPP P QQQ Q RRR R SSS S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                       @ @@@                                                                                                                                    B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                       p`P@0 `@ -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             virtual_bus_slave_port.cc[%s] %s:%d %s AICPU core %lu will run %lu cycle [%s] %s:%d %s AIC or AIV request at address 0x%lx [%s] %s:%d %s AICPU request at address 0x%lx [%s] %s:%d %s Write value to hwts0 register 0x%lx, value 0x%lx [%s] %s:%d %s Write value to hwts0 register 0x%lx, incorrect size %u [%s] %s:%d %s Write value to hwts1 register 0x%lx, value 0x%lx [%s] %s:%d %s Write value to hwts1 register 0x%lx, incorrect size %u [%s] %s:%d %s mem alloc size out of range! bus write: smmu_master_id: 0x smmu_flag: 0xbus read: smmu_master_id: 0x[%s] %s:%d %s init failed 8AsyncRAMSt23_Sp_counted_ptr_inplaceI6SC_DDRSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEdirect_readdirect_writeinit_with_seedinit_without_seedreadwritetickasync_ram.cc[%s] %s:%d %s read error DDR latency random seed = [%s] %s:%d %s write error 7BarSync@ -+   bar_sync.cc10EventQueue@ -+   event_queue.cc17IssueQueueArbiter@             -+   isq_arbiter.cc[{0:08d}]({1:s}): emplace instr_id: {2:d}, isq_id: {3:d}[{0:08d}]({1:s}): retire instr_id: {2:d}, isq_id: {3:d}10IssueQueueSt23_Sp_counted_ptr_inplaceI9set_eventSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10wait_eventSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ resume                 -+   issue_queue.ccL1L2L3L4L5FIXPIPEVEC ISSUEVECTOR Repeat0VEC0 ISSUEVEC1 ISSUEVEC0 IB ISSUEVEC1 IB ISSUEMTE1 ISSUEMTE1 Repeat0MTE2 Repeat0MTE3 Repeat0MTE4 Repeat0MTE5 Repeat0CUBE Repeat0SCALAR Repeat0FIXPIPE ISSUEFIXPIPE Repeat0undefine pipe Repeat0[%s] %s:%d %s ERROR: issue_queue.cc: wait_event_inst == nullptr tick: {0:d} {1:s} translate VSET_FLAG instr to {2:s}, Pipe: {3:s}, triggerPipe: {4:s}, event_id: {5:d}tick: {2:d} issq trigger l0c_set_flag {0:s} l0c_opt_id: {1:d} triggerPipe: {3:s}tick: {3:d} issq_exe_set_flag {0:s} l0c_opt_front_id: {1:d} triggerPipe: {2:s}, reorder_q_id: {3:d}tick: {0:d} {1:s} translate VSET_EVENT instr to {2:s}, Pipe: {3:s}, triggerPipe: {4:s}, event_id: {5:d}tick: {0:d} {1:s} translate VWAIT_FLAG instr to {2:s}, Pipe: {3:s}, triggerPipe: {4:s}, event_id: {5:d}tick: {0:d} isa: {1:s}, pc: {2:x} has update set flag table hazardtick: {0:d} isa: {1:s}, pc: {2:x} has vector issque single-port ram hazardtick: {0:d} isa: {1:s}, pc: {2:x} has MTE issque single-port ram hazardN13ascend_spdlog5sinks16stdout_sink_baseINS_7details17console_nullmutexEEEN13ascend_spdlog5sinks11stdout_sinkINS_7details17console_nullmutexEEEN13ascend_spdlog5sinks9base_sinkINS_7details10null_mutexEEEN13ascend_spdlog5sinks15basic_file_sinkINS_7details10null_mutexEEESt23_Sp_counted_ptr_inplaceIN13ascend_spdlog5sinks11stdout_sinkINS0_7details17console_nullmutexEEESaIS5_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN13ascend_spdlog5sinks15basic_file_sinkINS0_7details10null_mutexEEESaIS5_ELN9__gnu_cxx12_Lock_policyE2EEerror : @ -+   /initial_aicore_logabFailed opening file for writingFailed writing to file Failed flush to file {}{}log.ccSCALAR_PIPEVECTOR_PIPECUBE_PIPEDMAC_L1_PIPEDMAC_L2_PIPEDMAC_L3_PIPEUNKNOWNAddress {0:08x} = [{1:02x}]Address {0:08x} = [{1:04x}]memcpy_s error!Address {0:08x} = [{1:08x}] Address {2:08x} = [{3:08x}] Address {4:08x} = [{5:08x}] Address {6:08x} = [{7:08x}]Address {0:08x} = [{1:08x}] Address {2:08x} = [{3:08x}] Address {4:08x} = [{5:08x}]Address {0:08x} = [{1:08x}] Address {2:08x} = [{3:08x}]Address {0:08x} = [{1:08x}][{0:08d}](PC: 0x{1:08x})@{2:s} : (Binary: 0x{3:08x}) {4:s}/core.dump.1.dump.2.dump[%l] %v16MasterAccessPort@ -+   master_access_port.cc3RAMclearreadwriteiniValRAMiniValRAMram.cc[%s] %s:%d %s memset_s error %d [%s] %s:%d %s memcpy_s error %d [%s] %s:%d %s read address: 0x%x is larger than ddr size: 0x%x [%s] %s:%d %s write address: 0x%x is larger than ddr size: 0x%x read_in_pagewrite_in_page//------------------------------------------------------------------ N/Asc_buf.cc[%s] %s:%d %s addr is not same page of addr end N7aic_vec9VectorISAEN7aic_vec21vector_mov_xd_specialEN7aic_vec21vector_mov_special_xnEN7aic_vec17copy_bufC2unifiedEN7aic_vec17copy_unifBuf2bufCEN7aic_vec20copy_unifBuf2unifBufEN7aic_vec12brc_ub_2_dstEN7aic_vec6movevaEN7aic_vec8movemaskEN7aic_vec14vector_op_2srcEN7aic_vec14vector_op_1srcEN7aic_vec18vector_vad_op_2srcEN7aic_vec18vector_vad_op_1srcEN7aic_vec19vector_auxiliary_opEN7aic_vec21vector_opticalflow_opEN7aic_vec14vector_obj_detEN7aic_vec7col2imgEN7aic_vec12l0c_lock_setEN7aic_vec16l0c_lock_releaseEdecodedecodedecodedecodedecodedecodedecodeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializedecode@  0@P`p 0@                           0<1>//4-. 9/90<1>//-./ 0  9< 1 > / / - . 0   /  99990<>1//-./ 004400<1>//-./ 449  : < 1 > / / - .  0   /  9  : < 1 > / / - . 0   /              0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- --@(( ((@%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./@@) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @- -(( @( (%% %@%@&& &@&@< < < =@=@>@ >@ > > 1 1 1 ) )@'' '@' ** * *@++ + +@,, , ,@    22 2 3 3@          @      0@//.@.   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0 * $  ! " # 894@)@-./@ @ ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @     99 ::;$   !!""##FGE@E JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO P@PP P Q@QQ Q RRR R SSS S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- - -(( ( (%% %@%&& &@&< < < =@=@> >@> > 1 1 1 ) )'' '' ** * *++ + +,, , ,    22 2 3  3@                   0@//.8.  8 <445 5 55 66@87@DD@3%&'(2<=>?1+756:;0 * $  ! " # 894)@- . /,  @C@@MMM MMMMMMM M M M M MM        9 9 ::;$   !!""##FGEEJJKKLL66AAA@? ??BBCCI@H N NN@N@O O OPPP P QQQ Q RRR R SSS S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                       @ @@@                                                                                                                                    -+   decodeaic_vector_isa.cc[%s] %s:%d %s special errors [%s] %s:%d %s special encode errors [%s] %s:%d %s xd errors [%s] %s:%d %s xn errors [%s] %s:%d %s MOV number of burst can't be 0 [%s] %s:%d %s vector_isa.cc: dest_addr = 0x%x is not 16 Byte aligned. [%s] %s:%d %s vector_isa.cc: dest_addr = 0x%x is not 32 Byte aligned. [%s] %s:%d %s vector_isa.cc: src_addr = 0x%x is not 32 Byte aligned. [%s] %s:%d %s vector_isa.cc: src1_addr = 0x%x is not 32 Byte aligned. [%s] %s:%d %s dest_addr = %x address align error! %s( x[%ld]= 0x%lx, %s= 0x%lx,)[%s] %s:%d %s sprintf_s failed, return value: %d. %s(%s= 0x%lx, x[%ld]= 0x%lx)%s(num_block: %u, num_burst: %u, burst: %u, dest_addr: 0x%x, src_addr: 0x%x, stride: %u, dst_stride: %u, conv : %u, srcID3: %u, srcID1: %u, xm_val: 0x%lx)%s(num_block: %u, num_burst: %u, burst: %u, num_block_remain: %u, dest_addr: 0x%x, src_addr: 0x%x, stride: %u, dst_stride: %u, conv: %u, dstID: %u, xm_val: 0x%lx%s(num_block: %u, num_burst: %u, burst: %u, dest_addr: 0x%x, src_addr: 0x%x, stride: %u, dst_stride: %u, conv: %u, xm_val: 0x%lx%s(num_block: %u, num_burst: %u, burst: %u, dest_addr: 0x%x, src_addr: 0x%x, stride: %u, dst_stride: %u, conv: %u, dstID: %u, xm_val: 0x%lx)%s(num_block: %u, Vad: %u, src_addr: 0x%x, src1_addr: 0x%x, element_id: %u)%s(op0: %u, op1: %u, op2: %u, type: %u, dest_addr: 0x%x, src_addr: 0x%x, dst_stride: %u, src_stride: %u, reg: %u, h0: %u, xt_val: 0x%lx)%s(op0: %u, op1: %u, op2: %u, type: %u, dest_addr: 0x%x, src_addr: 0x%x, dst_stride: %u, src_stride: %u, reg: %u, h0: %u, repeat: %u, xt_val: 0x%lx)%s(op0: %u, op1: %u, op2: %u, type/convType: %u, repeat: %u, dest_addr: 0x%x, src1_addr: 0x%x, src_addr: 0x%x, dst_stride: %u, src_stride: %u, dst_rep_stride: %u, src_rep_stride: %u, reg: %u, h0: %u, xt_val: 0x%lx)%s(op0: %u, op1: %u, op2: %u, convType: %u, repeat: %u, dest_addr: 0x%x, src_addr: 0x%x, dst_stride: %u, src_stride: %u, dst_rep_stride: %u, src_rep_stride: %u, reg: %u, h0: %u, xt_val: 0x%lx)%s(op0: %u, op1: %u, op2: %u, conv_depth_type: %u, repeat: %u, dest_addr: 0x%x, src_addr: 0x%x, dst_stride: %u, src_stride: %u, dst_rep_stride: %u, src_rep_stride: %u, reg: %u, xt_val: 0x%lx.)%s(op0: %u, op1: %u, op2: %u, type/convType: %u, repeat: %u, dest_addr: 0x%x, src_addr: 0x%x, dst_stride: %u, src_stride: %u, dst_rep_stride: %u, src_rep_stride: %u, reg: %u, h0: %u)%s(op0: %u, op1: %u, op2: %u, type/convType: %u, repeat: %u, dest_addr: 0x%x, src_addr: 0x%x, dst_stride: %u, src_stride: %u, dst_rep_stride: %u, src_rep_stride: %u, reg: %u, h0: %u, xt_val: 0x%lx)%s(op0: %u, op1: %u, op2: %u, type: %u, repeat: %u, dest_addr: 0x%x, src_addr: 0x%x, src1_addr: 0x%x, dst_stride:0x%x, src_stride: %u, src1_stride: %u, dst_rep_stride:0x%x, src_rep_stride: %u, src1_rep_stride: %u, reg: %u, h0: %u, xt_val: 0x%lx.)%s(op0: %u, op1: %u, op2: %u, type/convType: %u, repeat: %u, Vad: %u, Van: %u, src1_addr: 0x%x, Vad_stride: %u, Van_stride: %u, reg: %u, h: %u, xt_val: 0x%lx)%s(op0: %u, op1: %u, op2: %u, type/convType: %u, repeat: %u, Vad: %u, Van: %u, Vad_stride: %u, Van_stride: %u, reg: %u, h: %u)%s(op0: %u, op1: %u, op2: %u, type/convType: %u, repeat: %u, Vad: %u, Van: %u, Vad_stride: %u, Van_stride: %u, reg: %u, h: %u, xt_val: 0x%lx)%s(op0: %u, op1: %u, op2: %u, type: %u, repeat: %u, Vad: %u, Vam: %u, Van: %u, Vad_stride: %u, Vam_stride: %u, Van_stride: %u, reg: %u, h0: %u, xt_val: 0x%lx)%s(op0 %u op1 %u type %u repeat: %u, Van: %u, dest_addr: 0x%x, xt_val: %lx, M: %u, N: %u)%s(op0 %u op1 %u type %u repeat: %u, src_addr: 0x%x, Vad: %u, xt_val: %lx, M: %u, N: %u)%s(op0 %u op1 %u type %u repeat: %u, Van: %u, Vad: %u, Van_stride: %u, Vad_stride: %u, M: %u, N: %u, xt_val: %lx)%s(op0 %u op1 %u type %u repeat: %u, src_addr: 0x%x, src1_addr: 0x%x, dest_addr: 0x%x, src_stride: %u, src1_stride: %u, dst_stride: %u, reg_type: %u, h0: %u, xt_val: %lx)col2img%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx)%s(op0 %u op1 %u type %u repeat: %u, xn_val: %lx, dest_addr: 0x%x, xt_val: %lx)%s(op0 %u op1 %u type %u repeat: %u, src_addr: 0x%x, src1_addr: 0x%x, dest_addr: 0x%x, src_stride: %u, src1_stride: %u, dst_stride: %u, reg_type: %u, h0: %u,)%s(op0 %u op1 %u type %u repeat: %u, Van: %u, dest_addr: 0x%x, M: %u, N: %u, Nd: %u, xt_val: %lx)%s(op0 %u op1 %u type %u repeat: %u, src_addr: 0x%x, Vad: %u, M: %u, N: %u, Nd: %u, xt_val: %lx)%s(op0 %u op1 %u type %u repeat: %u, Van: %u, Vad: %u, xt_val: %lx, Van_stride: %u, Vad_stride: %u, M: %u, N: %u)%s(op0 %u op1 %u type %u repeat: %u, src_addr: 0x%x, src1_addr: 0x%x, dest_addr: 0x%x, src_stride: %u, src1_stride: %u, dst_stride: %u, reg_type: %u, h0: %u)%s%s(num_block: %u, mask: %u, X%d: 0x%lx)vector_mov_xd_specialvector_mov_special_xn[%s] %s:%d %s Xn address is not 32B aligned = 0x%x. [%s] %s:%d %s Xm address is not 32B aligned = 0x%x. [%s] %s:%d %s Xd address is not 32B aligned = 0x%x. [%s] %s:%d %s Xn address is not 4B aligned = 0x%x. [%s] %s:%d %s Xm address is not 2B i.e. fp16 aligned = 0x%x. [%s] %s:%d %s Xd address is not 2B i.e. fp16 aligned = 0x%x. copy_bufC2unifiedcopy_unifBuf2bufCcopy_unifBuf2unifBufbrc_ub_2_dstmovevamovemaskvector_op_1srcvector_op_2srcvector_vad_op_1srcvector_vad_op_2srcvector_opticalflow_opvector_obj_detvector_auxiliary_opl0c_lock_setl0c_lock_release{:s}:{:d}:{:s} Could not recognize the isa encoding for type! {:s}:{:d}:{:s} Could not recognize the isa encoding! {:s}:{:d}:{:s} B8, M is not multiple of 4! {:s}:{:d}:{:s} B8, M is not even number! {:s}:{:d}:{:s} fp16, M is not even number! {:s}:{:d}:{:s} fp16 dosen't support N=32 ! 7CubeISA4mmad19cube_mov_special_xn15depth_wise_conv14cube_conv_calc13winograd_conv14cube_hset_flag15cube_hwait_flag17cube_hset_flag_xt18cube_hwait_flag_xtcheck_addr_aligncheck_addr_aligndecodeexecuteserializeserializeserializeserializeserializeserializeserializeserializeserialize@              -+   cube_isa.cc[%s] %s:%d %s Xn_val = %lx address align error! [%s] %s:%d %s Xm_val = %lx address align error! [%s] %s:%d %s Xd_val = %lx address align error! [%s] %s:%d %s instruction execute errors %s(type: %u, xd: 0x%x, xn: 0x%x, xm: 0x%x, xt: 0x%x, M:%u, K:%u, N:%u, xd_val: 0x%lx, xn_val: 0x%lx, xm_val: 0x%lx, xt_val: 0x%lx, c_ctrl: %u, sparsity: %u, w_offset: %u, fm_offset: 0x%x, small_K: %u, sMask_addr: 0x%x, wino_a: %u, wino_b: %u, s10_en: %u, unit_flag: %u)instr ID is: %lu%s(%s= 0x%lx, x[%ld]= 0x%lx)instr ID is: %lu%s(type: %u, xd: 0x%x, xn: 0x%x, xm: 0x%x, xt: 0x%x, H: %u, W: %u, W_start: %u, W_ext: %u, relu: %u, xd_val: 0x%lx, xn_val: 0x%lx,xm_val: 0x%lx, xt_val: 0x%lx, sMask_addr: %u, fm_offset: %u, w_offset: %u, padding_ctrl: %u, #h: %u, unit_flag: %u, instr ID is: %lu%s(type: %u, xd: 0x%x, xn: 0x%x, xm: 0x%x, xt: 0x%x, ch_size:%u, M:%u, K:%u, N:%u, xd_val: 0x%lx, xn_val: 0x%lx, xm_val: 0x%lx, xt_val: 0x%lx, accu_mode: %u, fm_offset: 0x%x, sMask_addr: 0x%x, w_offset: 0x%x) instr ID is: %lu%s(type: %u, xd: 0x%x, xn: 0x%x, xm: 0x%x, xt: 0x%x, M:%u, K:%u, N:%u, xd_val: 0x%lx, xn_val: 0x%lx, xm_val: 0x%lx,xt_val:0x%lx, smask_addr:0x%x, weight_ctrl: %u, accu_mode: %u, unit_flag: %u) instr ID is: %lu%s(pipe: %u, trigger pipe: %u, v: %u, mem: %u, event id: %u) instr ID is: %lu%s(pipe: %u, trigger pipe: %u, v: %u, mem: %u, event id: %u, xt_index: %u) instr ID is: %lummadcube_mov_special_xndepth_wise_convcube_conv_calcwinograd_convcube_hset_flagcube_hwait_flagcube_hset_flag_xtcube_hwait_flag_xt11FlowCtrlISA4jump5jumpc5jumpr7preload4call5callr7bar_set8bar_wait3ret4trap4loop9set_event10wait_event7barrier8nop_pipe7endloop3nop13end_execution10break_inst4adrp3dsb3wfe9hset_flag10hwait_flag11error_instr7jumpcmpdecodedecodedecodedecodeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserialize@ decodeexecute 0@P`p 0@            -+   flowctrl_isa.cc[%s] %s:%d %s set_event data type is wrong. [%s] %s:%d %s hset_flag data type is wrong. %sx (dest_address:0x%lx)%si (dest_address:0x%lx)%s (dest_address:0x%lx)%sx (dest_address:0x%lx, conditional_flag:%lx)%si (dest_address:0x%lx, conditional_flag:%lx)%sx (preload address: 0x%lx)%sx (event_id:0x%lx)%si(event_id:0x%lx)%s (loop_cnt: %ld)%s (loop count: %ld)%s(pipe_type: %s)%s(pipe_type: %s, tigger_pipe: %s, event_id: %hu)%s (dest_address:0x%lx, conditional_flag:%lx)%s(pipe_type: %s, tigger_pipe: %s, event_id: %hu, virtual_flag: %hu, mem_type: %hu.)ERROR: data type is wrong.ERROR: loop date_type_ is undefined.jumpjumprjumpcpreloadcallcallrbar_setbar_waitadrpend_executionrettraploopendloopbarrierset_eventwait_eventnop_pipenopjumpcmphset_flaghwait_flagdsbwfebreak_insterror_instrERROR: jump data type is wrong.ERROR: jumpc data type is wrong.ERROR: call data type is wrong.[%s] %s:%d %s cmp_dtype errors [%s] %s:%d %s cmp_optype errors [%s] %s:%d %s imm10 errors [%s] %s:%d %s imm5 errors [%s] %s:%d %s xn_4_1 errors [%s] %s:%d %s xn_0_0 errors [%s] %s:%d %s xm errors [%s] %s:%d %s jump_type errors [%s] %s:%d %s cmp_type errors $& ".   extractget_scalar_opcode_type@ get_vector_opcode_typeget_dmac_opcode_typeISAISA                 -+ instantiate_vector_dmac_isa  St23enable_shared_from_thisI3ISAE3ISAN7aic_vec6vmovevEN7aic_vec3vciEN7aic_vec4vaddEN7aic_vec8vadd_vadEN7aic_vec12vaddreluconvEN7aic_vec8vaddreluEN7aic_vec4vsubEN7aic_vec8vsub_vadEN7aic_vec12vsubreluconvEN7aic_vec8vsubreluEN7aic_vec4vmaxEN7aic_vec8vmax_vadEN7aic_vec4vminEN7aic_vec8vmin_vadEN7aic_vec4vmulEN7aic_vec8vmul_vadEN7aic_vec4vmlaEN7aic_vec8vmla_vadEN7aic_vec5vmaddEN7aic_vec9vmadd_vadEN7aic_vec6vlreluEN7aic_vec9vmaddreluEN7aic_vec13vmaddrelu_vadEN7aic_vec4vexpEN7aic_vec8vexp_vadEN7aic_vec6vrsqrtEN7aic_vec10vrsqrt_vadEN7aic_vec5vsqrtEN7aic_vec9vsqrt_vadEN7aic_vec5vreluEN7aic_vec9vrelu_vadEN7aic_vec4vrecEN7aic_vec8vrec_vadEN7aic_vec3vlnEN7aic_vec8vrln_vadEN7aic_vec4vabsEN7aic_vec8vabs_vadEN7aic_vec4vdivEN7aic_vec8vdiv_vadEN7aic_vec5vcaddEN7aic_vec5vcmaxEN7aic_vec5vcminEN7aic_vec6vcgmaxEN7aic_vec6vcgminEN7aic_vec6vcgaddEN7aic_vec13vncwhconv_vadEN7aic_vec8v4dtransEN7aic_vec5vaxpyEN7aic_vec9vaxpy_vadEN7aic_vec5vaddsEN7aic_vec9vadds_vadEN7aic_vec5vmulsEN7aic_vec9vmuls_vadEN7aic_vec5vmaxsEN7aic_vec9vmaxs_vadEN7aic_vec5vminsEN7aic_vec9vmins_vadEN7aic_vec4vcmpEN7aic_vec8vcmp_vadEN7aic_vec5vcmpvEN7aic_vec4vselEN7aic_vec8vsel_vadEN7aic_vec5vconvEN7aic_vec9vconv_vadEN7aic_vec8vmov_vadEN7aic_vec6vcpaddEN7aic_vec4vandEN7aic_vec3vorEN7aic_vec4vnotEN7aic_vec11vadddeqreluEN7aic_vec8vmulconvEN7aic_vec12vmulconv_vadEN7aic_vec5vrpacEN7aic_vec4viouEN7aic_vec5vaaddEN7aic_vec5vbs16EN7aic_vec4vms4EN7aic_vec8vextractEN7aic_vec8vcontactEN7aic_vec8vmergechEN7aic_vec7rpn_corEN7aic_vec8vscsplitEN7aic_vec8vscmergeEN7aic_vec9vcshuffleEN7aic_vec8vscatterEN7aic_vec8vpaddingEN7aic_vec7vgatherEN7aic_vec8vgatherbEN7aic_vec5vbrcbEN7aic_vec4vshrEN7aic_vec4vshlEN7aic_vec6vcmpvsEN7aic_vec7vreduceEN7aic_vec3vdpEN7aic_vec3vbiEN7aic_vec4vcbdESt23_Sp_counted_ptr_inplaceIN7aic_vec17copy_bufC2unifiedESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec20copy_unifBuf2unifBufESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec17copy_unifBuf2bufCESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec12brc_ub_2_dstESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec7col2imgESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vexp_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec10vrsqrt_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vrelu_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vrec_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vrln_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vabs_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vsqrt_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vconv_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vadd_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vsub_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vmax_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vmin_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vmul_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vmla_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vdiv_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vmadd_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec13vmaddrelu_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vaxpy_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vadds_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vmuls_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vmaxs_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vmins_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vcmp_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vsel_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec12l0c_lock_setESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec16l0c_lock_releaseESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec12vmulconv_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6movevaESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vscmergeESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vscsplitESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vcshuffleESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec7vgatherESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vgatherbESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vbrcbESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vpaddingESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6vcmpvsESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec7vreduceESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec3vdpESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec3vbiESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vshrESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vshlESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vscatterESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8movemaskESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5ldvadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vcbdESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6vmovevESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec3vciESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vexpESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6vrsqrtESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vreluESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vrecESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec3vlnESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vabsESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vcaddESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vcmaxESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vcminESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6vcgmaxESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6vcgminESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6vcgaddESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec13vncwhconv_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vmov_vadESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6vcpaddESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vnotESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vrpacESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vbs16ESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vms4ESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vextractESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vcontactESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vmergechESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec12rpn_cor_diagESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec10vtransposeESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8v4dtransESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vsqrtESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vconvESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vaddESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vsubESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vmaxESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vminESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vmulESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vmlaESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vdivESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vmaddESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec6vlreluESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec9vmaddreluESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vaxpyESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vaddsESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vmulsESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vmaxsESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vminsESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vcmpESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vcmpvESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec3vorESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vandESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4vselESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec4viouESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec5vaaddESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec7rpn_corESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec16vmovemask_xd_cmpESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec16vmovemask_cmp_xnESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec21vector_mov_special_xnESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec11vadddeqreluESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vmulconvESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vaddreluESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8vsubreluESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec12vaddreluconvESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec12vsubreluconvESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4mmadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15depth_wise_convSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13winograd_convSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI19cube_mov_special_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18load_src_to_dst_2dSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10set_dst_2dSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21load_out_to_dst_unzipSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21decompress_out_to_dstSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20set_rawheader_to_outSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17decompress_headerSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11unzip_indexSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20load_out_to_l1_imageSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18compress_ub_to_outSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI23load_l1_to_l0b_winogradSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI23load_l1_to_l0a_winogradSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16load_l1_to_l0_3dSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14mov_src_to_dstSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18mte_mov_special_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18mte_mov_xd_specialSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18load_src_to_l0b_b2SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17load_src_to_smaskSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13brc_l1_to_l0cSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18mov_src_to_dst_padSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13mvf_out_to_ubSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7mvf_dciSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12mov_nd_to_nzSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12mov_nz_to_ndSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_addSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_subSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_mulSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_maddSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_absSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_divSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_modSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_sqrtSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_negSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_maxSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_minSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_cmpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_cmpnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_selSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_andSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9scalar_orSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_xorSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_notSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_shlSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_shrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_clzSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12scalar_sbcntSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_sffSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_sflbitsSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_convSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_sbitsetSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_mov_xd_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20scalar_mov_xd_imme16SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21scalar_movk_xd_imme16SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21scalar_mov_xd_specialSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI21scalar_mov_special_xnSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9scalar_ldSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9scalar_stSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_signextSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_zeroextSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17scalar_dc_preloadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13scalar_insertSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17scalar_insert_extSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_add_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_mul_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_sub_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI23scalar_dc_preload_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_ldpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_stpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16scalar_cmp_imm12SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10scalar_stiSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14scalar_sti_immSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12scalar_movx8SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20scalar_mov_spr_imm16SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15scalar_pushq_00SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15scalar_pushq_01SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15scalar_pushq_10SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15scalar_pushq_11SaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11scalar_dcciSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4jumpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5jumpcSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5jumprSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7preloadSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4callSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7bar_setSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8bar_waitSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5callrSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4adrpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13end_executionSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3retSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4trapSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4loopSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7endloopSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7barrierSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3nopSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8nop_pipeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3dsbSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI3wfeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9hset_flagSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10hwait_flagSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7jumpcmpSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEvtransposevadddeqrelurpn_cor_diagvncwhconv_vadvbivdpvcbdviouvmlaldvadvaaddvbrcbvbs16vrpacvcgaddvcgmaxvcmpvsrpn_corv4dtransvcontactvextractvmergechvmov_vadvpaddingvscsplitisa.cc[%s] %s:%d %s memcpy_s error %d. [%s] %s:%d %s not supporting this op1 = 0x%x. [%s] %s:%d %s not supporting this encoding: %x, op1 = 0x%x. [info]: please use v2 encodingUNKNOWN_REGISTER[%s] %s:%d %s invalid instruction type. : wrong mov instruction encodingvexp_vadvrsqrt_vadvrelu_vadvrec_vadvrln_vadvabs_vadvsqrt_vadvconv_vadvadd_vadvsub_vadvmax_vadvmin_vadvmul_vadvmla_vadvdiv_vadvmadd_vadvmaddrelu_vadvaxpy_vadvadds_vadvmuls_vadvmaxs_vadvmins_vadvcmp_vadvsel_vadvmulconv_vadvscmergevcshufflevmovevvcgminvms4vconvvcmpvvmovemask_xd_cmpvmovemask_cmp_xnvmulconvvaddreluconvvsubreluconv6MteISA18mte_mov_special_xn18mte_mov_xd_special18load_src_to_dst_2d16load_l1_to_l0_3d14mov_src_to_dst20load_out_to_l1_image21store_l1_to_out_image18compress_ub_to_out21decompress_out_to_dst20set_rawheader_to_out17decompress_header21load_out_to_dst_unzip11unzip_index10set_dst_2d18load_src_to_l0b_b217load_src_to_smask23load_l1_to_l0b_winograd23load_l1_to_l0a_winograd10depth_wise13brc_l1_to_l0c9conv_calc19load_src_to_fbuffer12mte_set_flag13mte_wait_flag18mov_src_to_dst_pad13mvf_out_to_ub7mvf_dci12mov_nd_to_nz12mov_nz_to_nddecodedecodeexecuteexecutevirtual int mte_set_flag::getWritePort()virtual int mte_wait_flag::getWritePort()serializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserialize@  0@P`p 0@            @                              @                                      ????????? ?          -+   mte_isa.ccload_l1_to_l0a_2d%s(xd: %u, xn: %u, xm: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, srcIDValue: %u, dTypeValue: %u, destIDValue: %u, transposeValue: %u)load_out_to_l0a_2dload_ub_to_l0a_2dload_l1_to_l0b_2dload_out_to_l0b_2dload_ub_to_l0b_2dload_out_to_l1_2dload_src_to_dst_2dmov_ub_to_ub%s(xd: %u, xn: %u, xm: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, srcIDValue: %u, destIDValue: %u, reluValue: %u, padValue: %u)mov_out_to_ubmov_l1_to_ubmov_ub_to_l1mov_out_to_l1mov_ub_to_outmov_l1_to_outmov_l1_to_l0c16mov_l1_to_l0c32mov_l1_to_l0c16vmov_l1_to_l0c32vmov_ub_to_l1scmov_src_to_dstmvf_dci()decompress_header%s(xn: %u, xm: %u, xnValue: 0x%lx, xmValue: 0x%lx)set_rawheader_to_out%s(xd: %u, xm: %u, xdValue: 0x%lx, xmValue: 0x%lx)unzip_indexconv_calc%s(xn: %u, xt: %u, xnValue: 0x%lx, xtValue: 0x%lx, dTypeValue: %u)mte_set_flag%s(v: %u, mem: %u, eventID: %u, trigger_pipe: %u, pipe: %u)mte_wait_flagload_src_to_l0b_b2%s(xd: %u, xn: %u, xm: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx)load_out_to_l1_image%s(xd: %u, xs: %u, xt: %u, xdValue: 0x%lx, xsValue: 0x%lx, xtValue: 0x%lx, dTypeValue: %u)load_l1_to_l0b_winograd%s(xd: %u, xn: %u, xm: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, dTypeValue: %u)brc_l1_to_l0c%s(xd: %u, xn: %u, xm: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, reluValue: %u, destIDValue: %u)%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, dTypeValue: %u)compress_ub_to_out%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, dTypeValue: %lu)load_l1_to_l0a_winogradmov_nd_to_nz%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, csize: %u)mov_nz_to_nd%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, srcID: %u)store_l1_to_out_image%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, dTypeValue: %u)mvf_out_to_ub%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, dTypeValue: %u, itype: %u)mov_out_to_ub_padmov_ub_to_out_padload_src_to_smaskload_ub_to_smask%s(xd: %u, xn: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xtValue: 0x%lx, srcIDValue: %u)decompress_out_to_ub%s(xd: %u, xn: %u, xm: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, destIDValue: %u)decompress_out_to_l1decompress_out_to_dstload_out_to_fbufferload_l1_to_fbufferload_src_to_fbufferload_out_to_l0a_unzipload_out_to_l0b_unzipload_out_to_l1_unzip%s(xd: %u, xn: %u, xdValue: 0x%lx, xnValue: 0x%lx, destIDValue: %u)set_l0a_2d%s(xd: %u, xm: %u, xdValue: 0x%lx, xmValue: 0x%lx, destIDValue: %u)set_l0b_2dset_l1_2dset_dst_2dload_l1_to_l0a_3dload_l1_to_l0b_3dload_l1_to_ub_3dload_l1_to_dst_3d%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, sizeValue: %u, dTypeValue: %u, dst: %u, cSizeValue: %u, Fmatrix: 0x%lx)_v2%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, sizeValue: %u, dTypeValue: %lu, dst: %u, Transpose: %u, Fmatrix: 0x%lx)mte_mov_xd_specialmte_mov_special_xnload_l1_to_l0_3dload_out_to_dst_unzipdepth_wisemov_src_to_dst_padmvf_dci[ERROR]: ccu_addr_err: mte: addr: 0x{0:08x}, instr: {1:s}, id: {2:d}St23enable_shared_from_thisI8PushqISAESt23enable_shared_from_thisI11PushqISAInsE8PushqISA11PushqISAInsSt23_Sp_counted_ptr_inplaceIN7aiv_vec9sfuStaticESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceISt3mapI13PushqInfoType9PushqInfoSt4lessIS1_ESaISt4pairIKS1_S2_EEESaIS9_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8PushqISASaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ serialize                 -+ pushq_isa_t PushqISAIns::new_pushq_11(std::shared_ptr)  pushq_isa.ccvf(pc: %lx, pb_id: %lld, pc_offset[9:5]: %lx, pc_offset[4:0]: %lx)vfru(pc: %lx, pb_id: %lld, pc_offset[9:5]: %lx, pc_offset[4:0]: %lx)release_pbid(pb_id: %lld), id: SET_FLAGWAIT_FLAGRELEASE_PBIDVSET_EVENTFIFR1MOV_SPR_XNVFVFRUMOV_UB_TO_UBFMAXFMINRPN_COR_DIAG2MOVEVALDVAdMOVEMASKVNCHWCONV_VVVTRANSPOSEVCSHUFFLEV4DTRANSVSCSPLITVSORT8VMS4executeexecutedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodedecodeexecutedecodedecodedecodedecodedecodedecodedecodeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserializeserialize@  0@P`p 0@                      ( 0 8 @ H P X ` h p x  -+   9ScalarISA10scalar_add10scalar_sub10scalar_mul11scalar_madd10scalar_abs10scalar_div10scalar_mod11scalar_sqrt10scalar_neg10scalar_max10scalar_min10scalar_cmp11scalar_cmpn10scalar_sel10scalar_and9scalar_or10scalar_xor10scalar_not10scalar_shl10scalar_shr12scalar_sbcnt10scalar_sff10scalar_clz14scalar_sflbits14scalar_sbitset16scalar_mov_xd_xn20scalar_mov_xd_imme1621scalar_movk_xd_imme1621scalar_mov_xd_special21scalar_mov_special_xn14scalar_signext14scalar_zeroext9scalar_ld9scalar_st13scalar_ld_imm13scalar_st_imm11scalar_conv13scalar_insert17scalar_insert_ext12scalar_movx820scalar_mov_spr_imm1616scalar_add_imm1216scalar_mul_imm1216scalar_sub_imm1210scalar_ldp10scalar_stp10scalar_sti14scalar_sti_imm16scalar_cmp_imm1211scalar_dcci17scalar_dc_preload23scalar_dc_preload_imm1215scalar_pushq_0015scalar_pushq_0115scalar_pushq_1015scalar_pushq_11scalar_isa.cc[%s] %s:%d %s imme16 errors [%s] %s:%d %s dType errors [%s] %s:%d %s OP errors [%s] %s:%d %s datasource errors [%s] %s:%d %s imm6 errors [%s] %s:%d %s sbcnt errors [%s] %s:%d %s sff errors [%s] %s:%d %s bitSet errors [%s] %s:%d %s uimm2 errors [%s] %s:%d %s postValue errors [%s] %s:%d %s imm12 errors [%s] %s:%d %s imm6_5_4 errors [%s] %s:%d %s imm6_3_0 errors [%s] %s:%d %s uimm8 errors [%s] %s:%d %s ext errors [%s] %s:%d %s position_5 errors [%s] %s:%d %s position_4_0 errors [%s] %s:%d %s imm16 errors [%s] %s:%d %s xi errors [%s] %s:%d %s xj errors [%s] %s:%d %s immType errors [%s] %s:%d %s imm12_11_7 errors [%s] %s:%d %s imm12_6_0 errors %s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx )%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, OP:0x%lx, conditionFlag:0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, OP:0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx,)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx )%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, datasource:= 0x%lx, imm6:= 0x%lx )%s(dType:0x%lx, x[%ld]= 0x%lx,x[%ld]= 0x%lx , datasource:= 0x%lx, imm6:= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx,x[%ld]= 0x%lx, sbcnt:0x%lx)%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx, sff:0x%lx)%s(dType:0x%lx,x[%ld]= 0x%lx, x[%ld]= 0x%lx, bitSet:0x%lx)%s( x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(x[%ld]= 0x%lx, imme16:0x%lx )%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, post = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm12= 0x%lx, post = 0x%lx)%s( x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm6 = 0x%lx, imm5 = 0x%lx)%s( x[%ld]= 0x%lx, x[%ld]= 0x%lx, ext = 0x%lx, position = 0x%lx, uimm8 = 0x%lx)%s( x[%ld]= 0x%lx, imm16 = 0x%lx)%s( %s = 0x%lx, imm16 = 0x%lx)%s(x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm12 = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm6= 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, post = 0x%lx, immType = 0x%lx, immTypeValue = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx, post = 0x%lx, immType = 0x%lx, immTypeValue = 0x%lx, imm12 = 0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx, imm12 = 0x%lx, OP:0x%lx, conditionFlag:0x%lx)%s(dType:0x%lx, x[%ld]= 0x%lx)%s(x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(x[%ld]= 0x%lx, imm12= 0x%lx)%s(x[%ld]= 0x%lx, x[%ld]= 0x%lx, x[%ld]= 0x%lx)%s(x[%ld]= 0x%lx, x[%ld]= 0x%lx, imm5= 0x%lx)%s(x[%ld]= 0x%lx, imm10 = 0x%lx)%s(imm5 = 0x%lx, imm10 = 0x%lx)scalar_addscalar_subscalar_mulscalar_maddscalar_absscalar_divscalar_modscalar_sqrtscalar_negscalar_maxscalar_minscalar_cmpscalar_cmpnscalar_selscalar_andscalar_orscalar_xorscalar_notscalar_shlscalar_shrscalar_sbcntscalar_sffscalar_clzscalar_sflbitsscalar_sbitsetscalar_mov_xd_xnscalar_mov_xd_imme16scalar_movk_xd_imme16scalar_mov_xd_specialscalar_mov_special_xnscalar_signextscalar_zeroextscalar_ldscalar_stscalar_ld_immscalar_st_immscalar_convscalar_insertscalar_insert_extscalar_movx8scalar_mov_spr_imm16scalar_add_imm12scalar_sub_imm12scalar_mul_imm12scalar_ldpscalar_stpscalar_stiscalar_sti_immscalar_cmp_imm12scalar_dcciscalar_dc_preloadscalar_dc_preload_imm12scalar_pushq_00scalar_pushq_01scalar_pushq_10scalar_pushq_11}{ywusqomigc][YUQMIIGGEECCAA??==;;55333311-+)'\ZXVTPLHDBB@<840.*&"" |}~ EFGHs)*LMNOPQRS@  0@P`p 0@           B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                        ( 0 8 @ H P X ` h p x  -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             St23enable_shared_from_thisIN7aiv_vec10THREAD_ISAEEN7aiv_vec10THREAD_ISAESt23_Sp_counted_ptr_inplaceIN7aiv_vec16VEC_DYNAMIC_INFOESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec12VEC_ISA_INFOESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec10vloop_ctrlESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec3vldESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec3vstESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec3vexESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec12verror_instrESaIS1_ELN9__gnu_cxx12_Lock_policyE2EEthread_isa.cc. Id: N7aiv_vec10vloop_ctrlEN7aiv_vec12verror_instrEN7aiv_vec3vldEN7aiv_vec3vstEN7aiv_vec3vexE@ serialize 0@P`p 0@           B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                        ( 0 8 @ H P X ` h p x  -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vector_aiv_isa.ccverror_instrvloop_ctrlb32vexvloop(instr_num: %u, para_num: %u, loop: %u)vloopn.%s(instr_num: %u, para_num: %u, loop: %u)vloopc(instr_num: %u, para_num: %u, loop: %u)vpd(Pd: %u)vag(sn: %u, sm: %u, sd: %u, st: %u)11BasicBufferreadBankwriteBankcheckReadWriteBytesParagetAccessMaskreadLastLinereadFirstLinewriteLastLinewriteFirstLine@ readreadwritewritereadByteswriteBytesreadByteswriteBytesBasicBuffer-+   basic_buffer.cc[%s] %s:%d %s memcpy_s failed, error num: %d [%s] %s:%d %s %s readBank: the address value :%d is not found [%s] %s:%d %s %s writeBank: the address value :%d is not found [%s] %s:%d %s tick: %u. %s Address errors: the address or size is too big. start addr = 0x%x, size = 0x%x. [%s] %s:%d %s %s readBytes: the start address value over buffer size bound. address = 0x%x [%s] %s:%d %s %s getAccessMask errors. [%s] %s:%d %s %s read errors [%s] %s:%d %s %s write errors [%s] %s:%d %s %s readBytes: the address value :%d is too big [%s] %s:%d %s BasicBuffer::readBytes Size not match ERROR [%s] %s:%d %s %s writeBytes: the start address value over buffer size bound, address = 0x%x [%s] %s:%d %s %s writeBytes: the address value :%d is too big [%s] %s:%d %s bank_size is 0 that leads to division by zero. 8BasicDDR11BasicICacheSt23_Sp_counted_ptr_inplaceI5ICReqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7WRR_ArbSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI6RR_ArbSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEread_cache_ram@ refillBasicICache 0@P`p 0@            -+   readpreload_tspreload_ccucheck_ll_rsplookup_tagbasic_icache.ccunknown typeNONEPRELOADPREFETCHREADunknown statusIDLEHITMISSFETCHINGCOMPLETEDPRELOAD_TSPRELOAD_CCU---------------------------------------------------------------------req_id_: addr_: dest: buf_id: type: status: ll_req_id: -------------------- [{0:08d}]: icache READ request, id is 0x{1:x}, size is 0x{2:08x}, address is 0x{3:x}-------------------- [{0:08d}]: icache PRELOAD_TS request fail, addr: 0x{1:x}, preload_fifo_ size: 0x{2:x}, num: 0x{3:x}-------------------- [{0:08d}]: icache PRELOAD_TS request, addr: 0x{1:x}, num: 0x{2:x}, cacheline_nums: 0x{3:x}, req_id: 0x{4:x}-------------------- [{0:08d}]: icache PRELOAD_CCU request fail, addr: 0x{1:x}, preload_fifo_ size: 0x{2:x}-------------------- [{0:08d}]: icache PRELOAD_CCU request, addr: 0x{1:x}, num: 0x{2:x}, cacheline_nums: 0x{3:x}, req_id: 0x{4:x}-------------------- [{0:08d}]: icache PRELOAD_VCCU request, fifo is full, req_id is 0, address is 0x{1:x}, cmd_len is 0x{2:08x}-------------------- [{0:08d}]: icache PRELOAD_VCCU request, id is 0x{1:08x}, address is 0x{2:x}, cacheline_req_times is 0x{3:08x}[{0:08d}]: ccu end_instr flush icache clean_req_lst, preload_req id is 0x{1:x}[{0:08d}]: ccu end_instr flush icache clean_req_lst, normal_req id is 0x{1:x}[{0:08d}]: ccu miss_predict flush icache pipeline, normal_req id is 0x{1:x}[{0:08d}]: ccu miss_predict flush icache cmbf, normal_req id is 0x{1:x}[{0:08d}]: icache get_wrr_req: {1:s}, req_id_: 0x{2:x}[{0:08d}]: icache get_wrr_req: {1:s}, preload_type: {2:s}, req_id_: 0x{3:x}[{0:08d}]: icache refill acknowledge, req_id_: 0x{1:x}, ll_req_id_ is 0x{2:08x}, address is 0x{3:x}, buf_id is 0x{4:x}SIZE ERROR, tick: {0:d}, addr: 0x{1:x},size_: 0x{2:x},[{0:08d}]: icache refill request has same addr in CMBF, req_type:{1:08x}, req_id_: 0x{2:x}, ll_req_id_ is 0x{3:08x}, address is 0x{4:x}[{0:08d}]: icache refill request ostd hazard, req_type:{1:08x}, req_id_ is 0x{2:08x}, ll_req_id_ is 0x{3:08x}, address is 0x{4:x}, buf_id is 0x{5:x}[{0:08d}]: icache refill request, req_type:{1:08x}, req_id_ is 0x{2:x}, ll_req_id_ is 0x{3:08x}, address is 0x{4:x}, buf_id is 0x{5:x}[{0:08d}]: icache preload generate req num: 0x{1:x}, total_num: 0x{2:x}, req_id_: 0x{3:x}[{0:08d}]: icache preload fifo generate req done, req_id_: 0x{1:x}[{0:08d}]: icache read address is 0x{1:x}, size is 0x{2:08x}, status is {3:s}[{0:08d}]: icache replay stall[{0:08d}]: icache prefetch data is 0x{1:x}, id is 0x{2:x}[{0:08d}]: icache preload lookup_tag address is 0x{1:x}, id is 0x{2:x}, size is 0x{3:08x}, status is {4:s}[SP_ARB]: Requests are: [RR_ARB]: Requests are: [RR_ARB]: Last arb is: : [WRR_ARB]: Requests are: [WRR_ARB]: Weights are: [WRR_ARB]: Scores are: [WRR_ARB]: Weights sum is: 8CADCacheSt23_Sp_counted_ptr_inplaceI15MSHR_comparatorSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14STB_comparatorSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11DCacheFetchSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5DCReqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESTB_32B_write_linefill_bufSTB_32B_write_cache_req@  0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          -+   readread_cache_ramwriteDataread_STBwrite_STBMSHR_linefill_merge_reqSTB_linefill_merge_reqretire_MSHR_ld_instrwriteback_req_creatwriteback_cache_ramca_dcache.ccaligned_addr: addr_ofst_: aligned_size_: hit_pos_: buf_id_: ll_req_id_: ll_req_status_: refill_line_: tick: {0:d}, check_STB_write_UB_rsp complete_req0, ub_req_id0_: {1:d}.tick: {0:d}, check_STB_write_UB_rsp complete_req1, ub_req_id1_: {1:d}.tick: {0:d}, check_MSHR_read_BIU_rsp complete_req0, biu_req_id0_: {1:d}.tick: {0:d}, check_MSHR_read_BIU_rsp complete_req1, biu_req_id1_: {1:d}.------------------------ tick: {0:d}, ccu_ack_to_refill_buf req_id: {1:d} ------------------------------------------------ tick: {0:d}, completed_req_id: {1:d} ------------------------tick: {0:d}, clean_req_lst push req_id: {1:d} to completed_reqs_tick: {0:d}, clean_req_lst push req_id: {1:d} to ccu_ack_refill_buf_tick: {0:d}, check_UB_evict_rsp complete_req0, ub_req_id_: {1:d}.tick: {0:d}, check_UB_evict_rsp complete_req1, ub_req_id_: {1:d}.------------------------ tick: {0:d}, reset drain_all_STB_req ------------------------------------------------ tick: {0:d}, drain_all_STB_req ------------------------tick: {0:d}, M2_check_conflict has_MSHR_main_entry_resource_hzd, align_addr: 0x{1:x}, MSHR_main_entry_size: {2:d}.tick: {0:d}, M2_check_conflict has_STB_main_entry_resource_hzd, aligned_47_5: 0x{1:x}, STB_main_entry_size: {2:d}.tick: {0:d}, M2_check_conflict st_has_MSHR_ld_miss_address_hzd, align_addr: 0x{1:x}, MHSR_main_entry: {2:d}.tick: {0:d}, M2_check_conflict has_STB_forbid_hzd, align_addr: 0x{1:x}, STB_main_entry: {2:d}tick: {0:d}, M2_check_conflict has_MSHR_forbid_hzd, align_addr: 0x{1:x}, MHSR_main_entry: {2:d}tick: {0:d}, M2_check_conflict has_STB_sub_entry_resource_hzd, aligned_47_5: 0x{1:x}, STB_main_entry: {2:d}, STB_sub_entry_size: {3:d}.tick: {0:d}, M2_check_conflict has_MSHR_sub_entry_resource_hzd, align_addr: 0x{1:x}, MHSR_main_entry: {2:d}, MSHR_sub_entry_size: {3:d}.tick: {0:d}, M3_STB_read_biu_evict_addr_hzd, evict detail: type: {1:d}, align_addr: 0x{2:x}, wb_req_id: {3:d}.tick: {0:d}, M2_check_conflict has_evict_addr_hzd, evict detail: type: {1:d}, align_addr: 0x{2:x}, wb_req_id: {3:d}.tick: {0:d}, M3_MSHR_read_biu_evict_addr_hzd, evict detail: type: {1:d}, align_addr: 0x{2:x}, wb_req_id: {3:d}.tick: {0:d}, M0_check_conflict has M1_backpressure_stall, M1_instr: req_id: {1:d}, req_type: {2:d}, addr: 0x{3:x}, size: {4:d}tick: {0:d}, size error: 0x{1:x}, addr: 0x{2:x}tick: {0:d}, M0_check_conflict pass, req_type: {1:d}, addr:0x{2:x}, size:{3:x}------------------------ tick: {0:d},read_creat_req, req_id: {1:d}, req_addr: 0x{2:x}, read size: 0x{3:x}, is_ub: 0x{4:x}, is_stack: 0x{5:x}, ldbuf_ptr: 0x{6:x} ------------------------tick: {0:d}, invalid_cache_ram_va, wb_req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, MX: complete_writeback, wbreq_id: {1:d} suc , req_type:{2:d}, req_sta:{3:d}bitset::set%s: __position (which is %zu) >= _Nb (which is %zu)tick: {0:d}, M2_lookup_STB, req_id: {1:d}, req_type: {2:d}, addr: 0x{3:x}, size: {4:d}, match_STB_47_5: {5:d}, match_STB_47_5_id: {6:d}, match_STB_47_6: {7:d}, match_STB_47_6_id: {8:d}, stb_hit_strobe_: 0x{9:x}.tick: {0:d}, M2_lookup_MSHR, req_id: {1:d}, req_type: {2:d}, addr: 0x{3:x}, size: {4:d}, match_MSHR: {5:d}, match_MSHR_id: {6:d}.tick: {0:d}, replay M1/M2 stage instr: req_id: {1:d}, req_type:{2:d}tick: {0:d}, READ_CACHE_RAM, req_id: {1:d}, req_type: {2:d}, req_sta: {3:d}, req_addr: 0x{4:x}, addr_ofst: {5:d}, read_size: {6:d}.tick: {0:d}, M3:check_write_DATA_RSP success, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}, buf_id:{6:d}tick: {0:d}, M3:send_write_DATA success, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}, buf_id:{6:d}tick: {0:d}, M3:send_write_DATA fail, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}, buf_id:{6:d}tick: {0:d}, READ_STB, req_id: {1:d}, req_type: {2:d}, req_sta: {3:d}, req_addr: 0x{4:x}, total_read_size: {5:d}.tick: {0:d}, M3:check_write_REQ_RSP success, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}tick: {0:d}, ST_STB, req_id: {1:d}, req_type: {2:d}, req_sta: {3:d}, req_addr: 0x{4:x}, req_stb_ofst_: {5:d}, req_stb_length_: {6:d}, stb_strobe: 0x{7:x}.MSHR_MERGE_linefill_write_cache (ub_uncacheable)MSHR_MERGE_linefill_write_cachetick: {0:d}, {1:s}, MSHR_id: {2:d}, fetch_buf_id: {3:d}, align_addr: 0x{4:x}, idx_addr: {5:d}, avail_way_: {6:d}.STB_MERGE_linefill_write_cache (ub_uncacheable)STB_MERGE_linefill_write_cachetick: {0:d}, {1:s}, STB_id: {2:d}, fetch_buf_id: {3:d}, align_addr: 0x{4:x}, idx_addr: {5:d}, avail_way_: {6:d}, link_: {7:d}, link_index_: {8:d}.tick: {0:d}, send_write_req0_to_UB success, STB_id: {1:d}, ub_wr_req_id_: {2:d}, write_addr_: 0x{3:x}, masks: 0x{4:x}.tick: {0:d}, send_write_req1_to_UB success, STB_id: {1:d}, ub_wr_req_id_: {2:d}, write_addr_: 0x{3:x}, masks: 0x{4:x}.tick: {0:d}, send_write_req0_to_BIU success, STB_id: {1:d}, biu_wr_req_id_: {2:d}, write_addr_: 0x{3:x}.tick: {0:d}, send_write_req1_to_BIU success, STB_id: {1:d}, biu_wr_req_id_: {2:d}, write_addr_: 0x{3:x}.tick: {0:d}, STB_write_cache, STB_id: {1:d}, aligned_47_5: 0x{2:x}, idx_addr: 0x{3:x}, hit_way: {4:d}. ST_HIT_UNLOCK_CACHELINEtick: {0:d}, STB_write_cache, STB_id: {1:d}, aligned_47_5: 0x{2:x}, idx_addr: 0x{3:x}, hit_way: {4:d}.tick: {0:d}, INVALID_CACHELINE_req_creat, wb_req_id: {1:d}, idx_addr: {2:d}, tag_pos: {3:d}, wb_req_type: {4:d}, wb_req_sta: {5:d}tick: {0:d}, invalid_cache_ram_all, wb_req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, invalid_cache_ram, CMOING req complete, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, invalid_cache_ram, INVALIDING req complete, req_id: {1:d}, aligned_addr: 0x{2:x}, req_type:{3:d}, req_sta:{4:d}tick: {0:d}, M2_MERGE_STB, req_id: {1:d}, req_type: {2:d}, addr: 0x{3:x}, STB_id: {4:d}, cur_merge_num: {5:d}.tick: {0:d}, M2_MERGE_MSHR, req_id: {1:d}, req_type: {2:d}, addr: 0x{3:x}, MSHR_id: {4:d}, cur_merge_num: {5:d}.tick: {0:d}, M2_CREATE_MSHR, req_id: {1:d}, req_type: {2:d}, addr: 0x{3:x}, MSHR_id: {4:d}, cur_merge_num: {5:d}, need_read_mem: {6:d}, STB_valid: {7:d}, STB_index: {8:d}.tick: {0:d}, M2_CREATE_STB, req_id: {1:d}, req_type: {2:d}, addr: 0x{3:x}, STB_id: {4:d}, cur_merge_num: {5:d}, has_linked_STB: {6:d}, link_index: {7:d}.tick: {0:d}, clear_MSHR, req_addr: 0x{1:x}, MSHR_id: {2:d}, release_fetch_buf: {3:d}, fetch_buf_id: {4:d}.tick: {0:d}, clear_STB, aligned_47_5: 0x{1:x}, STB_id: {2:d}, release_fetch_buf: {3:d}, fetch_buf_id: {4:d}.tick: {0:d}, ld_st_bypass, isa: {1:s}, pc: {2:x}, src_reg: x{3:d}, skew_gpr_value: 0x{4:x}------------------------ tick: {0:d},write_creat_req, req_id: {1:d}, req_addr: 0x{2:x}, write size: 0x{3:x}, is_ub: 0x{4:x}, is_stack: 0x{5:x}, st_bufptr: 0x{6:x} ------------------------tick: {0:d}, M3_STB_READ_CACHE: req_id: {1:d} {2:s}, idx_addr: {3:d}, aligned_addr_: {4:x}, tag_addr: {5:x}, hit_pos: {6:d}, need_write_cache: {7:d}, need_read_mem: {8:d}, need_write_mem: {9:d}. ST_HIT_LOCK_CACHELINEtick: {0:d}, M3_STB_READ_CACHE: req_id: {1:d} {2:s}, idx_addr: {3:d}, aligned_addr_: {4:x}, tag_addr: {5:x}, hit_pos: {6:d}, need_write_cache: {7:d}, need_read_mem: {8:d}, need_write_mem: {9:d}.tick: {0:d}, retire_MSHR_ld_instr , req_id: {1:d}, req_addr: 0x{2:x}, req_type: {3:d}, req_sta: {4:d}, cur_merge_num: {5:d}.tick: {0:d}, REFILL WRITEBACK_CACHELINE_req_creat, wb_req_id: {1:d}, flush_buf_id: {2:d}, wb_req_addr: 0x{3:x}tick: {0:d}, FLUSH WRITEBACK_CACHELINE_req_creat, wb_req_id: {1:d}, idx_addr: {2:d}, tag_pos: {3:d}, wb_req_type:{4:d}, wb_req_sta:{5:d}, wb_req_addr: 0x{6:x}tick: {0:d}, clean_cache_ram_all, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, clean_cache_ram_va, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, create_req_complete for invalid_clean_cache_ram_all, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, create_req_complete for invalid_clean_cache_ram_va, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}tick: {0:d}, get_victim fail, avail_way_start: {1:d}, avail_way_end: {2:d}tick: {0:d}, get_victim, find invalid cacheline, victim_pos: {1:d}tick: {0:d}, get_victim, lru valid cacheline, victim_pos: {1:d}tick: {0:d}, get_victim, lru valid cacheline, dirty replace, victim_pos: {1:d}tick: {0:d}, retire_STB_st_instr, req_id: {1:d}, req_addr: 0x{2:x}, req_type: {3:d}, req_sta: {4:d}, cur_merge_num: {5:d}.tick: {0:d}, retire_STB_st_instr slave_entry, req_id: {1:d}, req_addr: 0x{2:x}, req_type: {3:d}, req_sta: {4:d}, cur_merge_num: {5:d}.tick: {0:d}, M2_lookup_tag, req_id: {1:d}, req_type: {2:d}, req_sta: {3:d}, req_addr: 0x{4:x}, aligned_addr: 0x{5:x}, addr_ofst: {6:d}, aligned_size: {7:d}tick: {0:d}, M2_lookup_tag: cmo_all HIT, req_id: {1:d}, req_type: {2:d}, req_sta: {3:d}tick: {0:d}, M2_lookup_tag: req_id: {1:d} HIT, idx_addr: {2:d}, aligned_addr_: {3:x}, tag_addr: {4:x}, hit_pos: {5:d}tick: {0:d}, M2_lookup_tag: cmo_va HIT, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}, req_addr: 0x{4:x}tick: {0:d}, M2_lookup_tag: cmo_va MISS, req_id: {1:d}, req_type:{2:d}, req_sta:{3:d}, req_addr: 0x{4:x}tick: {0:d}, ST_HIT_LOCK_CACHELINE: req_id: {1:d}, idx_addr: {2:d}, aligned_addr_: {3:x}, tag_addr: {4:x}, hit_pos: {5:d}tick: {0:d}, M2_lookup_tag: req_id: {1:d} MISS------------------------ tick: {0:d}, invalid_clean_all_creat_req, req_id: {1:d} ------------------------------------------------ tick: {0:d}, invalid_clean_va_creat_req, req_id: {1:d}, req_addr: 0x{2:x} ------------------------tick: {0:d}, M2_CHECK_WRITE_REG not ready, need replay. req_id: {1:d}, re_type: {2:d}, addr: 0x{3:x}.tick: {0:d}, M3:send_write_REQ success, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}, ll_req_id:{5:d}tick: {0:d}, M3:send_write_REQ id fail, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}tick: {0:d}, M3:send_write_REQ fail, wbreq_id: {1:d}, wbreq_type:{2:d}, wbreq_sta:{3:d}, req_addr: {4:x}tick: {0:d}, evict_req0_to_UB success, buf_id: {1:d}, ub_req_id_: {2:d}, write_addr: 0x{3:x}.tick: {0:d}, evict_req1_to_UB success, buf_id: {1:d}, ub_req_id_: {2:d}, write_addr: 0x{3:x}.STBtick: {0:d}, {1:s} send_read_req0_to_UB success, fetch_buf_id: {2:d}, ub_ld_req_id_: {3:d}, read_addr_: 0x{4:x}, is_stack_req: 0x{5:x}.tick: {0:d}, {1:s} send_read_req1_to_UB success, fetch_buf_id: {2:d}, ub_ld_req_id_: {3:d}, read_addr_: 0x{4:x}, is_stack_req: 0x{5:x}.tick: {0:d}, {1:s} send_read_req0_to_BIU success, fetch_buf_id: {2:d}, biu_ld_req_id_: {3:d}, read_addr_: 0x{4:x}, is_stack_req: 0x{5:x}.tick: {0:d}, {1:s} send_read_req1_to_BIU success, fetch_buf_id: {2:d}, biu_ld_req_id_: {3:d}, read_addr_: 0x{4:x}, is_stack_req: 0x{5:x}.MSHRtick: {0:d}, check_MSHR_read_UB_rsp complete_req0, req_addr: 0x{1:x}, ub_req_id0_: {2:d}.tick: {0:d}, check_MSHR_read_UB_rsp complete_req1, req_addr: 0x{1:x}, ub_req_id1_: {2:d}.tick: {0:d}, check_MSHR_read_BIU_rsp complete_req0, req_addr: 0x{1:x}, biu_req_id0_: {2:d}.tick: {0:d}, check_MSHR_read_BIU_rsp complete_req1, req_addr: 0x{1:x}, biu_req_id1_: {2:d}.tick: {0:d}, check_STB_read_UB_rsp complete_req0, req_addr: 0x{1:x}, ub_req_id0_: {2:d}.tick: {0:d}, check_STB_read_UB_rsp complete_req1, req_addr: 0x{1:x}, ub_req_id1_: {2:d}.tick: {0:d}, check_STB_read_BIU_rsp complete_req0, req_addr: 0x{1:x}, biu_req_id0_: {2:d}.tick: {0:d}, check_STB_read_BIU_rsp complete_req1, req_addr: 0x{1:x}, biu_req_id1_: {2:d}.8CAICache@ getInstrSet 0@P`p 0@            -+   ca_icache.ccvector::_M_realloc_insertvector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)[%s] %s:%d %s ca_icache, instr number doesn't match! [{0:08d}]: sghr after updateSGhr, sghr_:{1:08x}[{0:08d}]: sghr before predictor, sghr_:{1:08x}[{0:08d}]: cghr before predictor, cghr_:{1:08x}[{0:08d}]: cghr after predictor, cghr_:{1:08x}[{0:08d}]: sghr after predictor, sghr_:{1:08x}11DCacheFetchSt23_Sp_counted_ptr_inplaceI9SpaceUnitSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ -+   dcache_fetcher.cctick: {0:d},fetch input fail, the req is already in pref_req_list ,the req is :{1:s} , req type is :{2:d}, isa pc is :{3:x}tick: {0:d},fetch input success, the instruction addr is :0x{1:x} , req type is :{2:d}, isa name is: {3:s},isa pc is :{4:x}tick: {0:d},lookup base addr success, the instruction addr is: 0x{1:x}, req type is: {2:d}, isa name is :{3:s},isa pc is :{4:x},the match unit is :{5:d},the base addr is :{6:x}[{0:08d}]: get_max_dis_cnt_unit is :{1:d}tick: {0:d}, create new history track list success, the new spcae unit is: {1:d}, the baseaddr is: 0x{2:x}[{0:08d}]: dcache prefetch addr is :0x{1:x}, id is: 0x{2:x}tick: {0:d}, direct conflict, the space unit is :{1:d}, the fetch direct is: {2:x}, current index is :{3:x}, left index is :{4:x}, right index is :{5:x},tick: {0:d},set swap buf success, the swap space unit is {1:d}, space new addr is 0x{2:x},tick: {0:d},set swap buf failed, the space has been already swap, space unit is {1:d}, space origian addr is 0x{2:x}, swap_flag is {3:x}tick: {0:d},the swap space has been already, space unit is {1:d}, space addr is 0x{2:x}tick: {0:d}, do not match any fetch unit, need to create new history track list, req is :{1:s}, pc is :{2:x}[{0:08d}]: get arbiter unit is :{1:d}[{0:08d}]: fetcher completed ,req_id is: 0x{1:d}, req type is :{2:d}[{0:08d}]: req reaches the max value fetch stall ,req_cnt is :0x{1:d}8PMU_ITEM12pmu_status_t13pmu_counter_t12pmu_number_t11pmu_ratio_t8pmu_bw_t3PMUSt23_Sp_counted_ptr_inplaceIN9DvcConfig3CfgESaIS1_ELN9__gnu_cxx12_Lock_policyE2EEupdatecalc_bwconst toml::Value* toml::Value::findChild(const string&) constset_config_file@ void PMU::register_status_event(pmu_msg_type, const string&, uint32_t)void PMU::register_counter_event(pmu_msg_type, const string&, uint32_t)void PMU::register_number_event(pmu_msg_type, const string&, uint32_t)void PMU::register_ratio_event(pmu_msg_type, const string&, uint32_t)void PMU::register_bw_event(pmu_msg_type, const string&, uint64_t, uint64_t, uint32_t)-+   string didn't start with '"'string didn't endstring has unknown escape sequencestring didn't start with '''?string didn't end with ''''' ?string didn't end with '''?Unknown key formatis()pmu.ccconfig_aicore_trace.toml[%s] %s:%d %s PMU using config file: %s [%s] %s:%d %s Invalid PMU config file: %s [%s] %s:%d %s PMU config file %s not found. ccu_num == 2 || ccu_num == 1nullboolunknowndoublearraytablebw_setting.window_size[error] cfg_ path is unqualified.type must be table to do get(key). was not found.key int64_t was requested but type error: this value is bw_setting.stride_sizevector.vec_instr_execvector.vec_instr_pop_statusvector.vec_instr_pop_cyclevector.vec_instr_retire_statusvector.vec_instr_retire_cyclescalar.scalar_instr_execscalar.scalar_instr_popscalar.scalar_instr_pop_cyclescalar.scalar_instr_retirescalar.scalar_instr_retire_cyclecube.cube_instr_execmte.mte1_instr_execmte.mte2_instr_execmte.mte3_instr_execmte.mte4_instr_execmte.mte5_instr_execmte.mte2_aiv_instr_execmte.mte3_aiv_instr_execmte.mte1_instr_popmte.mte2_instr_popmte.mte3_instr_popmte.mte4_instr_popmte.mte5_instr_popmte.mte2_aiv_instr_popmte.mte3_aiv_instr_popmte.mte1_instr_retiremte.mte2_instr_retiremte.mte3_instr_retiremte.mte4_instr_retiremte.mte5_instr_retiremte.mte2_aiv_instr_retiremte.mte3_aiv_instr_retirevector.vec_busy_statusvector.vec_busy_cyclevector.vec_excute_statusvector.vec_excute_cyclesvector.vec_l0c_ub_cyclesscalar.scalar_busy_statusscalar.scalar_busy_cyclesscalar.scalar_exe_statusscalar.scalar_exe_cyclesscalar.scalar_ldst_statusscalar.scalar_ldst_cyclesscalar.scalar_mac_usage_statusscalar.scalar_mac_usage_cyclescube.cube_busy_statuscube.cube_busy_cyclecube.cube_mac_busy_statuscube.cube_mac_busy_cyclecube.cube_efficiencymte.mte1_busy_statusmte.mte2_busy_statusmte.mte3_busy_statusmte.mte4_busy_statusmte.mte5_busy_statusmte.mte2_aiv_busy_statusmte.mte3_aiv_busy_statusmte.mte1_busy_cyclemte.mte2_busy_cyclemte.mte3_busy_cyclemte.mte4_busy_cyclemte.mte5_busy_cyclemte.mte2_aiv_busy_cyclemte.mte3_aiv_busy_cyclecube.cube_instr_popcube.cube_instr_retirevector.vec_ld_busy_statusvector.vec_ld_busy_cyclesvector.vec_exe_busy_statusvector.vec_exe_busy_cyclesvector.vec_st_busy_statusvector.vec_st_busy_cyclesvector.vec_gatherscatter_busy_statusvector.vec_gatherscatter_busy_cyclesvector.vec_busy_cyclesvector.vec_ccu_busy_statusvector.vec_ccu_busy_cyclesvector.vec_ld_excute_statusvector.vec_ld_excute_cyclesvector.vec_exe_excute_statusvector.vec_exe_excute_cyclesvector.vec_st_excute_statusvector.vec_st_excute_cyclesvector.vec_gatherscatter_excute_statusvector.vec_gatherscatter_excute_cyclesvector.vec_ld_efficiencyvector.vec_exe_efficiencyvector.vec_st_efficiencyvector.vec_gatherscatter_efficiencyvector.vec_efficiencyvector.vec_mac_busy_statusvector.vec_mac_usage_cyclesmte.aipp_busy_statusmte.aipp_busy_cyclesmte.aipp_instr_popmte.aipp_instr_retirevector.sfu_busy_cyclevector.sfu_instr_popvector.sfu_instr_retiremte.l0c_write_bandwidthmte.l0c_write_cyclemte.l2_buf_read_reqmte.l2_buf_write_reqmte.ddr_read_reqmte.ddr_write_reqvector.ub_read_bandwidthvector.ub_write_bandwidthvector.ub_read_statusvector.ub_write_statuscube.l0a_read_bandwidthmte.l0a_write_bandwidthcube.l0a_read_cyclesmte.l0a_write_cyclecube.l0b_read_bandwidthmte.l0b_write_bandwidthcube.l0b_read_cyclesmte.l0b_write_cyclevector.vec_2_l0c_read_bandwidthcube.cube2l0c_read_bandwidthvector.vec_2_l0c_write_bandwidthcube.cube2l0c_write_bandwidthvector.vec_2_l0c_read_statuscube.cube2l0c_read_cyclesvector.vec_2_l0c_write_statuscube.cube2l0c_write_cyclesmte.l1_read_bandwidthmte.l1_write_bandwidthmte.l1_read_cyclemte.l1_write_cyclemte.l1_rd_rd_bank_conflict_cyclemte.l1_rd_wr_bank_conflict_cyclemte.l1_wr_wr_bank_conflict_cyclescalar.scalar2ub_read_statusscalar.scalar2ub_write_statusscalar.total_scalar2ub_statusscalar.scalar2ub_read_reqscalar.scalar2ub_write_reqscalar.total_scalar2ub_reqscalar.scalar2ub_read_cyclesscalar.scalar2ub_write_cyclesscalar.total_scalar2ub_cyclesmte.mte3_ub_read_bandwidthmte.mte3_ub_write_bandwidthmte.mte3_ub_read_cyclemte.mte3_ub_write_cyclevector.vec_2_ub_read_bandwidthvector.vec_2_ub_write_bandwidthvector.vec_2_ub_read_statusvector.vec_2_ub_write_statusvector.vec_2_pb_read_bandwidthvector.vec_2_pb_read_statusvector.sfu_ub_read_bandwidthvector.sfu_ub_write_bandwidthvector.sfu_ub_read_statusvector.sfu_ub_write_statusmte.aipp_dispatch_statusmte.aipp_img_ld_statusmte.aipp_read_req_statusmte.aipp_read_ack_statusmte.aipp_upsample_statusmte.aipp_dtc_statusmte.aipp_padding_statusmte.aipp_cpadding_statusmte.aipp_byte_align_statusmte.aipp_write_req_statuscube.cube_fp16_execcube.cube_int8_execvector.vec_fp32_execvector.vec_fp16_128lane_execvector.vec_fp16_64lane_execvector.vec_fp16_32lane_execvector.vec_int32_execvector.vec_misc_execscalar.flow_ctrl_execscalar.loop_execifu.icache_reqifu.icache_missifu.icache_preloadifu.icache_predict_pcifu.psq_ostd_full_statusscalar.scalar_waitflag_cyclesscalar.cube_waitflag_cyclesscalar.vec_waitflag_cyclesscalar.vec_v2_waitflag_cyclesscalar.mte1_waitflag_cyclesscalar.mte2_waitflag_cyclesscalar.mte3_waitflag_cyclesscalar.mte4_waitflag_cyclesscalar.mte5_waitflag_cyclesscalar.indir_jump_instrscalar.mispredicted_instrvector.psq_loop_buf_ld_instr_numvector.psq_loop_buf_exe_instr_numvector.psq_loop_buf_st_instr_numvector.psq_loop_buf_ld_send_isa_stavector.psq_loop_buf_ld_send_isa_numvector.psq_loop_buf_exe_send_isa_stavector.psq_loop_buf_exe_send_isa_numvector.psq_loop_buf_st_send_isa_stavector.psq_loop_buf_st_send_isa_numvector.psq_vf_pcvector.psq_vld_iter0_sizevector.psq_vexe_iter0_sizevector.psq_vst_iter0_sizevector.psq_vld_iter1_sizevector.psq_vexe_iter1_sizevector.psq_vst_iter1_sizevector.psq_vld_iter2_sizevector.psq_vexe_iter2_sizevector.psq_vst_iter2_sizevector.psq_vld_iter3_sizevector.psq_vexe_iter3_sizevector.psq_vst_iter3_sizevector.psq_fetch_instr_stavector.psq_fetch_instr_numscalar.scalar_div_execscalar.scalar_div_statusscalar.scalar_div_cyclesscalar.scalar_mult_execscalar.scalar_madd_execvector.rd_bankgroup_stall_statusvector.rd_bankgroup_stall_cyclesvector.wr_bankgroup_stall_statusvector.wr_bankgroup_stall_cyclesvector.vec_l0c_rd_stall_statusvector.vec_l0c_rd_stal_cyclesvector.vec_l0c_wr_stall_statusvector.vec_l0c_wr_stall_cyclesvector.vec_resc_conflict_statusvector.vec_resc_conflict_cyclesscalar.mte1_iq_full_statusscalar.mte1_iq_full_cyclesscalar.mte2_iq_full_statusscalar.mte2_iq_full_cyclesscalar.mte3_iq_full_statusscalar.mte3_iq_full_cyclesscalar.mte4_iq_full_statusscalar.mte4_iq_full_cyclesscalar.mte5_iq_full_statusscalar.mte5_iq_full_cyclesscalar.cube_iq_full_statusscalar.cube_iq_full_cyclesscalar.vec_iq_full_statusscalar.vec_iq_full_cyclesscalar.ccu_wait_instr_statusscalar.ccu_wait_instr_cyclesscalar.ccu_pipe_stall_statusscalar.ccu_pipe_stall_cyclesscalar.single_issue_statusscalar.single_issue_cyclesscalar.dual_issue_statusscalar.dual_issue_cyclesscalar.scalar_only_statusscalar.scalar_only_cyclescube.cube_l0c_stallvector.rd_bank_stall_statusvector.rd_bank_stall_cyclesvector.wr_bank_stall_statusvector.wr_bank_stall_cyclesvector.st_reg_port_stall_statusvector.st_reg_port_stall_cyclesvector.ld_back_pressure_statusvector.ld_back_pressure_cyclesvector.st_back_pressure_statusvector.st_back_pressure_cyclesbiu.biu_read_port0_latencybiu.biu_read_port1_latencybiu.biu_write_port0_latencybiu.biu_write_port1_latencybiu.biu_read_outstandingbiu.biu_write_outstandingbiu.biu_read_l2_bandwidthbiu.biu_write_l2_bandwidthbiu.biu_read_ddr_bandwidthbiu.biu_write_ddr_bandwidthscalar.mte1_iq_instr_numscalar.mte2_iq_instr_numscalar.mte3_iq_instr_numscalar.mte4_iq_instr_numscalar.mte5_iq_instr_numscalar.cube_iq_instr_numscalar.vec_iq_instr_nummte.fmc_work_cyclemte.fmc_idle_cyclemte.fmd_work_cyclemte.fmd_idle_cyclemte.mte_fmc_input_vldmte.mte_fmc_output_vldmte.mte_fmd_input_vldmte.mte_fmd_output_vldmte.mte_dcache_read_out_cyclesbiu.biu_busy_cyclemte.unzip instr event.A18sc_trace_file_baseopen_fpconst toml::Value* toml::Value::findChild(const string&) const@ -+   sc_trace_file_base.ccint%d-%d-%d%nInvalid token%d:%d:%lf%n%c%d:%dUnknown ident: [%s] %s:%d %s File path %s do not exist. _wave.vcdw[%s] %s:%d %s open file %s failed [%s] %s:%d %s Update file [%s] authority failed. %b %d, %Y %H:%M:%SProject.vcd_versionlog.flush_level14vcd_trace_file9vcd_trace14vcd_bool_trace18vcd_uint32_t_trace18vcd_uint64_t_trace15vcd_float_trace16vcd_double_traceprint_variable_declaration_linecompose_data_linewrite_commentobtain_namesummary_log@ -+   r%.16g %s'' has 0 bits$var %s % 3d %s %s $end sc_vcd_trace.cc$var %s % 3d %s %s [%d:0] $end [%s] %s:%d %s copy data from vcd_name to compdata failed, errno_t: %d. b%s %sbasic_string::substr%s: __pos (which is %zu) > this->size() (which is %zu)$scope module %s $end $upscope $end vcd[%s] %s:%d %s fp is nullptr $comment $end #%c%c%c%c%c_summary_log----------------------------- AiCore Summary Log ----------------------------- ============================================================================== kernal case name : %s kernal total ticks : %u system total ticks : %u Trace_Name | Total_Num %-44s| +++++++++++++++++++++ core: %d, tick: %d, kernal %d done +++++++++++++++++++++ AiCore$date %s $end vcd_version : $version %s%d $end 1 tick$timescale %s $end $enddefinitions $end all initial values are dumped below at time : tick = $dumpvars $end wirerealconst toml::Value* toml::Value::findChild(const string&) const@ add_trace_listinitial-+   trace.ccsystem.tickmem_bandwidth.tracearithmatic_throughput.traceflow_control.tracescalar_pipeline.tracestall_conditions.tracehistogram.traceinstructions.tracecontd_tri.scalar_busy_cycleProject.pathtick_tri.start_trace_ticktick_tri.end_trace_ticktick_tri.gap_trace_tickaicore_trace_enable.tracesummary_log_enable.enable4Dumpconst toml::Value* toml::Value::findChild(const string&) const@ setConfig 0@P`p 0@B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                   -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             *ZN4DumpD4EvEUlSt10shared_ptrIN13ascend_spdlog6loggerEEE_logdump.ccbasic_string::_S_construct null not valid CUBE_PORT VECTOR_PORTCUBE_PORTMTE_PORTNORMALBARRINGWAIT_SYNC_EVENTENDDMAC_L4_PIPEDMAC_L5_PIPEVECTOR_PIPE_V2REQUESTDATAconfig.tomlWARNING[%s] %s:%d %s config.toml cannot found, SIM.rotating of log use default value [%s] %s:%d %s cannot open %s instr_logcube_logvector_logscalar_logccu_loglsu_logrob_logbiu_stall_logmte_biu_req_logmte_biu_resp_logmte_rob_usage_logunzip_logfmd_logfmc_logmte_status_logbuffer_logrd_buffer_logparameter_rd_logparameter_wr_logl0a_rd_logl0a_wr_logl0b_rd_logl0b_wr_logl0c_rd_logl0c_wr_logub_rd_logub_wr_logl1_rd_logl1_wr_logbiu_logbiu_result_logbiu_rd_data_loginstr_popped_logub_logbank_conflict_logissque_logicache_logbp_logbuffer_op_logdcache_logbuffer_pingpong_conflict_logreg_logvec_icache_logl1_logaipp_logvector_reg_logmte_logSIM.rotating_file_sizeSIM.rotating_file_number[{0:08d}](PC: 0x{1:08x}) {2:s} : (Binary: 0x{3:08x}) {4:s} [{0:08d}](PC: 0x{1:08x}) {2:s} : (Binary: 0x{3:08x}) {4:s} Bank conflict RD({5:d}) WR({6:d})[{0:08d}](PC: 0x{1:08x}) {2:s} : (Binary: 0x{3:08x}) {4:s} Bank conflict RD({5:d}) WR({6:d}), WrCubelock wait({7:d}))[{0:08d}](PC: 0x{1:08x}){2:s} : (Binary: 0x{3:08x}) {4:s} start_cycle({5:d}) end_cycle({6:d})tick: {0:08d}tick: {0:d}, LSU_OUT_burst_length: {1:d}. Address: 0x{2:x}tick: {0:d}, LSU_IN_burst_length: {1:d}. Address: 0x{2:x}{0:d} {1:d} {2:d} 0x{3:x} tick: {0:d}, MTE RD ROB. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, READ_BIU_ADDR: 0x{5:08x}tick: {0:d}, MTE SEND BIU RD REQ. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, READ_ADDR: 0x{5:08x}, AXI: {6:d}.tick: {0:d}, MTE SEND BIU WR REQ. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, WRITE_ADDR: 0x{5:08x}, AXI: {6:d}.tick: {0:d}, MTE RECIEVE BIU RD RESP. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, READ_ADDR: 0x{5:08x}, AXI: {6:d}.tick: {0:d}, MTE RECIEVE BIU WR RESP. TAGID: {1:d}, UOPID: {2:d}, INSTRID: {3:d}, DATA_SIZE: {4:d}, WRITE_ADDR: 0x{5:08x}, AXI: {6:d}.tick: {0:d}, MTE LOWER ROB IS INCREASED BY: {1:d} B, REMAINING: 0x{2:x}.tick: {0:d}, MTE LOWER ROB IS DECREASED BY: {1:d} B, REMAINING: 0x{2:x}.tick: {0:d}, MTE HIGHER ROB IS INCREASED BY: {1:d} B, REMAINING: 0x{2:x}.tick: {0:d}, MTE HIGHER ROB IS DECREASED BY: {1:d} B, REMAINING: 0x{2:x}.memcpy_s error !tick: {0:d}, Cube_conflict_stage {1:d}.tick: {0:d}, BIU_Read_Req_Num: {1:d}.tick: {0:d}, BIU_Write_Req_Num: {1:d}.tick: {0:d}, unzip engine: {1:d} in working statustick: {0:d}, unzip engine: {1:d} in idle statustick: {0:d}, unzip engine: {1:d} in stall statustick: {0:d}, fmd engine: {1:d} in working statustick: {0:d}, fmd engine: {1:d} in idle statustick: {0:d}, fmd engine: {1:d} in stall statusFMC block compression fail. Inst ID: {0:d}, Block ID: {1:d}, Total: {2:d}tick: {0:d}, {1:s} is busy.current_tick: {0:d}.tick: {0:d}, BIU_RD_TAG_ID_USED_UPtick: {0:d}, BIU_ROB_FULLtick: {0:d}, BIU_RD_OTSD_FULLYtick: {0:d}, BIU_WR_TAG_ID_USED_UPtick: {0:d}, BIU_WR_BUSYtick: {0:d}, BIU_WR_OTSD_FULLYtick: {0:d}, L2_BIU_OUT_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, SYSCACHE_BIU_OUT_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, DDR_BIU_OUT_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, L2_BIU_IN_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, SYSCACHE_BIU_IN_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, DDR_BIU_IN_data_length: {1:d}, Address: 0x{2:x}.tick: {0:d}, Mac_Usage: {1:f} I1-I6 Usage: {2:f} WR1-WR3 Usage: {3:f}.tick: {0:d}, Dma_Usage, Mac_Usage: {1:f} I1-I6 Usage: {2:f} WR1-WR3 Usage: {3:f}.tick: {0:d}, Mac_Usage: {1:f}.tick: {0:d}, Cube_conflict_stage {1:s}.tick: {0:d}, {1:s}, {2:s}.tick: {0:d}, {1:s} pc: 0x{2:08x}.tick: {0:d}, {1:s}, write: addr: 0x{2:x}, size: {3:d}.tick: {0:d}, {1:s}, Read_request: addr: 0x{2:x}, port: 0x{3:x}.tick: {0:d}, {1:s}, Write_request: addr: 0x{2:x}, port: 0x{3:x}.tick: {0:d}, {1:s}, Partial_write_request: addr: 0x{2:x}, port: 0x{3:x}.[{0:08d}]({1:s}): STATUS EXECUTE : {2:s} change into {3:s}, Trigger pipe is {4:s}[{0:08d}]({1:s}): STATUS RESUME : {2:s} change into {3:s}[{0:08d}]({1:s}): POP STALL : (PC: 0x{2:08x}), (Binary: 0x{3:08x}) {4:s} [{0:08d}] EVENT QUEUE ADD SET FLAG HAZARD: SRC_PIPE:{1:s} DST_PIPE:{2:s} EVENT_ID:{3:d} WAITTING_RETIRE_NUM : VEC0:{2:d} | VEC1:{3:d} | MTE1:{4:d} | MTE2:{5:d} | MTE3:{6:d} | MTE4:{7:d} | MTE5:{8:d} | CUBE:{9:d}[{0:08d}]({1:s}): status is {2:s}[{0:08d}] event: src pipe is {1:s}, dst pipe is {2:s}, id is {3:d}, num is {4:d}[{0:08d}]: cache read address is 0x{1:08x}, size is 0x{2:08x}, status is {3:s}[{0:08d}]: cache refill request, id is 0x{1:08x}, address is 0x{2:08x}[{0:08d}]: cache refill acknowledge, id is 0x{1:08x}, address is 0x{2:08x} [{0:08d}]: icache load data is 0x{1:08x}[{0:08d}]: predictor sucessful, branch result is 0x{1:08x}, pht index is {2:d}[{0:08d}]: predictor fail, branch result is 0x{1:08x}, pht index is {2:d}tick: {0:d}, {1:s}, Read_pingpong_conflict: addr: 0x{2:x}, size: {3:d}, instr id: {4:d}.tick: {0:d}, {1:s}, Write_pingpong_conflict: addr: 0x{2:x}, size: {3:d}, instr id: {4:d}.[{0:08d}]({1:s}): status is {2:s}, source pipe is {3:s}readwritetick: {0:d}, Switch {1:s} {2:s}tick: {0:d}, PC: 0x{1:08x} {2:s} {3:s} {4:s}, Id: {5:d}[{0:08d}] SET_EVENT ------ SRC_PIPE ----- DST_PIPE ----- EVENT_ID ----- NUM[{0:08d}] WAIT_EVENT ----- SRC_PIPE ----- DST_PIPE ----- EVENT_ID ----- NUM # {0:15s}{1:15s}{2:d}{3:15d}tick: {0:08d} {1:s} {2:s} Address {3:08x} size {4:d}tick: {0:08d} {1:s}PARA_BUFFERtick: {0:08d} {1:s}:{2:04d}tick: {0:d}, {1:s}, Read_bank_conflict: addr: 0x{2:x}, size: {3:d}.tick: {0:d}, {1:s}, Write_bank_conflict: addr: 0x{2:x}, size: {3:d}.tick: {0:d}, {1:s}, Partial_write_bank_conflict: addr: 0x{2:x}, size: {3:d}.++++++++++++++++++++++core: {0:d}, tick: {1:d}, kernal{2:d} done++++++++++++++++++++++. B=ZN9BasicCube19dw_calculateB8toS32IhaEEvRK23tag_depthwise_conv_infojjEUlPhE_ZN9BasicCube19dw_calculateB8toS32IaaEEvRK23tag_depthwise_conv_infojjEUlPaE_ZN9BasicCube19dw_calculateB8toS32IhhEEvRK23tag_depthwise_conv_infojjEUlPhE_ZN9BasicCube21mmad_calculateB8toS32IsaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_ZN9BasicCube21mmad_calculateB8toS32IsaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_ZN9BasicCube21mmad_calculateB8toS32IssEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_ZN9BasicCube21mmad_calculateB8toS32IssEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_ZN9BasicCube21mmad_calculateB8toS32IhaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_ZN9BasicCube21mmad_calculateB8toS32IhaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_ZN9BasicCube21mmad_calculateB8toS32IhhEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_ZN9BasicCube21mmad_calculateB8toS32IhhEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_ZN9BasicCube21mmad_calculateB8toS32IaaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_ZN9BasicCube21mmad_calculateB8toS32IaaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_9BasicCubeSt23_Sp_counted_ptr_inplaceISt5dequeISt10shared_ptrI11CubeIsaInfoESaIS3_EESaIS5_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9EventElmtSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13CubePipeSliceSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIbSaIbELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11CubeIsaInfoSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IaaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IaaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IhhEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IhhEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IhaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IhaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IssEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IssEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IsaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPtZN9BasicCube21mmad_calculateB8toS32IsaEEvR13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPhZN9BasicCube19dw_calculateB8toS32IhhEEvRK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPaZN9BasicCube19dw_calculateB8toS32IaaEEvRK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt19_Sp_counted_deleterIPhZN9BasicCube19dw_calculateB8toS32IhaEEvRK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9WINO_CONVSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE*ZN9BasicCube24mmad_calculatefp16tofp16ER13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_*ZN9BasicCube24mmad_calculatefp16tofp16ER13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_*ZN9BasicCube24mmad_calculatefp16tofp32ER13cube_fsm_paraP18tag_cube_exec_infoEUlPtE_*ZN9BasicCube24mmad_calculatefp16tofp32ER13cube_fsm_paraP18tag_cube_exec_infoEUlPtE0_*ZN9BasicCube16arrange_matrix_aER13cube_fsm_paraP18tag_cube_exec_infoEUlPhE_*ZN9BasicCube13read_matrix_cER13cube_fsm_paraP18tag_cube_exec_infoEUlPhE_*ZN9BasicCube17dw_conv_apply_memER23tag_depthwise_conv_infoEUlPtE_*ZN9BasicCube17dw_conv_apply_memER23tag_depthwise_conv_infoEUlPtE0_*ZN9BasicCube18dw_conv_read_mat_aER23tag_depthwise_conv_infoEUlPhE_*ZN9BasicCube18dw_conv_read_mat_bER23tag_depthwise_conv_infoEUlPtE_*ZN9BasicCube20dw_calculateF16toF16ERK23tag_depthwise_conv_infojjEUlPtE_*ZN9BasicCube20dw_calculateF16toF32ERK23tag_depthwise_conv_infojjEUlPtE_*ZN9BasicCube19read_fifo_conv_calcEP18tag_cube_exec_infoR13cube_fsm_paraEUlPhE_decodeB8U2toB8arrange_matrix_a_normal_modearrange_matrix_a_gemv_modearrange_matrix_b_b8_fp16decodeU2toFp16getB8U2opcodeuint32_t ceil_divide_u32(uint32_t, uint32_t)mmul_stage_exc_start@ arrange_matrix_areadDatareadDatareadDatascatteReadData get_r_b_info_normal_typeread_fifo_conv_calc             ????????? ?          -+   read_matrix_a_GEMM_moderead_matrix_cread_matrix_a_GEMV_modedw_conv_read_mat_bmmad_calculateB8toS32mmad_calculateB8toS32mmad_calculateB8toS32mmad_calculateB8toS32mmad_calculateB8toS32mmad_calculatefp16tofp16mmad_calculatefp16tofp32update_pipeline_stagepop_instrtickdw_conv_stage_write_l0cdw_copy_mat_adw_calculateF16toF16dw_calculateF16toF32dw_calculateB8toS32dw_calculateB8toS32dw_calculateB8toS32*St19_Sp_counted_deleterIPtZN9BasicCube24mmad_calculatefp16tofp16ER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube24mmad_calculatefp16tofp16ER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube24mmad_calculatefp16tofp32ER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube24mmad_calculatefp16tofp32ER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN9BasicCube16arrange_matrix_aER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN9BasicCube13read_matrix_cER13cube_fsm_paraP18tag_cube_exec_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube17dw_conv_apply_memER23tag_depthwise_conv_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube17dw_conv_apply_memER23tag_depthwise_conv_infoEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN9BasicCube18dw_conv_read_mat_aER23tag_depthwise_conv_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube18dw_conv_read_mat_bER23tag_depthwise_conv_infoEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube20dw_calculateF16toF16ERK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPtZN9BasicCube20dw_calculateF16toF32ERK23tag_depthwise_conv_infojjEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN9BasicCube19read_fifo_conv_calcEP18tag_cube_exec_infoR13cube_fsm_paraEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE[error] issue_q_ nullptr[error] pmu_ nullptrdw_get_row_val : h: 0x{0:x}, w: 0x{1:x}, ch: 0x{2:x}, pos_src: 0x{3:x}, value: 0x{4:x}, instr name: {5:s}, instr id: {6:d},CUBE::dw_calculateB8toS32:sMaskOffset == {0:d}: sMask_addr: {1:d}, sMask_value: {2:d}, channel: {3:d}, bias: {4:d}.CUBE::dw_calculateB8toS32:i == {0:d}: j: {1:d}, ch: {2:d}, mat_c_pos: {3:d}, mat_c_value: {4:08x}.CUBE::dw_conv_padding_mat_a:mat_a_arr_pos: 0x{0:x}, padding_val: 0x{1:x}.cube get_row_col_in_frac_mtx: none zero number should no more than cube size.instr: {0:s} id: {1:d}back to back wino_conv:{0:d} null isa:{1:d}, cube queue empty:{2:d}, cur_tick: {3:d}isInstrSmallerThanOne16x16Matrx or two adjacent depthwise_convwaiting_sync_pulseimmediate set waitbasic_cube.cc[%s] %s:%d %s unexpected u2_num when low_pre_tbl == 3. [%s] %s:%d %s unexpected u2_num. [%s] %s:%d %s unexpected low_pre_tbl 62:63 value. b != 0 && (a + b > a)[%s] %s:%d %s tick: %x, uop_index: %x, matrix_piped_cycle: %x. [error] wrong data type! small k only support integer. [error] wrong data type! sparse mode does not support s4. dpw_fifo nullptr!pmu_ nullptr![%s] %s:%d %s mem alloc out of range [%s] %s:%d %s l0_b_round = 0x%x is larger than l0b size. error k length = , is not c0 aligncube instr: {0:s} Id: {1:d} calculate fp16 to fp32 input is NaN.cube instr: {0:s} Id: {1:d} calculate fp16 to fp32 input is inf.cube instr: {0:s} Id: {1:d} calculate fp16 to fp16 input is NaN.cube instr: {0:s} Id: {1:d} calculate fp16 to fp16 input is inf.CUBE {0:s}: l0b addr out of range, instr id: {1:d}CUBE {0:s}: l0a addr out of range, instr id: {1:d}CUBE {0:s}: l0c addr out of range, instr id: {1:d}CUBE {0:s}: l0B addr out of range, instr id: {1:d}Error! cube:is_set_legal : winograd and small-K mode can not work together instr: {0:s} id: {1:d}Error! cube:is_set_legal : winograd and offset mode can not work togetherinstr: {0:s} id: {1:d}Error! cube:is_set_legal :sparse and SPR_LOW_PRE_TBL[63:62] == 2'b11 can not work together, when data type == b8u2.instr: {0:s} id: {1:d}Error! cube:is_set_legal : offset and SPR_LOW_PRE_TBL[63:62] == 2'b11 can not work together, when data type == b8u2.instr: {0:s} id: {1:d}CUBE: dw_conv_read_info Error, ret = {0:x}. dw_conv_apply_mem: Error, ret = {0:d}. dw_conv_read_mat_a: Error, ret = {0:d}. vdrop_counter_ nullptr tick: {0:d}, reached_vdrop_interval.tick: {0:d}, en_vdrop.tick: {0:d}, en_check_sync_p.set flag exe: tick: {0:d} wait flag exe: tick: {0:d} tick: {0:d} enable_nop_counter: cube_dummpy_cyclecube_nop_cyclevector_writel0c_bp_stallunexpected cube instr opcode[%s] %s:%d %s cube_busy_cnt is nullptr! tick: {0:d} pipeline content: stage: {0:d}; count: {1:d}; pc: {2:x};cube hset_wait stall cur_tick: {0:d}, instr:{1:s}, id:{2:d}.fsm ****write c cur_tick: {0:d}, c_col_continue_index: {1:d}wino conv fsm read c cur_tick: {0:d}, c_col_continue_index: {1:d}fsm ****** read a cur_tick: {0:d}, a_col_continue_index: {1:d}****fsm read b cur_tick: {0:d}, b_col_continue_index: {1:d}fsm read c cur_tick: {0:d}, c_col_continue_index: {1:d}l0c write: set_unit_flag: {0:d}CUBE::dw_conv_stage_write_l0c gen addr: uop_index = {0:d}, offset_frac = {1:d}, addr_tmp = 0x{2:x}, size_tmp = 0x{3:x}, i = {4:d}CUBE::dw_conv_stage_write_l0c copy data: uop_index = {0:d}, offset_frac = {1:d}, pos_dst = 0x{2:x}, pos_src = 0x{3:x}, i = {4:d}CUBE::dw_conv_read_mat_a:i: {0:d}, j: {1:d}, mat_a_arr_pos: {3:d}, data: 0x{4:x}.CUBE::dw_copy_mat_a: pos_fm_wh: 0x{0:x}, pos_mat_a: 0x{1:x}, instr name: {2:s}, instr id: {3:d},CUBE::dw_calculateF16toF16:i == {0:d}: j: {1:d}, ch: {2:d}, mat_c_pos: {3:d}, mat_c_value: {4:08x}.CUBE::dw_calculateF16toF32:i == {0:d}: j: {1:d}, ch: {2:d}, mat_c_pos: {3:d}, mat_c_value: {4:08x}.get_data_in_result_q: c_index_N:{0:d} c_index_K: {1:d} offset: {2:d} index_in_res: {3:d} cur_tick(): {4:d}dw_conv_read_info: isa is nullptr. dw_conv_read_info: Error! W must equal to 16*N + 2, When padding disableinstr: {0:s} id: {1:d}CUBE::dw_conv_read_info: H: {0:d} W_ext: {1:d} conv_padding_ctrl: {2:d} mat_type: {3:d} sMask_addr: {4:d} f_ofst: {5:d} w_ofst: {6:d} a_w_size: {7:d} a_w_frac: {8:d} fm_w_size: {9:d} wino conv fsm write c cur_tick: {0:d}, c_col_continue_index: {1:d}, wc_para.M_frac_type: {2:d}, wc_para.K: {3:d}, wc_para.N_frac_type: {4:d}, uop_index: {5:d},dw_conv_stage_read_fifo: cubr_tick:{0:d}fsm read a cur_tick: {0:d}, last read: {1:d}, a_col_continue_index: {2:d}****fsm read b cur_tick: {0:d}, last read: {1:d}, b_col_continue_index: {2:d}wino_c_w_ack_stage: winograd_conv_q_.erase cur_tick:{0:d}, l0c_w_frac_index:{0:d}, a_row_frac:{0:d}, b_col_frac:{0:d}@             -+   basic_flowctrl_func.cc13BasicRegister16BasicGPRRegisterset_exception@ -+   scalar_read_registerscalar_write_registerbasic_gpr_register.cc[%s] %s:%d %s GPR is not supporting set_exception function. unknown registerNametick: {0:d}, read gpr reg: {1:d}, value: {2:x}tick: {0:d}, write gpr reg: {1:d}, value: {2:x}8BasicLSU@  0@P`p 0@            @                              @                                           ????????? ?                ( 0 8 @ H P X ` h p x  -+   basic_lsu.cc<jt|$.6>FPZb.uint32_t BasicMteDecode::get_field(uint64_t, uint32_t, uint32_t)@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   void BasicMteDecode::mvf_decode(std::shared_ptr)load_3d_decodemte_instr_decode14BasicMteDecodeSt23_Sp_counted_ptr_inplaceI10mte_info_tSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEvector::_M_insert_auxbasic_mte_decode.ccend <= 63sparse mode do not support B4 data type!MTE {0:s} Xm: sid: {1:d}, nd_num: {2:d}, n: {3:d}, d: {4:d}, src_nd_matrix_stride: {5:d}, Xt: src_D: {6:d}, dst_nz_C0_stride: {7:d}, dst_nz_n_stride: {8:d}, dst_nz_matrix_stride: {9:d}MTE {0:s} Xm: burst_num: {1:d}, burst: {2:d}, src_gap: {3:d}, dst_gap: {4:d}, pad_l: {5:d}, pad_r: {6:d}MTE: {0:s}: block number zero error. Id: {1:d}{0:s}: dst_addr = 0x{1:08x} not 512B align. Id: {2:d}{0:s}: dst_addr = 0x{1:08x} not 1024B align. Id: {2:d}{0:s}: src_addr = 0x{1:08x} not 32B align. Id: {2:d}{0:s}: dst_addr = 0x{1:08x} not 32B align. Id: {2:d}{0:s}: burst_num = 0. Id: {1:d}{0:s}: burst_len = 0. Id: {1:d}MTE {0:s} Xm: burst_num: {1:d}, burst: {2:d}, src_gap: {3:d}, dst_gap: {4:d}smask INDEX: src addr: 0x{0:08x} should be 2B aligned in biu port. Id: {1:d}smask INDEX: src addr: 0x{0:08x} should be 32B aligned in ub port. Id: {1:d}smask INDEX: dst addr: 0x{0:08x} should be 32B aligned. Id: {1:d}smask INDEX: dst addr: 0x{0:08x} is overflow. Id: {1:d}MTE {0:s}: src_addr: 0x{1:08x} overflow: 0x{2:08x}. Id: {3:d}depthwise: fm_h : {0:d} < 3. Id: {1:d}depthwise: fm_w : {0:d} is illegle when pad is disable. Id: {1:d}MTE {0:s} fmatrix: fm_w: {1:d}, fm_h: {2:d}, pad_l: {3:d}, pad_r: {4:d}, pad_t: {5:d}, pad_b: {6:d}load_3d:error padding = 0x{0:x} in B8 data type!{0:s}, src_addr: 0x{1:08x}, dst_addr: 0x{2:08x}, rd_p: {3:d}, wr_p: {4:d}{0:s}, --------------------, dst_addr: 0x{1:08x}, -------, wr_p: {2:d}MTE {0:s} Xm: c_dim_idx: {1:d}, fetch_pos_w: {2:d}, fetch_pos_h: {3:d}, filter_pos_w: {4:d}, filter_pos_h: {5:d}MTE {0:s} Xt: stride_w: {1:d}, stride_h: {2:d}, filter_w: {3:d}, filter_h: {4:d}, dilation_w: {5:d}, dilation_h: {6:d}, jump_offset: {7:d}, repeat_mode: {8:d}, repeat_times: {9:d}MTE {0:s} Xm: K_length: {1:d}, M_length: {2:d}, k_start: {3:d}, m_start: {4:d}MTE {0:s} Xt: stride_w: {1:d}, stride_h: {2:d}, filter_w: {3:d}, filter_h: {4:d}, dilation_w: {5:d}, dilation_h: {6:d}, chn_size: {7:d}MTE {0:s}: mte_err_illegal_k_m_start_pos k_start: {1:d}, c0: {2:d}. Id: {3:d}MTE {0:s}: mte_err_illegal_k_m_start_pos m_start: {1:d}. Id: {2:d}MTE {0:s}: mte_err_illegal_k_m_start_pos k_start: {1:d}, m_start: {2:d}. Id: {3:d}MTE {0:s}: mte_err_illegal_k_m_ext_step k_length: {1:d}, m_length: {2:d}. Id: {3:d}MTE {0:s}: dst_addr: 0x{1:08x} should be {2:d} byte align. Id: {3:d}MTE {0:s}: dst_addr: 0x{1:08x} overflow 0x{2:08x}. Id: {3:d}MTE: {0:s}: write addr wrap error. Id: {1:d}MTE: {0:s}: ub read addr wrap error. Id: {1:d}MTE {0:s}: src_addr: 0x{1:08x} should be {2:d} byte align. Id: {3:d}MTE {0:s}: index_addr: 0x{1:08x} should be {2:d} byte align. Id: {3:d}{0:s}: index_num = 0. Id: {1:d}MTE {0:s}: src_addr: 0x{1:08x} should be 32 byte align. Id: {2:d}MTE {0:s}: dst_addr: 0x{1:08x} should be 512 byte align. Id: {2:d}MTE {0:s}: mte_illegal_fm_size: fm_w:{1:d}, fm_h:{2:d}. Id: {3:d}MTE {0:s} Xm: fm_w: {1:d}, fm_h: {2:d}, channel_size: {3:d}, pad_l: {4:d}, pad_r: {5:d}, pad_t: {6:d}, pad_b: {7:d}MTE {0:s} Xt: k_step: {1:d}, k_start: {2:d}, m_step: {3:d}, m_start: {4:d}MTE {0:s}: mte_fpos_larger_fsize: fetch_pos_w:{1:d}, fetch_pos_h:{2:d}, filter_w:{3:d}, filter_h:{4:d}. Id: {5:d}MTE {0:s}: mte_fmapwh_larger_l1size: fm_w:{1:d}, fm_h:{2:d}, c_index:{3:d}. Id: {4:d}MTE {0:s}: mte_cidx_overflow: fm_w:{1:d}, fm_h:{2:d}, c_index:{3:d}. Id: {4:d}MTE {0:s}: mte_fmap_less_kernel. Id: {1:d}MTE {0:s}: mte_f1wpos_larger_fsize. Id: {1:d}MTE {0:s}: dst_addr: 0x{1:08x} should be 32 byte align. Id: {2:d}{0:s}: src_addr = 0x{1:08x} not {2:d}B align. Id: {3:d}MTE {0:s} Xm: Ci: {1:d}, Ni: {2:d}, Nb: {3:d}, type_mode: {4:d} #+k3[K;{SC[cs__dmac_split__dmac_brc__dmac_brc_conv__dmac_paddinguint32_t BasicMteExecute::get_field(uint64_t, uint32_t, uint32_t)__mov_pad__mov_pad__mov_pad@ move_data_opt2 void BasicMteExecute::nznd_move(std::shared_ptr, Coord)mov_smask_executeload_fbuf_datavoid BasicMteExecute::mvf_execute(std::shared_ptr)dmac_mov_dataload3d_read_datawinograd_a_read_datawinograd_a_read_datawinograd_a_read_data 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   dcmp_blockget_cycle_matrixdecompress_cycle_matrix15BasicMteExecuteSt23_Sp_counted_ptr_inplaceI13load3d_data_tSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEbasic_mte_execute.ccvector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)isa_para->read_size == isa_para->write_sizeERROR DMA INSTR INFOERROR BRC INSTR INFOMTE: {0:s}: decompress len less errorMTE: {0:s}: decompress len over/less error{:s}:{:d}:{:s} mte unzip isa :unit line length and data type shoule be the same{:s}:{:d}:{:s} mte unzip isa :ori matrix length should be 512 byte aligned{:s}:{:d}:{:s} mte unzip isa :ori matrix length should be smaller than 32KB{:s}:{:d}:{:s} mte unzip isa :cycle matrix uncompress is only supportted in mini and lite version{:s}:{:d}:{:s} memset_s failed, err = {:d}.error instr for mteWINOGARD SRC IS INF: SRC = 0x{0:x}WINOGARD SRC IS NAN: SRC = 0x{0:x}11BasicScalarSt23_Sp_counted_ptr_inplaceI15BasicScalarFuncSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17BasicFlowCtrlFuncSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEcheck_fp_status@  0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          void BasicScalar::updateMultiCyclePipe(std::vector >*)-+   void BasicScalar::updateAluPipe()basic_scalar.cc[%s] %s:%d %s Scalar: pc: 0x%x, instr %s overflow. [%s] %s:%d %s Scalar: pc: 0x%x, instr %s underflow. [%s] %s:%d %s Scalar: pc: 0x%x, instr %s nan. [%s] %s:%d %s Scalar: pc: 0x%x, instr %s inf. alu_isa_ != nullptrtick {0:d}: SCALAR_EXE_UNIT_{1:d}: set alu wr skew, isa: {2:s}, pc: {3:x}.tick {0:d}: SCALAR_EXE_UNIT_{1:d}: set early instr not wb, isa: {2:s}, pc: {3:x}, xd: {4:d}.tick {0:d}: SCALAR_EXE_UNIT_{1:d}: lsu skew to alu0 instr, isa: {2:s}, pc: {3:x}, src_reg: x{4:d}, skew_gpr_value: 0x{5:x}.tick {0:d}: SCALAR_EXE_UNIT_{1:d}: skew to alu instr, isa: {2:s}, pc: {3:x}, src_reg: x{4:d}, skew_gpr_value: 0x{5:x}.tick {0:d}: SCALAR_EXE_UNIT_{1:d}: set flowctrl instr skew, isa: {2:s}, pc: {3:x}, skew_spr_value: 0x{4:x}.flowctrl_isa_ != nullptrtick {0:d}: SCALAR_EXE_UNIT_{1:d}: alu wr skew, skew_reg: {2:x}, skew_value: 0x{3:x}.SCALAR: {0:s}: ccu_neg_sqrt. Negative number in sqrt instruction. pc: {1:x}SCALAR: {0:s}: ccu_div0. Divisor == 0 is division. pc: {1:x}tick {0:d}: SCALAR_EXE_UNIT_{1:d}: set fpu instr not wb, isa: {2:s}, pc: {3:x}, xd: {4:d}.tick {0:d}: SCALAR_EXE_UNIT_{1:d}: set alu instr not wb, isa: {2:s}, pc: {3:x}.SCALAR FLUSHEDtick {0:d}: SCALAR_EXE_UNIT_{1:d}: mis-predict flush scalar instr, isa: {2:s}, pc: {3:x}.basic_scalar_addbasic_scalar_subbasic_scalar_mulbasic_scalar_maddbasic_scalar_absbasic_scalar_divbasic_scalar_modbasic_scalar_sqrtbasic_scalar_negbasic_scalar_maxbasic_scalar_minbasic_scalar_cmp_s64basic_scalar_cmp_u64basic_scalar_cmp_f32basic_scalar_cmpn_f32basic_scalar_selbasic_scalar_andbasic_scalar_orbasic_scalar_xorbasic_scalar_notbasic_scalar_shlbasic_scalar_shrbasic_scalar_sbcntbasic_scalar_sff_b64basic_scalar_clzbasic_scalar_sflbitsbasic_scalar_sbitsetbasic_scalar_signextbasic_scalar_zeroextbasic_scalar_convbasic_scalar_cmp_imm12@             -+   basic_scalar_func.cc[%s] %s:%d %s op type errors [%s] %s:%d %s op errors [%s] %s:%d %s scalar conv not support conv type: %lx. 14BasicScalarLsumergeDatamergeDatamergeDatamergeDatadivideDatadivideDatadivideDatadivideData@  0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          -+   basic_scalar_lsu.cctick: {0:d}, CCU_LSU ld_st_bypass, isa: {1:s}, pc: {2:x}, src_reg: x{3:d}, skew_gpr_value: 0x{4:x}tick {0:d}: CCU_LSU wr skew, skew_reg: x{1:d}, skew_value: 0x{2:x}.tick {0:d}: CCU_LSU instr: {1:s}, pc: {2:x} before memory map decode, ldst addr: {3:x}. sys_va_base: {4:x}, stack_phy_base: {5:x}.tick {0:d}: CCU_LSU instr: {1:s}, pc: {2:x} push to S0 stage after memory map decode, ldst addr: {3:x}.tick {0:d}: CCU_LSU instr: {1:s}, pc: {2:x} unrecognize ldst addr. addr: {3:x}tick {0:d}: CCU_LSU instr: {1:s}, pc: {2:x} push to S0/M0 stage after memory map decode, ldst addr: {3:x}, is_sqcr: {4:x}, is_ub: {5:x}, is_ddr: {6:x}, is_stack: {7:x}.tick {0:d}: CCU_LSU: push to sequencer failed, ostd_hazd. cur_ostd_num: {1:d}.tick {0:d}: CCU_LSU: push to sequencer failed, ld_buf_size_hazd, cur_ld_ostd_num: {1:d}, cur_ld_buf_size: {2:d}.tick {0:d}: CCU_LSU: {1:s}, pc: {2:x} push to sequencer successed, request id: {3:d}.tick {0:d}: SCALAR LSU: {1:s}, pc: {2:x} push to sequencer failed.tick {0:d}: CCU_LSU: st pb fail, pb is full.tick {0:d}: CCU_LSU: {1:s}, pc: {2:x} M0 replay, request id: {3:d}.tick {0:d}: CCU_LSU: {1:s}, pc: {2:x} M0 pop, request id: {3:d}.tick {0:d}: CCU_LSU: {1:s}, pc: {2:x} push to dcache successed, request id: {3:d}.tick {0:d}: CCU_LSU: {1:s}, pc: {2:x} push to dcache failed.16BasicSPRRegistervector_write_registervector_read_registerset_exception@ -+   scalar_write_registerscalar_read_registerbasic_spr_register.cc[%s] %s:%d %s Model Interrupted by Exception. tick: {0:d}, write spr reg: {1:s}, {2:x}, value: {3:x}tick: {0:d}, read spr reg: {1:s}, {2:x}, value: {3:x}9BasicUnitwrite_gpr_registerwrite_spr_register nopqrstuvwxyz{|}~# read_spr_register@             ????????? ?          -+   basic_unit.ccN7aiv_vec16BasicVECRegisterESt23_Sp_counted_ptr_inplaceIN7aiv_vec10PHYSIC_REGESaIS1_ELN9__gnu_cxx12_Lock_policyE2EEvoid aiv_vec::PHYSIC_REG::write(std::vector*, uint32_t, uint32_t)writevoid aiv_vec::BasicVECRegister::record_rename_index(uint32_t)uint32_t aiv_vec::BasicVECRegister::get_rename_p_index(uint32_t, uint32_t)uint32_t aiv_vec::BasicVECRegister::SearchVregVidx(uint32_t)uint32_t aiv_vec::BasicVECRegister::SearchPregVidx(uint32_t)@ void aiv_vec::PHYSIC_REG::read(std::vector*, uint32_t, uint32_t)readwrite 0@P`p 0@B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                       -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             basic_vec_register.ccoffset + data_size <= lencannot find physical register index, index num is %u v_reg v_index = %u p_reg v_index = %u ERR V_reg v_index = %u ERR P_reg v_index = %u Vecotr_Reg_VPredicate_Reg_PWide_Vector_Reg_WAlignment_Reg_UIntegr_RegVector_Address_RegS_REG_A_REG_Switch {0:s}: value: 0x{1:x}PC: 0x{0:08x} {1:s} {2:s}, Id: {3:d}: value: 0x{4:x}11BasicVector@  0@P`p 0@                 @                              @                                      ( 0 8 @ H P X ` h p x        ????????? ?          -+   basic_vector.cc6CACube*ZN6CACube9apply_memEvEUlPhE_*ZN6CACube9apply_memEvEUlPhE0_*ZN6CACube9apply_memEvEUlPhE1_*ZN6CACube9apply_memEvEUlPhE2_*ZN6CACube9apply_memEvEUlPhE3_*ZN6CACube9apply_memEvEUlPhE4_*ZN6CACube9apply_memEvEUlPhE5_@ apply_mem             -+   *St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E0_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E1_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E2_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E3_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E4_SaIvELN9__gnu_cxx12_Lock_policyE2EE*St19_Sp_counted_deleterIPhZN6CACube9apply_memEvEUlS0_E5_SaIvELN9__gnu_cxx12_Lock_policyE2EEca_cube.cc@              -+   cube_fsm.cc cube : mmad_get_next_sta wrong cube fsm !wino_conv_r_fsm: uop:{0:d}, c_index:{1:d} last_rd:{2:d}wino_conv_w_fsm: uop:{0:d}, c_index:{1:d}mmad_fsm: uop:{0:d}, a_base_i_:{1:d}, b_base_i_:{2:d}, c_base_i_:{3:d}, a_i:{4:d}, b_i:{5:d}, c_i:{6:d}, r_a:{7:d}, r_b:{8:d}, r_c:{9:d}, w_c:{10:d}, m_fra_wid_:{11:d}, k_fra_wid_:{12:d}, n_fra_wid_:{13:d}, m_fra_ttl_:{14:d}, k_fra_ttl_:{15:d}, n_fra_ttl_:{16:d}, status:{17:d} last_rd_a:{18:d} last_rd_b:{19:d} last_rd_c:{20:d} stall:{21:d} last_row_c:{22:d} last_col_c:{23:d}$b\HB<4,, Tcheck_param@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   aipp_decoder.cc[%s] %s:%d %s ERROR: invalid padding parameter %d decode: decode_mte_ldimg: aipp_instr_id_: {0:d}, src_y_addr: 0x{1:x}, src_uv_addr: 0x{2:x}, dst_addr: 0x{3:x}, img_format: {4:s}, uni_chn: {5:d}, raw_bit_size: {6:d}, data_type: {7:s}, h_size: {8:d}, v_size: {9:d}, h_res: {10:d}, h_start_pos: {11:d}, v_start_pos: {12:d}, raw1to4: {13:s}, dma_buf_size: {14:d}, trans_size: {15:d}, pl_0_chn_num: {16:d}, in_chn_size: {17:d}, pl_1_chn_num: {18:d}, ch1_interval: {19:d}, pl_1_line_stride: {20:d}, pl_1_pixel_stride: {21:d}, pixel_size_in_l1: {22:d}, pl_0_pixel_size: {23:d}, pl_1_pixel_size: {24:d}, cur_h_size: {25:d}, cur_v_size: {26:d}, padding_mode: {27:s}, top_padding_size: {28:d}, bot_padding_size: {29:d}, left_padding_size: {30:d}, right_padding_size: {31:d}, csc_en: {32:d}, c_padding: {33:d}, single_line_mode: {34:d}, pad_h_size: {35:d}, pad_v_size: {36:d}, upsample_proc_pixels: {37:d}, csc_proc_pixels: {38:d}, dtc_proc_pixels: {39:d}, padding_proc_pixels: {40:d}, cpadding_proc_pixels: {41:d}, raw_to_f16_n: {42:d}, start_chan_num: {43:d}, output_4_chan: {44:d}, dst_stride: {45:d}, valid_chn_num: {46:d}, out_chn_size: {47:d}, uni_chn: {48:d}, bypass: {49:s}, SPLIT_RGGBSPLIT_RGBSPLIT_RXSPLIT_NOSPLIT_NUMF16S16FILLSINGLE_RCBLOCKMIRRORYUV420_U8XRGB_U8NC1HWC0_FP16NC1HWC0_S8RGB_U8ARGB_U8YUV422P_U8YUV422S_U8AYUV444_U8YUV400_U8RAW10RAW12RAW16RAW14RAW20RAW24*******RGB16RGB20RGB24RGB8_IRRGB16_IRRGB24_IRSt23_Sp_counted_ptr_inplaceISt6vectorI10AIPP_PIXELSaIS1_EESaIS3_ELN9__gnu_cxx12_Lock_policyE2EEprint_img_to_file@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   aipp_pv_func.cc llt/model/data/isg_data[%s] %s:%d %s File dir %s do not exist. %s/%s[%s] %s:%d %s sprintf_s print_img_to_file into compdata failed. %02x src.txtupsample.txtRDFC.txtCSC.txtU8Trans.txtPadding.txtCPadding.txt6CaAippSt23_Sp_counted_ptr_inplaceI13AIPP_ISA_INFOSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14biuReadUopTypeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_aipp.ccinit parms: mte_ldimg: push_aipp_cmd: mte_ldimg: tick: {0:d}, aipp_cmd_que_: {1:d}, retire instr: mte_ldimg: tick: {0:d}, isa_queue_: {1:d}, push biu: mte_ldimg: call push biu, tick: {0:d}, biu_data->dst_addr: 0x{1:x}, pl0_ping_buf_addr_uc_: 0x{2:x}, pl0_pong_buf_addr_uc_: 0x{3:x}, dma_buf_size: {4:d}, upsample0_buf_: {5:d}, upsample1_buf_: {6:d}, upsample2_buf_: {7:d}, upsample3_buf_: {8:d}, uni_chn: {8:d}, push biu: mte_ldimg: call push biu, tick: {0:d}, biu_data->dst_addr: 0x{1:x}, pl0_ping_buf_addr_uc_: 0x{2:x}, pl0_pong_buf_addr_uc_: 0x{3:x}, dma_buf_size: {4:d}, upsample0_buf_: {5:d}, uni_chn: {6:d}, push biu: mte_ldimg: call push biu, tick: {0:d}, buf_id0_que_: {1:d}, buf_id1_que_: {2:d}, dat_pl: 0x{3:d}, v_pos_: {4:d}, buf_id_que.size(): push biu: mte_ldimg: tick: {0:d}, pl_0_trans_: {1:d}, upsample0_buf_: {2:d}, pl_0_rcv_line_cnter_: {3:d}, pl_0_rcv_cnter_: {4:d}, pl_1_trans_: {5:d}, upsample1_buf_: {6:d}, upsample2_buf_: {7:d}, pl_1_rcv_line_cnter_: {8:d}, pl_1_rcv_cnter_: {9:d}, uni_chn: {10:d}, rd req: mte_ldimg: tick: {0:d}, rd_uops_: {1:d}, is_last: {2:d}, upsample: mte_ldimg: call upsample, tick: {0:d}, upsample0_buf_: {1:d}, upsample1_buf_: {2:d}, upsample_queue_: {3:d}, pl_0_rcv_line_cnter_: {4:d}, pl_0_rcv_cnter_: {5:d}sync_line_cnter_: {6:d}, sync_pixel_cnter_: {7:d}, upsample: mte_ldimg: tick: {0:d}, proc_pixels: {1:d}, avail_pixels: {2:d}, upsample0_buf_: {3:d}, upsample1_buf_: {4:d}, upsample_queue_: {5:d}, sync_line_cnter_: {6:d}, sync_pixel_cnter_: {7:d}, dtc: mte_ldimg: tick: {0:d}, dtc_queue_: {1:d}, padding_queue_: {2:d}, proc_pixels: {3:d}, out_pixels: {4:d}, upsample: mte_ldimg: tick: {0:d}, upsample_queue_: {1:d}, csc_queue_: {2:d}, out_pixels: {3:d}, in_pixels: {4:d}, csc: mte_ldimg: tick: {0:d}, csc_queue_: {1:d}, dtc_queue_: {2:d}, proc_pixels: {3:d}, in_pixels: {4:d}, out_pixels: {5:d}, padding: mte_ldimg: tick: {0:d}, padding_queue_: {1:d}, cpadding_uops_: {2:d}, rects: {3:d}, x: {4:d}, y: {5:d}, proc_pixels: {6:d}, in_pixels: {7:d}, padding_h_cnter_: {8:d}, padding_v_cnter_: {9:d}, cpadding: mte_ldimg: tick: {0:d}, cpadding_uops_: {1:d}, wr_uops_: {2:d}, proc_pixels: {3:d}, x: {4:d}, y: {5:d}, pixel_size: {6:d}, dst_stride_size: {7:d}, wr_size: {8:d}, wr_addr: 0x{9:x}, wr: mte_ldimg: tick: {0:d}, wr_uops_: {1:d}, aipp_instr_id_: {2:d}, wr_size: {3:d}, wr_addr: 0x{4:x}, wr_cnter_: {5:d}, is_last: {6:d}, build_rd_uop: mte_ldimg: tick: {0:d}, read_addr: 0x{1:x}, write_addr: 0x{2:x}, data_size: {3:d}, break_down_trans: mte_ldimg: tick: {0:d}, h_pos_: {1:d}, v_pos_: {2:d}, dat_begin_: {3:d}, size_: {4:d}, gen uops: mte_ldimg: tick: {0:d}, rd_uops_: {1:d}, pop instr: mte_ldimg: tick: {0:d}, aipp_cmd_que_: {1:d}, isa_queue_: {2:d}, 5CaLSUSt23_Sp_counted_ptr_inplaceI14BasicMteDecodeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15BasicMteExecuteSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13bwifSharedBufSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15variLatencyFifoSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11fmcd_para_tSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE*ZN5CaLSU14mte_port_writeESt10shared_ptrI10mte_info_tEmjPvS3_EUlPhE_@ build_config 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   *St19_Sp_counted_deleterIPhZN5CaLSU14mte_port_writeESt10shared_ptrI10mte_info_tEmjPvS5_EUlS0_E_SaIvELN9__gnu_cxx12_Lock_policyE2EEca_lsu.ccMTE, instr ID is: ca_lsu.cc:320, L1_3D_SIZE = 0ERROR SRC PORT!ERROR DST PORT!deque::_M_range_check: __n (which is %zu)>= this->size() (which is %zu)AIPP/UNZIP tick:{0:d}: {1:s}: addr = 0x{2:08x}, size = {3:x}, {4:s}, instr_id = {5:d}, retire_set = {6:d}10CaLsuBiuIFSt23_Sp_counted_ptr_inplaceI9mte_uop_tSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11brifUopArbiSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11bwifUopArbiSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI10AippBufferSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8CachePldSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@ @ void CaLsuBiuIF::get_data(bwif_arbi_t, uint32_t, uint64_t, uint8_t*, std::vector::iterator)gen_wr_reqreadbool bwifSharedBuf::read(uint32_t, uint8_t*, uint32_t)void variLatencyFifo::gen_gather_mode_req(uint32_t, uint64_t, std::vector::iterator)void CaLsuBiuIF::gen_scatte_wr_dst_uop(biuWrType&, LsuPortIndex) 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   void bwifUopArbi::exec_arbiter()void AippBuffer::pop()tick: {0:08d}: AIPP UV: TAG_ID: {1:d}, UOP_SIZE: {2:d}ca_lsu_biu_if.ccsize % 64 == 0ca_lsu_biu_if.cc:884, resp size = 0ca_lsu_biu_if.cc:641, CA MTE BIU IF: Error, wrong command generation state.biu rd interface error portscatter_remain_size_ % bwt.isa_para->burst == 0ca_lsu_biu_if.cc:1293, ERROR PORTca_lsu_biu_if.cc:1128, req size = 0tick: {0:d}, MTE BIU RD: INSTR_ID: {1:d}, DATA_SIZE: {2:d}, BASE_ADDR: 0x{3:08x}, TREAD_ID: {4:d}i != (uint32_t)bwif_arbi_t::PORT_NUMtick: {0:d}, MTE BIU WR: INSTR_ID: {1:d}, DATA_SIZE: {2:d}, BASE_ADDR: 0x{3:08x}, TREAD_ID: {4:d}tick: {0:d}, in_order_tag, otsd_num = {1:d}tick: {0:d}, outof_order_tag, otsd_num = {1:d}ca_lsu_biu_if.cc:467, CA MTE BIU IF: Error, wrong command generation state.tick: {0:d}, TAG_ID: {1:d}, INSTR_ID: {2:d}, TNX_ID: {3:d}, REMAIN: {4:d}tick: {0:d}. delete_fn_data_tn: tag_id: {1:d}, trans_id: {2:d}, cmd_id: {3:d}, ptr: {4:x}.tick: {0:08d}: AIPP UV REQ: DATA_SIZE: {1:d}, TAG_ID: {2:d}, RETIRE_SET: {3:d}, BUF_SIZE: {4:d}tick: {0:08d}: AIPP Y REQ: DATA_SIZE: {1:d}, TAG_ID: {2:d}, RETIRE_SET: {3:d}, BUF_SIZE: {4:d}tick: {0:d}, AIPP PING PONG BUFFER, AIPP CHN TYPE: {1:d}, INSTR_ID: {2:d}, RETIRE_SET: {3:d}tick: {0:d}, AIPP PUSH DATA, AIPP CHN TYPE: {1:d}, INSTR_ID: {2:d}, RETIRE_SET: {3:d}!aipp_tag_lut_[output_pnt].empty()tick: {0:d}, MTE2: {1:s} instr_id: {2:d}, release wait flag event id {3:d}, wait flag id: {4:d}tick: {0:d}, MTE2: {1:s} instr_id: {2:d}, backpressure by wait flag event id {3:d}, wait flag id: {4:d},,66@Jhpz@@hJ""&:>B..2&&*6wr_abi_t get_port(dmaCmdType)@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   12CmdSchedulerSt15_Sp_counted_ptrIP12cmdIssueTypeLN9__gnu_cxx12_Lock_policyE2EEca_lsu_cmd_scheduler.ccca_lsu_cmd_scheduler.cc: 617, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 632, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 648, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 669, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 684, ERROR CMD TYPE!ca_lsu_cmd_scheduler.cc: 692, AIPP IS nullptrca_lsu_cmd_scheduler.cc: 1019, WAIPP IS nullptrca_lsu_cmd_scheduler.cc: 459, ERROR CMD TYPE!. poped from IQca_lsu_cmd_scheduler.cc: 93, ERROR MTE INSTR!ca_lsu_cmd_scheduler.cc: 146, MTE CMDSCHEDULER: ERROR, UNKNOWN CMD TYPE!. pop success 18DepthWiseUopEngine@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_depthwise_uop_engine.cc12DmaUopEngine@ void DmaUopEngine::gen_src_to_out_uop(std::shared_ptr, std::shared_ptr, bool)void DmaUopEngine::dma_gather_mode(std::shared_ptr) 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_dma_uop_engine.ccDmaUopEngineerror src id! ERROR SRC PORTread_size == 128src_pipe == 313FmcdUopEngine@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_fmcd_uop_engine.ccFmcdUopEngineca_lsu_fmcd_uop_engine.cc: 269, req_size = {0:d} != resp_size = {1:d}12FmdUopEngine@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_fmd_uop_engine.ccFmdUopEngineca_lsu_fmd_uop_engine.cc: 94, fmd header is not emptyca_lsu_fmd_uop_engine.cc: 332, ERROR FMD DST PORT16Img2colUopEngine@ virtual void Img2colUopEngine::generateUop() 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_img2col_uop_engine.cc11CaInterface@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_interface.ccca_lsu_interface.cc: 77, mte uop t is nullptr!ca_lsu_interface.cc: 82, band width is 0!tick: {0:d}, fifo header id: {1:d}, execute instr id: {2:d}16KSparseUopEngine@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_ksparse_uop_engine.ccKSparseUopEngineSMASK WRITE13CaL0Interfacevoid CaL0Interface::mte1_l0a_hazard()void CaL0Interface::mte1_l0b_hazard()void CaL0Interface::mte2_l0b_hazard()void CaL0Interface::gen_l0a_write_abiter()void CaL0Interface::gen_l0b_write_abiter()@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_l0_interface.ccL0A WRITEL0B WRITELOC WRITEDEPTH WRITE{0:s}, no datatick: {0:d}, MTE1: instr_id: {1:d}, release set flag event id {2:d}13CaL1InterfaceSt15_Sp_counted_ptrIP15biuWriteUopTypeLN9__gnu_cxx12_Lock_policyE2EE@ void reqInfo::dec_count()void bwifSharedBuf::get_response(uint32_t)void bwifSharedBuf::req_grant(uint32_t) 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_l1_interface.ccL1 INTF: ERROR DST PORTaipp adapter error instr idL1 UB WRITEL1 BIU WRITEL1 UOP READL1 BIU READl1 interface ERROR WRITE PORT!12MvfUopEngineSt15_Sp_counted_ptrIP14biuReadUopTypeLN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_mvf_uop_engine.cc15PlanarUopEngine@ void PlanarUopEngine::__setl02d_send_uop() 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_planar_uop_engine.ccuop->vld_time >= 4ca_lsu_planar_uop_engine.cc:135, ERROR DST PORTca_lsu_planar_uop_engine.cc:162, ERROR INSTR IN UE2D=13CaUBInterfacevirtual bool CaUBInterface::fetch()@ void variLatencyFifo::dec_count(uint32_t)virtual void CaUBInterface::read() 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_ub_interface.ccowner_->ub_rd_crdt_ > 0UB BIU READiter->second > 0UB UOP READtick:{0:d}: UB READ RESP: {1:s}, instr_id = {2:d}ERROR WRITE PORT!UB WRITEUB WRITE SEND: tick: {0:d}, req_id = {1:d}UB WRITE GRANT: tick: {0:d}, req_id = {1:d}14UnzipUopEngineSt23_Sp_counted_ptr_inplaceI9uzpEngineSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI11uzpIdxTableSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEvoid uzpEngine::set_latency(UZP_FSM_STATE, std::string)@ bool UnzipUopEngine::fetch_ouput(uzp_uop_t&, LsuPortIndex) 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   void UnzipUopEngine::get_uzp_uop()void UnzipUopEngine::uzp_cmp_data()bool uzpIdxTable::mte_response(uint32_t)ca_lsu_unzip_uop_engine.ccUZP_BYPASSUZP_QUANTUZP_STRUZP_LOW_SPARSE_DICTUZP_HIGH_SPARSE_DICTUZP_LOW_SPARSEUZP_HIGH_SPARSEfalse && "unzip error dst id"UnzipUopEnginetick: {0:d}, UZP GET MTE RESP. INSTRID: {1:d}, DATA_SIZE: {2:d}, TAGID: {3:d}data_size < bwt.sizetick: {0:d}, UZP ENGINE REQ. INSTRID: {1:d}, DATA_SIZE: {2:d}, REQ_ID: {3:d}, RETIRE: {4:d}, STATUS: {5:s}tick: {0:d}, UZP ENGINE RESP. INSTRID: {1:d}, DATA_SIZE: {2:d}, REQ_ID: {3:d}, RETIRE: {4:d}, STATUS: {5:s}tick: {0:d}, UZP ENGINE OUT. INSTRID: {1:d}, DATA_SIZE: {2:d}, REQ_ID: {3:d}, RETIRE: {4:d}false && "error uzp status"tick: {0:d}, UZP IDX GET MTE RESP. INSTRID: {1:d}, DATA_SIZE: {2:d}, TAGID: {3:d}data_size % it->index_len == 0len < data_size9UopEngine@ void UopEngine::push_biu_wr_uop(biuWriteUopType, uint32_t)void UopEngine::genarate_rd_uop(std::shared_ptr, LsuPortIndex, LsuPortIndex, bool, uint32_t)void bwifSharedBuf::push_uop(biuWriteUopType) 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   bool UopEngine::check_wait_flag(std::shared_ptr&)void UopEngine::set_uop_to_l1Intf()ca_lsu_uop_engine.ccca_lsu_uop_engine.cc:67, Wrong UE Type.ca_lsu_uop_engine.cc:115, Wrong UE Type.BasicUopEngineit->second.req_send == falseuop != nullptrtick: {0:d}, MTE1: {1:s} instr_id: {2:d}, release wait flag event id {3:d}, wait flag id: {4:d}tick: {0:d}, MTE1: {1:s} instr_id: {2:d}, backpressure by wait flag event id {3:d}, wait flag id: {4:d}l1_uop.uop->vld_time >= 417WinogradUopEngine@           /?void WinogradUopEngine::gen_wino_uop(std::shared_ptr, uint32_t)void WinogradUopEngine::winograd_l0a_kernal(std::shared_ptr, uint32_t)void WinogradUopEngine::winograd_l0a_frac_interation(std::shared_ptr) 0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_lsu_winograd_uop_engine.ccwino_iter.fp_q.size() == 18it.empty()?9LsuDCacheSt23_Sp_counted_ptr_inplaceI8CacheCfgSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI5TagIdSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI8CacheReqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@            -+   lsu_dcache.ccmte dcache run_req_type: req id:{0:d} tick: {1:d}.mte dcache clean_completed_req: req id:{0:d} tick: {1:d}.mte dcache push_req_to_mshr: req id:{0:d} merge:{1:d} tick: {2:d}.mte dcache gen req: req id:{0:d} hit:{1:d} addr: 0x{2:x} size: 0x{3:x} tick: {4:d}.mte dcache read request cache miss tick: {0:d}.mte dcache read request back pressure by mshr tick: {0:d}.mte dcache rsp_to_out_ack succ: req id:{0:d} rob vld:{1:s} rd_biu_ostd:{2:d} tick: {3:d}.mte dcache locking_tag_buf: req id:{0:d} rob vld:{1:s} idx:{2:d} victim_way:{3:d} tick: {4:d}.mte dcache push_mis_req_to_mis_seq: req id:{0:d} tick: {1:d}.mte dcache send_rsp_to_out: req id:{0:d} tick: {1:d}.mte dcache read biu stall: req id:{0:d} tick: {1:d}.7CaWaippSt23_Sp_counted_ptr_inplaceI15biuWriteUopTypeSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI14WAIPP_ISA_INFOSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   ca_waipp.ccrd req: mte_stimg: tick: {0:d}, rd_uops_: {1:d}, rd_ack_uops: {2:d}, cur_rd_num_: {3:d}, rd ack: mte_stimg: tick: {0:d}, rd_ack_uops_: {1:d}, trans_buf_: {2:d}, data_size: {3:d}, trans: mte_stimg: tick: {0:d}, trans_buf_: {1:d}, wr0_buf_: {2:d}, wr1_buf_: {3:d}, proc_bytes: {4:d}, in_bytes_: {5:d}, out_bytes: {6:d}, ca_waipp.cc, req_size = {0:d} != resp_size = {1:d}wr: mte_stimg: tick: {0:d}, wr0_buf_: {1:d}, wr1_buf_: {2:d}, wr_uops_: {3:d}, waipp_wdata_buf_: {4:d}, waipp_uop_buf_: {5:d}, pop_size: {6:d}, batch_id: {7:d}, line_id: {8:d}, wr_cnter_: {9:d}, wr: mte_stimg: tick: {0:d}, waipp_wdata_buf_: {1:d}, waipp_uop_buf_: {2:d}, data_size: {3:d}, write_address: 0x{4:x}, retire_set: {5:d}, retire instr: mte_stimg: tick: {0:d}, isa_queue_: {1:d}, gen rd uops: mte_stimg: tick: {0:d}, rd_uops: {1:d}, gen wr_trans: mte_stimg: tick: {0:d}, row: {1:d}, col: {2:d}, line_id: {3:d}, batch_id: {4:d}, pop_size: {5:d}, data_size: {6:d}, buf_size: {7:d}, start_addr: 0x{8:x}, end_addr: 0x{9:x}, align_128: 0x{10:x}, gen wr uops: mte_stimg: tick: {0:d}, wr_uops: {1:d}, pop instr: mte_stimg: tick: {0:d}, waipp_cmd_que_: {1:d}, isa_queue_: {2:d}, @  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   waipp_decoder.ccdecode: st_ldimg: dst_addr: 0x{0:x}, src_addr: 0x{1:x}, h_size: {2:d}, v_size: {3:d}, trans_mode: {4:s}, dst_stride: {5:d}, src_dtype: {6:s}, dst_dtype: {7:s}, in_chn_size: {8:d}, out_bits_size: {9:d}, in_pixel_size: {10:d}, in_valid_pixel_size: {11:d}, cur_h_size: {12:d}, cur_v_size: {13:d}, out_h_size: {14:d}, out_v_size: {15:d}, out_pix_num: {16:d}, instr_id: {17:d}, version_name: {18:s}, bypass: {19:s}, MINILITETINYVECU16U14U12TRANS_16TO3TRANS_4TO1BYPASS@  0@P`p 0@            @                              @                                       ????????? ?          p`P@0 `@ -+   waipp_pv_func.ccwaipp_src.txtwaipp_dTrans.txtwaipp_ctrans.txtexcuteUop_readDeltaexcuteRdbuff_VADD_DownexcuteRdbuff_VADD_TOPgenerateUopalign_buffer_offsetgen_write_maskexcuteUop_readFeature@  0@P`p 0@                           0<1>//4-. 9/90<1>//-./ 0  9< 1 > / / - . 0   /  99990<>1//-./ 004400<1>//-./ 449  : < 1 > / / - .  0   /  9  : < 1 > / / - . 0   /              0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- --@(( ((@%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./@@) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @- -(( @( (%% %@%@&& &@&@< < < =@=@>@ >@ > > 1 1 1 ) )@'' '@' ** * *@++ + +@,, , ,@    22 2 3 3@          @      0@//.@.   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0 * $  ! " # 894@)@-./@ @ ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @     99 ::;$   !!""##FGE@E JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO P@PP P Q@QQ Q RRR R SSS S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- - -(( ( (%% %@%&& &@&< < < =@=@> >@> > 1 1 1 ) )'' '' ** * *++ + +,, , ,    22 2 3  3@                   0@//.8.  8 <445 5 55 66@87@DD@3%&'(2<=>?1+756:;0 * $  ! " # 894)@- . /,  @C@@MMM MMMMMMM M M M M MM        9 9 ::;$   !!""##FGEEJJKKLL66AAA@? ??BBCCI@H N NN@N@O O OPPP P QQQ Q RRR R SSS S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                       @ @@@                                                                                                                                    -+   7tagFp16aic_ca_vec_col2img_uop_engine.cc[%s] %s:%d %s memset_s failed, error num: %d [%s] %s:%d %s img2col error, stride_w = 0, forced to 1. [%s] %s:%d %s img2col error, stride_h = 0, forced to 1. [%s] %s:%d %s img2col error, dialtion_w = 0, forced to 1. [%s] %s:%d %s img2col error, dialtion_h = 0, forced to 1. [%s] %s:%d %s fetch position: (%d, %d) in filter >= kernal size: (%d, %d). [%s] %s:%d %s img2col error, fm_w: %d or fm_h: %d is 0. [%s] %s:%d %s img2col error, dilated filter size: (%d, %d) > fm size: (%d, %d). [%s] %s:%d %s img2col error, 1st filter width position: %u > fm_w + pad_right - dilated_filter_width. [%s] %s:%d %s img2col error, 1st filter height position: %u > fm_h + pad_bottom - dilated_filter_height. [%s] %s:%d %s img2col error, 1st filter position(%d, %d) < -255. emuuuuuuuuuuuuuuu%euu-7--77uuuuuuuuuuuuAuuuuuuuKK7AAAuuUUuu]uuuuuuuu@  0@P`p 0@                           0<1>//4-. 9/90<1>//-./ 0  9< 1 > / / - . 0   /  99990<>1//-./ 004400<1>//-./ 449  : < 1 > / / - .  0   /  9  : < 1 > / / - . 0   /              0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- --@(( ((@%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./@@) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @- -(( @( (%% %@%@&& &@&@< < < =@=@>@ >@ > > 1 1 1 ) )@'' '@' ** * *@++ + +@,, , ,@    22 2 3 3@          @      0@//.@.   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0 * $  ! " # 894@)@-./@ @ ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @     99 ::;$   !!""##FGE@E JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO P@PP P Q@QQ Q RRR R SSS S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- - -(( ( (%% %@%&& &@&< < < =@=@> >@> > 1 1 1 ) )'' '' ** * *++ + +,, , ,    22 2 3  3@                   0@//.8.  8 <445 5 55 66@87@DD@3%&'(2<=>?1+756:;0 * $  ! " # 894)@- . /,  @C@@MMM MMMMMMM M M M M MM        9 9 ::;$   !!""##FGEEJJKKLL66AAA@? ??BBCCI@H N NN@N@O O OPPP P QQQ Q RRR R SSS S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                       @ @@@                                                                                                                                    -+   void aic_vec::CaVector::vms4_trigger_rd(aic_vec::p_vec_uop_t, uint32_t)void aic_vec::CaVector::vms4_sort_proc(aic_vec::p_vec_uop_t)N7aic_vec8CaVectorESt23_Sp_counted_ptr_inplaceIN7aic_vec7VEC_UOPESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec8CaVector16VecPreRetireInfoESaIS2_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec12Vms4ListInfoESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec11Vms4BufInfoESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aic_vec14Vms4OutBufInfoESaIS1_ELN9__gnu_cxx12_Lock_policyE2EEaic_ca_vector.cc//---ISA Info ----------------------------------------------------ISA ID is: ISA bin is: ISA name is: ISA dtype is: ISA conv type is: ISA reg type is: ISA cond op type is: ISA xd is: ISA xm is: ISA xn is: ISA xt is: ISA xd val is: ISA xm val is: ISA xn val is: ISA xt val is: ISA dst addr is: ISA src0 addr is: ISA src1 addr is: ISA stride mode is: ISA repeat mode is: ISA mask mode is: ISA dst stride is: ISA src0 stride is: ISA src1 stride is: ISA dst repeat stride is: ISA src0 repeat stride is: ISA src1 repeat stride is: ISA repeat is: ISA mask 0/1 are: //---UOP Info ----------------------------------------------------UOP issue tick is: UOP id is: UOP rd_vld is: UOP rd_rdy is: UOP latency_vld is: UOP rd_latency is: UOP exe_latency is: UOP wr_latency is: UOP stage is: UOP retire stage is: UOP back_pressue cycle is: UOP repeat_time is: UOP src1 value bypassed: UOP dst value bypassed: tick: {0:d}, proc_mix_mcb_fusion, deqscale_pre: 0x{1:x}, deqscale_next: 0x{2:x}, mcb_pre: 0x{3:x}, mcb_next: 0x{4:x}, burst_idx: 0x{5:x}tick: {0:d}, check_instr_fusion end,bInstrFusion: {1:d}, is_src_same: {2:d}, is_h_suprt: {3:d}, is_data_suprt: {4:d}, is_dst_addr_suprt: {5:d}tick: {0:d}, uop->id:{1:d}, Err fusion type.=============vms4_trigger_rd, send_rd_req, tick is:{0:d},list_idx is:{1:d},uop->repeat_time is:{2:d},start_addr is:0x{3:x}==================================vms4_trigger_rd, send_rd_req, tick is:{0:d},list is:{1:d},buf is:{2:d},cur_rd_size is:{3:d},start_addris:0x{4:x},uop->ub_rd0_req_id is:{5:d},cur_list->list_pre_rd_size is:{6:d},list_total_size is:{7:d}=====================cur_buf->buf_size_cnt == 0============= vms4_check_rd_req, rd_req_arbit_suc, tick is:{0:d},list is:{1:d},list_buf is:{2:d},rd_req_id is:{3:d} ================================== tick is:{0:d},vms4_check_rd_buf, rd_req_cpmplete, repeat is:{1:d},list is:{2:d},buf is:{3:d},buf_rd_req_size is:{4:d},buf_size_cnt is:{5:d},is_list_rd_end is:{6:d}=====================++++++++++++++++vms4_check_wr_req, wr_req_completed, tick is:{0:d},out_buf_idx is:{1:d},uop->ub_wr_req_id is:{2:d}++++++++++++++++------------ CaVector::vms4_check_wr_req,set is_list_wr_end, tick is:{0:d},list is:{1:d},wr_end_req_id is:{2:d} ---------------------------------- CaVector::vms4_rd_proc,rdy_to_rd,send_rd_req,step2 tick is:{0:d} ---------------------------------- CaVector::vms4_rd_proc,rdy_to_rd,step3 tick is:{0:d},vms4_rd_proc_list_id is:{1:d},vms4_rd_proc_buf_id is:{2:d} ---------------------------------- CaVector::vms4_rd_proc,send_rd_req,step4 tick is:{0:d},vms4_rd_proc_list_id is:{1:d},vms4_rd_proc_buf_id is:{2:d} ----------------------tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},burst_num: {6:d},burst_len: {7:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},burst_num: {6:d},burst_len: {7:d},conv_relu: {8:d},lrelu_ctrl: {9:d},on_fly_ctl: {10:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},burst_num: {6:d},burst_len: {7:d},h: {8:d},conv_relu: {9:d},brc_rpt_ctrl: {10:d},on_fly_ctl: {11:d},on_fly_op_mode: {12:d},lrelu_ctrl: {13:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},mode: {6:d},C: {7:d},image_size: {8:d},ele_size: {9:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d}, vbi_rep_mode: {6:d}, v_rep_num: {7:d}, h_rep_num: {8:d},MASK_mode: {9:d},MASK[0]: 0x{10:x},MASK[1]: 0x{11:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},VSEL_mode: {6:d},MASK_mode: {7:d},MASK[0]: 0x{8:x},MASK[1]: 0x{9:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},reduce_mode: {6:d},src1_rep_std: {7:d},MASK_mode: {8:d},MASK[0]: 0x{9:x},MASK[1]: 0x{10:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},s16_bit_extend: {6:d},MASK_mode: {7:d},MASK[0]: 0x{8:x},MASK[1]: 0x{9:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d},reg_type: {6:d},region_prop_ctrl: 0x{7:x}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d}, paral: {4:d}, uop_num: {5:d}, region_size: {6:d}tick: {0:d}, isa: {1:x} {2:s}, repeat: {3:d},vms4_type: {4:d},vms4_mask: {5:d},list0_size: {6:d},list1_size: {7:d},list2_size: {8:d},list3_size: {9:d},region_size: {10:d}UOP issue tick is:{0:d}UOP id is:{0:d}UOP ub_rd0 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_rd1 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP special rd,ub_rd1 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_wr_req masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_rd2 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_rd3 masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP ub_wr1_req masks{0:x}, {1:x}, {2:x}, {3:x},{4:x}, {5:x}, {6:x}, {7:x}UOP rd_latency is:{0:d}UOP exe_latency is:{0:d}UOP wr_latency is:{0:d}UOP stage is:{0:d}UOP retire stage is:{0:d}UOP back_pressue cycle is:{0:d}UOP read_conflict_cycle is:{0:d}UOP valu_conflict_cycle is:{0:d}UOP order_conflict_cycle is:{0:d}UOP throughput_conflict_cycle is:{0:d}UOP var_valu_conflict_cycle is:{0:d}UOP wr_conflict_cycle is:{0:d}UOP bypass_iss_delay is:{0:d}UOP repeat_time is:{0:d}UOP src1 value bypassed:{0:d}UOP dst value bypassed:{0:d}UOP dma_vdeq_burstn_uop0_delay:{0:d}UOP dma_vdeq_burst_uop0_rd_ub_cflt:{0:d}UOP dma_vdeq_burst_uop0_rd_ub_delay:{0:d}UOP vexp_vln_delay:{0:d}UOP viou_vaadd_iss_delay:{0:d}UOP special_instr_iss_delay:{0:d}tick: {0:d}, uop_mode1_perf_dble: {1:d}, this pair don't support.tick: {0:d}, uop_mode1_perf_dble: {1:d}, is_src0_suprt_mode1: {2:d}, is_src1_suprt_mode1: {3:d}, is_dst_suprt_mode1: {4:d}, two_src_dif_linetype: {5:d}.++++++++++++++++ vms4_trigger_wr, set wr_end_req_id, tick is:{0:d},list is:{1:d},wr_end_req_id is:{2:d}++++++++++++++++++++++++++++++++ vms4_trigger_wr, can't set wr_end_req_id! tick is:{0:d},list is:{1:d},wr_end_req_id is:{2:d},is_list_sort_end is:{3:d},sort_proc_rdy_to_wr is:{4:d},wr_proc_rdy_to_wr is:{5:d}++++++++++++++++++++++++++++++++ vms4_trigger_wr, send_wr_req, tick is:{0:d},out_buf_idx is:{1:d},wr_size is:{2:d},uop->ub_wr_req_id is:{3:d},start_addr is:0x{4:x}++++++++++++++++------------ CaVector::vms4_sort_proc,wr_proc_rdy_to_wr,send_wr_req,step2 tick is:{0:d} ---------------------------------- CaVector::vms4_sort_proc,sort_proc_rdy_to_wr,send_wr_req,step1 tick is:{0:d} ----------------------*******************vms4_sort_proc, sort_procing, tick is:{0:d},repeat is:{1:d},sort out list is:{2:d},sort out list_buf is:{3:d}, out buf is:{4:d},uop->isa_info->vms4_cur_sort_id is:{5:d}*******************cur_out_buf_info->second->out_buf_sta != 2------------ CaVector::vms4_sort_proc,rdy_to_wr,step3 tick is:{0:d} ---------------------------------- CaVector::vms4_wr_proc,rdy_to_wr,send_wr_req,step2 tick is:{0:d} ---------------------------------- CaVector::vms4_wr_proc,rdy_to_wr,step3 tick is:{0:d} ----------------------tick: {0:d}, UOP id is:{1:d}, l0c_wr_req_id is:{2:d},l0c_wr_proc_len is:{3:d}tick: {0:d}, UOP id is:{1:d}, ub_wr_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, uop->id:{1:d}, uop->l0c_wr_req_id:{2:d}, uop wr latency == 0, while L0C wr not completed.tick: {0:d}, uop->id:{1:d}, uop->ub_wr_req_id:{2:d}, uop wr latency == 0, while UB wr not completed.tick: {0:d}, retire set_deqtick: {0:d}, retire instr1tick: {0:d}, UOP id is:{1:d}, ub_rd0_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, UOP id is:{1:d}, ub_rd1_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, UOP id is:{1:d}, VDEQ ub_rd0_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, UOP id is:{1:d}, l0c_rd0_req_id is:{2:d},l0c_rd0_proc_len is:{3:d}tick: {0:d}, UOP id is:{1:d}, src0 rd is optimizedtick: {0:d}, UOP id is:{1:d}, ub_rd2_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, UOP id is:{1:d}, src2 rd is optimizedtick: {0:d}, UOP id is:{1:d}, ub_rd3_req_id is:{2:d},one_bit_size is:{3:d}tick: {0:d}, I1 step2, decodetick: {0:d}, vector_mov_special_xn, ibuf_.empty(): {1:d}, pipe_.empty(): {2:d}, irq_.empty(): {3:d}, pc: 0x{4:08x}tick: {0:d}, uop->id:{1:d}, VDEQ step1.tick: {0:d}, uop->id:{1:d}, VDEQ step2.tick: {0:d}, uop->id:{1:d}, VDEQ step3.tick: {0:d}, uop->id:{1:d}, VDEQ step4.tick: {0:d}, uop->id:{1:d}, VDEQ step5.tick: {0:d}, uop->id:{1:d}, VDEQ step6.tick: {0:d}, uop->id:{1:d}, VDEQ step7.tick: {0:d}, uop->id:{1:d}, is_uop_rd_invalid:{2:d}, is_uop_wr_invalid:{3:d}.bypass delay check step4,tick: {0:d}, UOP id is:{1:d}, UOP vbi_h_repeat_idx is:{2:d},pre_uop_issue_cyc is:{3:d},pre_uop_issue_rpt is:{4:d}bypass delay check step5,tick: {0:d}, UOP id is:{1:d}, UOP vbi_h_repeat_idx is:{2:d},pre_uop_issue_cyc is:{3:d},pre_uop_issue_rpt is:{4:d}bypass delay check step4,tick: {0:d}, UOP id is:{1:d}, UOP repeat_time is:{2:d},pre_uop_issue_cyc is:{3:d},pre_uop_issue_rpt is:{4:d}bypass delay check step5,tick: {0:d}, UOP id is:{1:d}, UOP repeat_time is:{2:d},pre_uop_issue_cyc is:{3:d},pre_uop_issue_rpt is:{4:d}gc_[WSPLI=951-)%! l7 7 zz7tt7.....vvvvvvvv&&&&vvvV6 fvvvv4vvvnvNNvB ^,,vv44@     0@P`p 0@            0<1>//4-. 9/90<1>//-./ 0  9< 1 > / / - . 0   /  99990<>1//-./ 004400<1>//-./ 449  : < 1 > / / - .  0   /  9  : < 1 > / / - . 0   /              0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- --@(( ((@%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./@@) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @- -(( @( (%% %@%@&& &@&@< < < =@=@>@ >@ > > 1 1 1 ) )@'' '@' ** * *@++ + +@,, , ,@    22 2 3 3@          @      0@//.@.   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0 * $  ! " # 894@)@-./@ @ ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @     99 ::;$   !!""##FGE@E JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO P@PP P Q@QQ Q RRR R SSS S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- - -(( ( (%% %@%&& &@&< < < =@=@> >@> > 1 1 1 ) )'' '' ** * *++ + +,, , ,    22 2 3  3@                   0@//.8.  8 <445 5 55 66@87@DD@3%&'(2<=>?1+756:;0 * $  ! " # 894)@- . /,  @C@@MMM MMMMMMM M M M M MM        9 9 ::;$   !!""##FGEEJJKKLL66AAA@? ??BBCCI@H N NN@N@O O OPPP P QQQ Q RRR R SSS S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                       @ @@@                                                                                                                                                -+     N7aic_vec10VecDecoderESt23_Sp_counted_ptr_inplaceIN7aic_vec12VEC_ISA_INFOESaIS1_ELN9__gnu_cxx12_Lock_policyE2EEvec_aic_decoder.ccillegal cfg about the list_en paramillegal cfg about the isa_info->size0 paramillegal cfg about the isa_info->size1 paramillegal cfg about the isa_info->size2 paramillegal cfg about the isa_info->size3 paramillegal cfg about the repeatTime paramillegal cfg about the list_en param when (exhaust_en==1 && repeat_time>1)illegal cfg about the list_size param when (exhaust_en==1 && repeat_time>1)use MINI tablethis dma instr not supportthis dma conv_relu not support, conv_relu: vec_instr_illegal_cfg: {0:s}, id: {1:d}[NOT SUPPORT] instr {0:s}, conv_type: DEQ, id: {1:d} not support in h200 vec_illegal_mask: {0:s}, id: {1:d}vec_instr_undef: {0:s}, id: {1:d}vec_instr_not_align: {0:s}, {1:s}: 0x{2:x}, align_bytes: {3:d}, id: {4:d}xmxdvec: ccu_addr_err: {0:s}, addr: 0x{1:08x} is overflow l0c buffer size, id: {2:d}vec: ccu_addr_err: {0:s}, addr: 0x{1:08x} is overflow ub buffer size, id: {2:d}vec_instr_illegal_cfg: {0:s}, don't support op_cal! on-the-fly operation should be 0, id: {2:d}vec_instr_illegal_cfg: {0:s}, conv_relu don't support op_cal! on-the-fly operation should be 0, id: {2:d}vec_instr_illegal_cfg: instr {0:s}, burst_len can't be 0, id: {1:d}src1_start_line: src1_end_line: dst_start_line: dst_end_line:vec_instr_illegal_cfg: {0:s}, on_fly_cal src UB and dst UB addr cflt, id: {1:d}vec_instr_addr_misalign: {0:s}, on_fly_cal dst addr 0x{1:08x}is not 32B aligned!, id: {2:d}[NOT SUPPORT] instr {0:s}, id: {1:d} not support in h200[NOT SUPPORT] instr {0:s} conv_relu: {1:02x}, id: {2:d} not support in h200[NOT SUPPORT] instr {0:s} on-the-fly calculation, id: {1:d} not support in h200[NOT SUPPORT] instr {0:s} L0CDPF16 to UB, id: {1:d} not support in h200[NOT SUPPORT] instr {0:s} leaky-relu, id: {1:d} not support in h200@@@@@MMMMP(tFM6FFFFF.#~s6+{&bWRG ZOxm h] peLA<1D9vkJ?`U4)-+   @     0@P`p 0@            0<1>//4-. 9/90<1>//-./ 0  9< 1 > / / - . 0   /  99990<>1//-./ 004400<1>//-./ 449  : < 1 > / / - .  0   /  9  : < 1 > / / - . 0   /              0< 1 > / / 4 - .  9/  90<1>//-. 0/##9 :#!0#<%1%>%/%/%-%.%% %/%%99990<>1//-. /004400<1>//-. /449 : < 1 > / / - .  0   /  9:<1>//-.0 /                                                  99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::09  9   : : 0< < < 1 1 1 / / > > -./    99::0<<<111//>>-./  99999999999999990RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS                                                    99  - . /  < < < 1 1 1 / / 4 > >   99.-/< < < 1 1 1 / / 4 > >   -./      9 9 0 -./990<<<111//>>-./  99::0-./<<<111//>>  99::0  9  9   : : 0 < < < 1 1 1 / / > > - . /        99::0<<<111//>>-./  9999  999999  999999  9999  0RRRRSSSS0RRRRSSSS0RRRRSSSS<<<111//>>990::RRRSSS990::RRRSSS990::RRRSSS990::RRRSSS990499040RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS0RRRRSSSS-./4-./4-./<<<111//>>  4-./4-./-./4-./499:< < < 1 1 1 / / > >  R R R R S S S S 0     9 9   : < < < 1 1 1 / / > >    R R R R S S S S 0     99:<<<111//>>0RRRRSSSS  99:<<<111//>>0RRRRSSSS  ..  )) -- --@(( ((@%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233   @@     @0 //. .   <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./@@) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- --(( ((%% %%@&& &&@<<<==>>>>111))@'''@' * ***@++ ++@,, ,,@ 22 233     @@    @0 //. .  <44@5 5 5@5 @66@87@DD3%&'(2<=>?1 +7 5 6 : ; 0*$ !"#8@9@4 -./) ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$  !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCIH N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S ) ) - - --( ( ((% % %%& & &&< <<= => >> >1 11))' ''' * * **+ + ++, , ,,   2 2 23 3         @    @0/ / . .   <44@5 5 5@5 @66@8 7  @ DD3 % & ' ( 2 < = > ? 1+ 756:;0*$ !"#8 9 4-./), @C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@                          9 9::;$  !!" " # # F G     E E JJ@KK@LL@6 6 A A A ? ? ? B B C C I@H N NN@N@O O OPP P PQQ Q QR R RR S S SS )) -- @- -(( @( (%% %@%@&& &@&@< < < =@=@>@ >@ > > 1 1 1 ) )@'' '@' ** * *@++ + +@,, , ,@    22 2 3 3@          @      0@//.@.   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0 * $  ! " # 894@)@-./@ @ ,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @     99 ::;$   !!""##FGE@E JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO P@PP P Q@QQ Q RRR R SSS S )) -- @-@-(@( (@(%% %@%@&& &@&@<@<@<@=@=@>@>@>@>@1@1@1@)@)@''@'@' **@* *@++ +@+@,, ,@,@@  @@22 2@3 3@@ @@@ @@@@     @0@//.@ .@   <44@5 5 5@5 @66@87@DD@3%&'(2<=>?1@+7@5@6@:@;@0@*@$@ @!@"@#@894@)@-./@@,@C@@MMM@M@MM@M@MM@M @M @M @M @M @M@M@     @   9 9 ::;$   !!""##FGEE@JJ@KK@LL@66@AAA@???BBCCI@H N NN@N@O OO@P@PP P@Q@QQ Q@RRR@R SSS@S )) -- - -(( ( (%% %@%&& &@&< < < =@=@> >@> > 1 1 1 ) )'' '' ** * *++ + +,, , ,    22 2 3  3@                   0@//.8.  8 <445 5 55 66@87@DD@3%&'(2<=>?1+756:;0 * $  ! " # 894)@- . /,  @C@@MMM MMMMMMM M M M M MM        9 9 ::;$   !!""##FGEEJJKKLL66AAA@? ??BBCCI@H N NN@N@O O OPPP P QQQ Q RRR R SSS S ) ))* **++ +,, ,%% %&& &-PP PQQ Q2''(OD3%&'(2<=>?756:;10*+//RRRSSS        @@@@@ @ @ @ @ @ @        @@@@@ @ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@@@ @ @ @ @ @@@@        @@@@@@@ @ @ @ @ @ @@                  @@@@@@@ @ @ @ @ @ @@                       @ @@@                                                                                                                                                mov_l0c_ub_opmov_l0c_ub_opmov_l0c_ub_opmov_l0c_ub_opexec_vms4exec_mov_l0c_ub8ARITH_OPI7tagFp16aE8ARITH_OPI7tagFp16hE8ARITH_OPIj7tagFp16E8ARITH_OPI7tagFp16jE8ARITH_OPIiiE8ARITH_OPIi7tagFp16E8ARITH_OPIjjE8ARITH_OPIshE8ARITH_OPI7tagFp16S0_E6DIV_OPI7tagFp16S0_E11MLA_OP_C210I7tagFp16jEN7aic_vec9VecPVFuncE8LRELU_OPI7tagFp16S0_E7RELU_OPI7tagFp16S0_E8LRELU_OPIjjE6MUL_OPI7tagFp16S0_E7RELU_OPIjjE6EXP_OPI7tagFp16S0_E6EXP_OPIjjE7SQRT_OPI7tagFp16S0_E7SQRT_OPIjjE8RSQRT_OPI7tagFp16S0_E8RSQRT_OPIjjE7RELU_OPIiiE6REC_OPI7tagFp16S0_E6REC_OPIjjE5LN_OPI7tagFp16S0_E5LN_OPIjjE6ABS_OPI7tagFp16S0_E6ABS_OPIjjE8ARITH_OPIssE6ABS_OPIssE6ADD_OPI7tagFp16S0_E6ADD_OPIjjE7CMAX_OPI7tagFp16S0_E6MAX_OPIjjE6MAX_OPIssE7CMIN_OPI7tagFp16S0_E6MIN_OPIjjE6MIN_OPIssE6NOT_OPIssE6MAX_OPI7tagFp16S0_E6MAX_OPIiiE6MIN_OPI7tagFp16S0_E6MIN_OPIiiE6ADD_OPIiiE6ADD_OPIssE6MUL_OPIiiE6MUL_OPIssE6MUL_OPIjjE6SUB_OPI7tagFp16S0_E6SUB_OPIiiE6SUB_OPIssE6SUB_OPIjjE10ADDRELU_OPI7tagFp16S0_E10ADDRELU_OPIssE10ADDRELU_OPIjjE10ADDRELU_OPIiiE10SUBRELU_OPI7tagFp16S0_E10SUBRELU_OPIssE10SUBRELU_OPIjjE10SUBRELU_OPIiiE8ARITH_OPIsaE14ADDRELUCONV_OPIsaE14ADDRELUCONV_OPI7tagFp16aE14ADDRELUCONV_OPIj7tagFp16E14ADDRELUCONV_OPIshE14SUBRELUCONV_OPIsaE14SUBRELUCONV_OPI7tagFp16aE14SUBRELUCONV_OPIj7tagFp16E14SUBRELUCONV_OPIshE6DIV_OPIjjE11MUL_CONV_OPI7tagFp16aE11MUL_CONV_OPI7tagFp16hE15ADD_DEQ_RELU_OPIi7tagFp16E12AXPY_OP_C210I7tagFp16S0_E12AXPY_OP_C210IjjE12AXPY_OP_C210I7tagFp16jE6CMP_OPI7tagFp16S0_E6CMP_OPIjjE6CMP_OPIssE6SHR_OPIiiE6SHR_OPIjjE6SHR_OPIssE8ARITH_OPIttE6SHR_OPIttE6SHL_OPIttE6SHL_OPIjjE5OR_OPIssE6AND_OPIssE11MLA_OP_C210I7tagFp16S0_E11MLA_OP_C210IjjE12MADD_OP_C210I7tagFp16S0_E12MADD_OP_C210IjjE17MADD_RELU_OP_C210I7tagFp16S0_E17MADD_RELU_OP_C210IjjE6MOV_OPIssE7RELU_OPIssEvec_aic_pv_func.ccvec_ub_wrap_around: instr {0:s}, id: {1:d}VecPVFunc: instr {0:s}, memcpy_s error, id: {1:d}N7aiv_vec8CaVectorESt23_Sp_counted_ptr_inplaceIN7aiv_vec11ConnectPortISt10shared_ptrINS0_10THREAD_ISAEEEESaIS5_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec20VecLanePortConnectorESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI12VectorICacheSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec16BasicVECRegisterESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec6VecCCUESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec7VecLaneESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec6VecSFUESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec6VecGsuESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec17AicAivBusyCounterESaIS1_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@           B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                        ( 0 8 @ H P X ` h p x  -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             aiv_ca_vector.cc&&E#Is1!qqqK; ;5{_;;;;'' ]7??? i  ggAi}+U -SSc;Ow'''Y1mE#+ 3 ; CCCCCCCCCCCCCCCC CCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCC CCKSKS [ C C CC C CCCCCCCCCCCCCcccks{ void aiv_vec::VecDecoder::get_vfcvt_rz_type(aiv_vec::vec_isa_t, uint32_t)void aiv_vec::VecDecoder::get_vfcvt_ro_type(aiv_vec::vec_isa_t, uint32_t)uint8_t aiv_vec::VecDecoder::get_alignment_reg_flag(aiv_vec::vec_isa_t, aiv_vec::vec_reg_index_t)@ void aiv_vec::VecDecoder::vld_decode(aiv_vec::vec_isa_t)vld_decodevoid aiv_vec::VecDecoder::vsld_decode(aiv_vec::vec_isa_t)vsld_decodevoid aiv_vec::VecDecoder::vgather_decode(aiv_vec::vec_isa_t)vgather_decodevgatherb_decodevldu_decodevlda_decodevzu_decodevbr_decodevci_decodevoid aiv_vec::VecDecoder::pge_decode(aiv_vec::vec_isa_t)pge_decodevoid aiv_vec::VecDecoder::pld_decode(aiv_vec::vec_isa_t)pld_decodevst_decodevscatter_decodevoid aiv_vec::VecDecoder::vsst_decode(aiv_vec::vec_isa_t)vsst_decodevstu_decodevsta_decodepst_decodevstur_decodevoid aiv_vec::VecDecoder::vstar_decode(aiv_vec::vec_isa_t)vstar_decodevec_arith_2src_3bit_type_decodedhist_decodevec_cross_arith_2src_3bit_type_decodevec_arith_2src_2bit_type_decodevaxpy_decodevrnds_lrelu_decodevec_dupi_decodevec_arith_3src_3bit_type_decodevec_arith_3src_2bit_type_decodevec_arith_cross_1src_3bit_type_decodevec_logic_2src_2bit_type_decodevec_logic_2src_1bit_type_sm_decodevec_logic_2src_1bit_type_vm_decodevec_rnd_2bit_type_decodevoid aiv_vec::VecDecoder::vec_avg_2bit_type_decode(aiv_vec::vec_isa_t)vec_avg_2bit_type_decodevoid aiv_vec::VecDecoder::vec_mov_intlv_decode(aiv_vec::vec_isa_t)vec_mov_intlv_decodevselr_decodevoid aiv_vec::VecDecoder::vec_mov_slide_decode(aiv_vec::vec_isa_t)vec_mov_slide_decodevec_scalar_arith_2src_3bit_type_decodevec_arith_2src_cmp_decodevec_scalar_arith_2src_cmp_decodevoid aiv_vec::VecDecoder::vec_2src_immd_decode(aiv_vec::vec_isa_t)vec_2src_immd_decodepre_logic_2src_no_type_decodepre_mov_intlv_decodevoid aiv_vec::VecDecoder::pre_mov_slide_decode(aiv_vec::vec_isa_t)pre_mov_slide_decodevec_mov_1src_decodevmov_decodeppack_decodevec_vdups_decodevec_vdup_decodepre_logic_1src_no_type_decodevoid aiv_vec::VecDecoder::plt_decode(aiv_vec::vec_isa_t)plt_decodevext_vextfa_decodevoid aiv_vec::VecDecoder::pset_decode(aiv_vec::vec_isa_t)pset_decodevoid aiv_vec::VecDecoder::vsqz_decode(aiv_vec::vec_isa_t)vsqz_decodevoid aiv_vec::VecDecoder::vusqz_decode(aiv_vec::vec_isa_t)vusqz_decodevec_ldst_sp_decodepre_ldst_sp_decodevec_vpack_decodevec_arith_1src_3bit_type_decodevoid aiv_vec::VecDecoder::get_vfcvt_rnd_type(aiv_vec::vec_isa_t, uint32_t)void aiv_vec::VecDecoder::vec_vtrc_decode(aiv_vec::vec_isa_t)vec_vtrc_decodevoid aiv_vec::VecDecoder::vec_vcvt_decode(aiv_vec::vec_isa_t)vec_vcvt_decodevoid aiv_vec::VecDecoder::vec_vfcvt_decode(aiv_vec::vec_isa_t)vec_vfcvt_decodevintegrals1_decodevintegrals2_decodevintegrals3_decodevoid aiv_vec::VecDecoder::wadd_decode(aiv_vec::vec_isa_t)wadd_decodevoid aiv_vec::VecDecoder::wadda_decode(aiv_vec::vec_isa_t)wadda_decodevoid aiv_vec::VecDecoder::wsub_decode(aiv_vec::vec_isa_t)wsub_decodevoid aiv_vec::VecDecoder::wmul_decode(aiv_vec::vec_isa_t)wmul_decode 0@P`p 0@           B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                        ( 0 8 @ H P X ` h p x  -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             void aiv_vec::VecDecoder::wmuls_decode(aiv_vec::vec_isa_t)wmuls_decodevoid aiv_vec::VecDecoder::wmula_decode(aiv_vec::vec_isa_t)wmula_decodevoid aiv_vec::VecDecoder::wmulas_decode(aiv_vec::vec_isa_t)wmulas_decodewaddsub_decodewcvt48_decodevoid aiv_vec::VecDecoder::wpack_decode(aiv_vec::vec_isa_t)wpack_decodevoid aiv_vec::VecDecoder::wpacks_decode(aiv_vec::vec_isa_t)wpacks_decodevoid aiv_vec::VecDecoder::wfifr_decode(aiv_vec::vec_isa_t)wfifr_decodedecodevoid aiv_vec::VecDecoder::vgather_uop(aiv_vec::vec_isa_t)void aiv_vec::VecDecoder::gen_scatter_uop(aiv_vec::vec_isa_t, uint32_t) [with T = unsigned int; F = unsigned int; aiv_vec::vec_isa_t = std::shared_ptr; uint32_t = unsigned int]void aiv_vec::VecDecoder::gen_scatter_uop(aiv_vec::vec_isa_t, uint32_t) [with T = short unsigned int; F = unsigned char; aiv_vec::vec_isa_t = std::shared_ptr; uint32_t = unsigned int]void aiv_vec::VecDecoder::gen_scatter_uop(aiv_vec::vec_isa_t, uint32_t) [with T = short unsigned int; F = short unsigned int; aiv_vec::vec_isa_t = std::shared_ptr; uint32_t = unsigned int]void aiv_vec::VecDecoder::vscatter_uop(aiv_vec::vec_isa_t)N7aiv_vec10VecDecoderEvec_aiv_decoder.ccfalse && "cannot find reg index"bitset::testfalse && "error rnd type".#normal.#brc_b8.#brc_b16.#brc_b32.#us_b8.#us_b16.#ds_b8.#ds_b16.#bdintlv.#dintlv_b8.#dintlv_b16.#unpk_b8.#unpk_b16.#brc_blk.#e2b_b16false && "error dist type"%s(dist: %u, vd: %u, sn: %u, am: %u, loop: %u).#s3_b16.#s4_b64.#s8_b32.#s2_b64false && "error stride type!"%s(stride: %u, vd: %u, sn: %u, am: %u, loop: %u).b8.b16.b32false && "error type!"%s(vd: %u, sn: %u, st: %u, am: %u, type: %u, loop: %u)%s(vd: %u, sn: %u, st: %u, am: %u, loop: %u)%s(st: %u, vd: %u, sn: %u, am: %u, ud: %u, loop: %u)%s(sn: %u, am: %u, ud: %u, loop: %u)%s(ud: %u, loop: %u)%s(vd: %u, sn: %u, type: %u, loop: %u).f16.f32false && "PGE ERROR TYPE"%s(pd: %u, pattern: %u, type: %u, loop: %u).#us.#dsfalse && "pld error dist!"%s(pd: %u, sn: %u, am: %u, dist: %u, loop: %u).#norm_b8.#norm_b16.#norm_b32.#1pt_b8.#1pt_b16.#1pt_b32.#pk_b16.#pk_b32.#intlv_b8.#intlv_b16%s(dist: %u, vd: %u, sn: %u, am: %u, pg: %u, loop: %u)%s(vn: %u, vd: %u, sn: %u, pg: %u, type: %u, loop: %u).#s8_b16false && "error stride!"%s(am: %u, vd: %u, sn: %u, stride: %u, loop: %u)%s(vd: %u, sn: %u, am: %u, ud: %u, post: %u, loop: %u).#pk%s(dist: %u, pd: %u, sn: %u, am: %u, loop: %u)%s(post: %u, vd: %u, sn: %u, ud: %u, loop: %u)%s(am: %u, sn: %u, ud: %u, type: %u, loop: %u)%s(vd: %u, vn: %u, vm: %u, pg: %u, type: %u)%s(vd: %u, vn: %u, pg: %u)%s(vd: %u, vn: %u, index: %u, pg: %u, type: %u)%s(vd: %u, vn: %u, sm: %u, pg: %u, type: %u)%s(vd: %u, vn: %u, imm8: %u, type: %u, part: %u)%s(vd: %u, vn: %u, pd: %u, pg: %u, type: %u)%s(vd: %u, vn: %u, vm: %u, pg: %u, type: %u, rnd: %u)vd % 2 == 0 && "vd index must be even"%s(vd: %u, vn: %u, vm: %u, type: %u)vn % 2 == 0 && "vslide: vn_index must be even!"%s(vd: %u, vn: %u, sm: %u, type: %u)%s(pd: %u, vn: %u, vm: %u, pg: %u, type: %u, cmp_type: %u)%s(pd: %u, vn: %u, sm: %u, pg: %u, type: %u, cmp_type: %u)%s(vd: %u, vn: %u, pg: %u, type: %u, imm: 0x%x)%s(pd: %u, pn: %u, pm: %u, pg: %u)%s(pd: %u, pn: %u, pm: %u, type: %u)pn % 2 == 0 && "pslide: pn_index must be even!"%s(pd: %u, pn: %u, sm: %u, type: %u)%s(vd: %u, vn: %u, pg: %u, type: %u)%s(vd: %u, vn: %u)%s(sn: %u, pg: %u)%s(pd: %u, pn: %u, part: %u)%s(vd: %u, sn: %u, pg: %u, type: %u, pm: %u)%s(vd: %u, vn: %u, pg: %u, type: %u, pm: %u)%s(pd: %u, pn: %u, pg: %u)%s(pd: %u, sn: %u, type: %u)%s(pn: %u)%s(pd: %u, pattern: %u, type: %u)%s(vd: %u, pg: %u, type: %u)%s(vd: %u, offset: %u)%s(pd: %u, offset: %u)%s(vd: %u, vn: %u, part: %u, type: %u)false && "vtrc error type!"%s(vd: %u, vn: %u, pg: %u, type: %u, rnd: %u).u82u16.u82u32.s82s16.s82s32.u162u8.u162u32.s162u8.s162u32.s162s32.u322u8.u322u16.u322s16.s322u8.s322u16.s322s16false && "vcvt error type!"false && "vscvt error type!"%s(vd: %u, vn: %u, type: %u, part: %u)%s(vd: %u, vn: %u, type: %u, pp: %u).f162s8.f162u8.f162s32false && "vfcvt error type!".f322f16.f322s32.f322s16.f162f32.f162s16.u82f16.s82f16.s162f16.s162f32.s322f32.f162s4false && "vsfcvt error type!"%s(vd: %u, vn: %u, pg: %u, type: %u, part: %u, ro: %u)%s(vd: %u, vn: %u, pg: %u, type: %u, part: %u, rz: %u)%s(vd: %u, vn: %u, pg: %u, type: %u, part: %u)%s(vd: %u, vn: %u, pg: %u, type: %u, pp: %u)%s(vd: %u, vn: %u, pg: %u, type: %u, part: %u, rnd: %u)%s(vn: %u)%s(vd: %u).u8.s8.u16.s16%s(wd: %u, vn: %u, vm: %u, pg: %u, type: %u).u8u8.u8s8.s8s8.u16u16.u16s16.s16s16.u8s16.s8s16.u16u32.u16s32.s16u32.s16s32%s(wd: %u, vn: %u, vm: %u, pg: %u, type: %u, part: %u)%s(wd: %u, vn: %u, sm: %u, pg: %u, type: %u, part: %u)%s(wd: %u, vn: %u, sm: %u, pg: %u, type: %u)%s(wd: %u, vn: %u, vm: %u, pg: %u, part: %u)%s(wd: %u, vn: %u, vm: %u, part: %u).s242s8.s242u8.s482s16.s482u16.s242s16.s642s32.s242u16.s482s32%s(vd: %u, wn: %u, vm: %u, pg: %u, rs: %u, type: %u, part: %u)%s(vd: %u, wn: %u, vm: %u, rs: %u, type: %u, part: %u)%s(vd: %u, wn: %u, vm: %u, pg: %u, rs: %u, type: %u)%s(vd: %u, wn: %u, vm: %u, rs: %u, type: %u)%s(vd: %u, wn: %u, sm: %u, pg: %u, rs: %u, type: %u, part: %u)%s(vd: %u, wn: %u, sm: %u, rs: %u, type: %u, part: %u)%s(vd: %u, wn: %u, sm: %u, pg: %u, rs: %u, type: %u)%s(vd: %u, wn: %u, sm: %u, rs: %u, type: %u)%s(wd: %u, vn: %u, sm: %u, type: %u)bitset::resetfalse && "vscatter error type" m [u SeA/I '9wWE_=O+i{3q#abPj H Z 6t$>| .lL:T 2D ^p(fxVK5@* convert_datatypeconvert_datatypeconvert_datatypeconvert_datatypeconvert_2_normal_typeconvert_2_normal_typeconvert_2_normal_typeconvert_2_normal_typeconvert_2_normal_typeconvert_2_normal_typeconvert_2_normal_typeconvert_2_normal_type@ void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = long unsigned int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]uint8_t* aiv_vec::VecPVFunc::get_v_dst_value(aiv_vec::vec_isa_t, uint32_t, aiv_vec::vector_reg_type_t, uint32_t)void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = signed char; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = Int96; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = Uint24; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = Int24; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = Int48; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = Uint48; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = long int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = short int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = short unsigned int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = tagFp16; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = unsigned int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = unsigned char; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecPVFunc::execute_pge_type(aiv_vec::vec_isa_t) [with T = unsigned int; aiv_vec::vec_isa_t = std::shared_ptr]void aiv_vec::VecPVFunc::execute_pge_type(aiv_vec::vec_isa_t) [with T = short unsigned int; aiv_vec::vec_isa_t = std::shared_ptr]void aiv_vec::VecPVFunc::execute_pge_type(aiv_vec::vec_isa_t) [with T = unsigned char; aiv_vec::vec_isa_t = std::shared_ptr]void aiv_vec::VecPVFunc::mul_bitset(std::bitset<256>&, std::bitset<256>&, uint32_t) 0@P`p 0@           B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                        ( 0 8 @ H P X ` h p x  -+   void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = tagFp16; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]uint32_t aiv_vec::VecPVFunc::get_reg_index(aiv_vec::vec_isa_t, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t)void aiv_vec::VecPVFunc::post_update(aiv_vec::vec_isa_t, uint32_t)void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = unsigned int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = unsigned char; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = Int48; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = short unsigned int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = signed char; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = short int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = long int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = Uint24; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]convert_2_normal_typevoid aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = Int24; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = Uint48; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]convert_2_normal_typevoid aiv_vec::VecPVFunc::rd_data_1src(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vector_reg_type_t, aiv_vec::vec_reg_index_t) [with T = Int96; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex]void aiv_vec::VecPVFunc::exec_vldu(aiv_vec::vec_isa_t)             !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             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aiv_vec12SHLS_OP_INFOIjjEEN7aiv_vec12SHLS_OP_INFOIiiEEN7aiv_vec12SHRS_OP_INFOIhhEEN7aiv_vec12SHRS_OP_INFOIttEEN7aiv_vec12SHRS_OP_INFOIssEEN7aiv_vec12SHRS_OP_INFOIjjEEN7aiv_vec12SHRS_OP_INFOIiiEEN7aiv_vec12RNDS_OP_INFOIssEEN7aiv_vec12RNDS_OP_INFOIiiEEN7aiv_vec11ABS_OP_INFOIaaEEN7aiv_vec11ABS_OP_INFOIssEEN7aiv_vec11ABS_OP_INFOIiiEEN7aiv_vec11ABS_OP_INFOI7tagFp16S1_EEN7aiv_vec11ABS_OP_INFOIjjEEN7aiv_vec11CLS_OP_INFOIhhEEN7aiv_vec11CLS_OP_INFOIaaEEN7aiv_vec11CLS_OP_INFOIttEEN7aiv_vec11CLS_OP_INFOIssEEN7aiv_vec11CLS_OP_INFOIjjEEN7aiv_vec11CLS_OP_INFOIiiEEN7aiv_vec11NEG_OP_INFOIaaEEN7aiv_vec11NEG_OP_INFOIssEEN7aiv_vec11NEG_OP_INFOIiiEEN7aiv_vec11NEG_OP_INFOI7tagFp16S1_EEN7aiv_vec11NEG_OP_INFOIjjEEN7aiv_vec11REC_OP_INFOI7tagFp16S1_EEN7aiv_vec11REC_OP_INFOIjjEEN7aiv_vec13RSQRT_OP_INFOI7tagFp16S1_EEN7aiv_vec13RSQRT_OP_INFOIjjEEN7aiv_vec12SQRT_OP_INFOI7tagFp16S1_EEN7aiv_vec12SQRT_OP_INFOIjjEEN7aiv_vec10LN_OP_INFOI7tagFp16S1_EEN7aiv_vec10LN_OP_INFOIjjEEN7aiv_vec12RELU_OP_INFOIiiEEN7aiv_vec12RELU_OP_INFOI7tagFp16S1_EEN7aiv_vec12RELU_OP_INFOIjjEEN7aiv_vec11EXP_OP_INFOI7tagFp16S1_EEN7aiv_vec11EXP_OP_INFOIjjEEN7aiv_vec8VBCNT_OPIaaEEN7aiv_vec8VBCNT_OPIssEEN7aiv_vec8VBCNT_OPIiiEEN7aiv_vec6NOT_OPIaaEEN7aiv_vec6NOT_OPIssEEN7aiv_vec6NOT_OPIiiEEN7aiv_vec11CMP_OP_INFOIhhEEN7aiv_vec11CMP_OP_INFOIaaEEN7aiv_vec11CMP_OP_INFOIttEEN7aiv_vec11CMP_OP_INFOIssEEN7aiv_vec11CMP_OP_INFOIiiEEN7aiv_vec11CMP_OP_INFOIjjEEN7aiv_vec12ADD3_OP_INFOIhhEEN7aiv_vec12ADD3_OP_INFOIaaEEN7aiv_vec12ADD3_OP_INFOIttEEN7aiv_vec12ADD3_OP_INFOIssEEN7aiv_vec12ADD3_OP_INFOIiiEEN7aiv_vec12ADIF_OP_INFOIhhEEN7aiv_vec12ADIF_OP_INFOIaaEEN7aiv_vec12ADIF_OP_INFOIttEEN7aiv_vec12ADIF_OP_INFOIssEEN7aiv_vec12ADIF_OP_INFOIjjEEN7aiv_vec12ADIF_OP_INFOIiiEEN7aiv_vec12VSAD_OP_INFOIhhEEN7aiv_vec12VSAD_OP_INFOIaaEEN7aiv_vec12VSAD_OP_INFOIttEEN7aiv_vec12VSAD_OP_INFOIssEEN7aiv_vec12VSAD_OP_INFOIjjEEN7aiv_vec12VSAD_OP_INFOIiiEEN7aiv_vec12MADD_OP_INFOI7tagFp16S1_EEN7aiv_vec12MADD_OP_INFOIjjEEN7aiv_vec12CMAX_OP_INFOIssEEN7aiv_vec12CMAX_OP_INFOIiiEEN7aiv_vec12CMIN_OP_INFOIssEEN7aiv_vec12CMIN_OP_INFOIiiEEN7aiv_vec11AND_OP_INFOIhhEEN7aiv_vec5OR_OPIhhEEN7aiv_vec6XOR_OPIhhEEN7aiv_vec7NAND_OPIhhEEN7aiv_vec11TRC_OP_INFOI7tagFp16S1_EEN7aiv_vec11TRC_OP_INFOIjjEEN7aiv_vec12WADD_OP_INFOIhjEEN7aiv_vec12WADD_OP_INFOIaiEEN7aiv_vec8ARITH_OPItmEEN7aiv_vec12WADD_OP_INFOItmEEN7aiv_vec8ARITH_OPIslEEN7aiv_vec12WADD_OP_INFOIslEEN7aiv_vec13WADDA_OP_INFOIhjEEN7aiv_vec13WADDA_OP_INFOIaiEEN7aiv_vec13WADDA_OP_INFOItmEEN7aiv_vec13WADDA_OP_INFOIslEEN7aiv_vec12WSUB_OP_INFOIhiEEN7aiv_vec12WSUB_OP_INFOIaiEEN7aiv_vec8ARITH_OPItlEEN7aiv_vec12WSUB_OP_INFOItlEEN7aiv_vec12WSUB_OP_INFOIslEEN7aiv_vec13WSUBA_OP_INFOIhiEEN7aiv_vec13WSUBA_OP_INFOIaiEEN7aiv_vec13WSUBA_OP_INFOItlEEN7aiv_vec13WSUBA_OP_INFOIslEEN7aiv_vec15WADDSUB_OP_INFOIhjEEN7aiv_vec15WADDSUB_OP_INFOIaiEEN7aiv_vec15WADDSUB_OP_INFOItmEEN7aiv_vec15WADDSUB_OP_INFOIslEE[%s] %s:%d %s memset_s for dst ptr failed [%s] %s:%d %s memset_s for dst ret failed [%s] %s:%d %s memcpy_s for dst ret failed exec_dhist. not support vl_spr: {0:d}VCADD: tree element num: {0:d}VCADD: src0: 0x{0:x}, src1: 0x{1:x}, result: 0x{2:x}cannot find reg index id: {0:d}, index: {1:d}false && "error pattern!"VSCATTER do not support same index, data: 0x{0:x}vec_aiv_pv_func.cc[%s] %s:%d %s memcpy_s for dst ptr failed isa_info->get_dst_value((vec_reg_index_t)vx, reg_type) != nullptr && "get dst reg index nullptr"error type instr: {0:s}, type_id: {1:d}error type instr: {0:s}, dist_id: {1:d}error stride instr: {0:s}, type_id: {1:d}error dist instr: {0:s}, dist_id: {1:d}exec_vldu. (Sn + Am):0x{0:x}, T:0x{1:x}, new_ofst:0x{2:x}, align_tmp: 0x{3:x}, st_value: 0x{4:x}, st_valid: 0x{5:x}exec_vldu. part_ud: 0x{0:x}, part_vtmp: 0x{1:x}, ud_offset: 0x{2:x}, vl_spr: 0x{3:x}, u_reg_len: 0x{4:x}, am_value: 0x{5:x}exec_vldu. UREG post_update keep origin_value.exec_vldu.VLDU Set UREG 0.post_update_ofst < tmp.size()exec_vldu. UREG normal post_update. post_offset: 0x{0:x}, post_update_ofst: 0x{1:x}VSTUR: dst_addr: 0x{0:08x}, dst_addr_tail: 0x{1:08x}, aligned_addr_0: 0x{2:08x}, aligned_addr_1: 0x{3:08x}, aligned_addr_2: 0x{4:08x}.N7aiv_vec6VecCCUESt23_Sp_counted_ptr_inplaceIN7aiv_vec11VLoopStatusESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13VecLoopBufferSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec13VecPrefetcherESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec18VecSRegFetchEngineESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI18VloopExceptionUnitSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEbool aiv_vec::VecCCU::check_address_register_hazard(aiv_vec::vec_isa_t, aiv_vec::vec_isa_t)@  0@P`p 0@                       B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                            ( 0 8 @ H P X ` h p x  -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             tick: {0:d}, {1:s} pc: {2:x}, name: {3:s}, count: {4:d}, limit: {5:d}load_instr_num_exceptiontick: {0:d}, load_loop_should_be_increased pc: {1:x}, name: {2:s}, loop: {3:d}, last_loop: {4:d}vag_instr_numtick: {0:d}, store_loop_should_be_decreased pc: {1:x}, name: {2:s}, loop: {3:d}, last_loop: {4:d}tick: {0:d}, vld_vst_use_same_align_reg pc: {1:x}, name: {2:s}, reg_index: {3:d}vec_ccu.ccdst_map->size() < 2tick: {0:d}, ccu_pipeline_is_hangup.tick: {0:d}, AIV_release_vec_lane_ownership.tick: {0:d}, AIC_GRANTED FIXPIPE_start_occupy_vec_lane.tick: {0:d}, fixpipe wr ub and aic vec task cannot execute at the same time!tick: {0:d}, AIC_GRANTED AIC_start_occupy_vec_lane.tick: {0:d}, AIC_GRANTED AIV_start_occupy_vec_lane.tick: {0:d}, AIV_GRANTED AIV_start_occupy_vec_lane.tick: {0:d}, AIV_GRANTED FIXPIPE_start_occupy_vec_lane.tick: {0:d}, AIV_GRANTED AIC_start_occupy_vec_lane.tick: {0:d}, AIC_FORBIDDEN AIV_start_occupy_vec_lane.tick: {0:d}, EXE stage should dual issue.tick: {0:d}, vec_ccu hazard cannot send isa pc: 0x{1:x}, single_launch: {2:d}.tick: {0:d}, vec_ccu address register hazard cannot send isa pc: 0x{1:x}.tick: {0:d}, vec_ccu hazard gather unit cannot access isa: 0x{1:x}.tick: {0:d}, vec_ccu hazard ldu cannot dual issue isa1: 0x{1:x},isa2: 0x{2:x}.N7aiv_vec6VecGsuEvoid aiv_vec::VecGsu::associate(aiv_vec::CaVector*)void aiv_vec::VecGsu::record_idx(aiv_vec::gsu_info_t&, uint32_t)@ aiv_vec::gsu_dtype_t aiv_vec::VecGsu::cur_dtype()aiv_vec::gsu_dtype_t aiv_vec::VecGsu::s_dtype()aiv_vec::gsu_dtype_t aiv_vec::VecGsu::g_dtype() 0@P`p 0@           B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                        ( 0 8 @ H P X ` h p x  -+   void aiv_vec::VecGsu::update_fsm()void aiv_vec::VecGsu::merge_addr(aiv_vec::gsu_info_t&, uint32_t)void aiv_vec::gsu_index_t::set_dtype(aiv_vec::vec_isa_t, bool, uint32_t)             !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_gsu.ccowner != nullptrinfo.idx.size() <= 64colase_.empty() == falseindex_fifo_[1].empty() == falseindex_fifo_[0].empty() == falsetick: {0:d}, GSU_FSM: G_ID1tick: {0:d}, GSU_FSM: G_ID2tick: {0:d}, GSU_FSM: S_ID1tick: {0:d}, GSU_FSM: S_ID2GSU: tick: {0:d}, idx_id: {1:d}, pos: {2:d}, index invalidGSU: tick: {0:d}, addr: 0x{1:08x}, bank: {2:d}, bank_group: {3:d}, bit0: {4:d}, idx_id: {5:d}, pos: {6:d}. bitmap idleGSU: tick: {0:d}, addr: 0x{1:08x}, bank: {2:d}, bank_group: {3:d}, bit0: {4:d}, idx_id: {5:d}, pos: {6:d}. coalescing successGSU: tick: {0:d}, addr: 0x{1:08x}, bank: {2:d}, bank_group: {3:d}, bit0: {4:d}, idx_id: {5:d}, pos: {6:d}. have cflt: {7:d}tick: {0:d}, gsu fifo pop: id: {1:d}tick: {0:d}, push_gsu_fifo, pc: 0x{1:x}, id: {2:d}, fifo_size: {3:d}tick: {0:d}, send_gsu_ecc_rd_req, id: {1:d}tick: {0:d}, send_gsu_rd_req, id: {1:d}tick: {0:d}, send_gsu_wr_req, id: {1:d}12VectorICache10TagElement6TagRam7DataRam11MISQElement4Misq19VecICacheTagArbiter20VecICacheDataArbiter13RequestHolderSt23_Sp_counted_ptr_inplaceI6TagRamSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI7DataRamSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI4MisqSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI13RequestHolderSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI9LockEntrySaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI19VecICacheTagArbiterSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI20VecICacheDataArbiterSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@                       B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                            ( 0 8 @ H P X ` h p x  -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_icache.cctick: {0:d}, unlock_addr: {1:x}.tick: {0:d}, csline_req at pc: {1:x} passed arbitration.tick: {0:d}, linefill_done at pc: {1:x}, unlock_not_in_misq_entry.tick: {0:d}, 1st_time_fill_csline at pc: {1:x}.tick: {0:d}, lock pcg: {1:d}, type: {2:d}, pc: {3:x}.tick: {0:d}, send_instr_req_to_arbit at addr: {1:x}, bank_mask {2:x}.tick: {0:d}, fetch_pc: {1:x}, vf_id: {2:d}, req_type: {3:d} misq missed, ret: {4:d}.tick: {0:d}, fetch_pc: {1:x}, vf_id: {2:d}, req_type: {3:d} misq valid.tick: {0:d}, fetch_pc: {1:x}, vf_id: {2:d}, req_type: {3:d} misq invalid.tick: {0:d}, misq_full lock pcg: {1:d}, type: {2:d}, pc: {3:x}.tick: {0:d}, put req to misq: vf_id {1:d}, type: {2:d}, pc: {3:x}.tick: {0:d}, put req to donelist: {1:d}, type: {2:d}, pc: {3:x}.tick: {0:d}, discard_high_pri at addr: {1:x}.tick: {0:d}, send_line_fill_to_data_arbit at addr: {1:x}, bank_mask {2:x}.tick: {0:d}, send_line_fill_to_tag_ram at addr: {1:x}.N7aiv_vec7VecLaneE@  0@P`p 0@           B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                        ( 0 8 @ H P X ` h p x  -+   void aiv_vec::VecLane::wr_result(aiv_vec::vec_isa_t, std::vector&, aiv_vec::vec_reg_index_t, aiv_vec::vector_reg_type_t) [with T = unsigned int; aiv_vec::vec_isa_t = std::shared_ptr; aiv_vec::vec_reg_index_t = aiv_vec::vecRegisterIndex; aiv_vec::vector_reg_type_t = aiv_vec::VECTOR_REG_TYPE]void aiv_vec::VecLane::gsu_idx_vld()             !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_lane.ccvector::_M_fill_inserttick: {0:d}, read_am_reg index {1:d} value {2:x} to isa pc {3:x} stage {4:d}.tick: {0:d}, update_am_reg pc: {1:x}, name: {2:s}, value: {3:d} tick: {0:d}, put_isa_to_lane_arbiter pc: {1:x}, name: {2:s}, id: {3:d}, info_num: {4:d}tick: {0:d}, check_ub_req pc: {1:x}, name: {2:s}, req: {3:d}, latency: {4:d}tick: {0:d}, pre_load_data_back pc: {1:x}, name: {2:s}, req: {3:d}, latency: {4:d}tick: {0:d}, send_vextfa_isa_to_stu_lane pc: {1:x}, name: {2:s}tick: {0:d}, send_gsu_isa_to_gsu_lane_port pc: {1:x}, name: {2:s}tick: {0:d}, has_valu_cflt pc: {1:x}, name: {2:s}, latency: {3:d}, throughput: {4:d}tick: {0:d}, has_throughput_cflt pc: {1:x}, name: {2:s}, latency: {3:d}, throughput: {4:d}, valu_grp: {5:d}tick: {0:d}, execute_pipe pc: {1:x}, name: {2:s}, latency: {3:d}tick: {0:d}, config_pipe_timing,invalid op! pc: {1:x}, name: {2:s}tick: {0:d}, config_pipe_timing,can't find op,set tmp VALU pc: {1:x}, name: {2:s}, latency: {3:d}, throughput: {4:d}, valu_grp: {5:d}tick: {0:d}, put_isa_to_lane_pipe pc: {1:x}, name: {2:s}, latency: {3:d}tick: {0:d}, send_ub_req pc: {1:x}, name: {2:s}, req: {3:d}d_info->gsu_id.size() == 1tick: {0:d}, gsu_idx_vld pc: {1:x}, name: {2:s}, id: {3:d}N7aiv_vec13VecPrefetcherESt23_Sp_counted_ptr_inplaceI16VecIcacheRequestSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec18VecPrefecherStatusESaIS1_ELN9__gnu_cxx12_Lock_policyE2EE@ void aiv_vec::VecPrefetcher::execute_no_vloop_instr(std::shared_ptr)      0@P`p 0@                  B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                            ( 0 8 @ H P X ` h p x  -+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_prefetcher.cctick: {0:d}, vec_prefetcher {1:d} expect vnop at pc {2:x}.owner_->vec_sfu_top_[thread_id_] != nullptrVECTOR_PUSHQtick: {0:d}, vec_prefetcher {1:d} fetch_pc: {2:x} is_in_hit_info: {3:d} cur_vf_pos_in_pf: {4:d}.tick: {0:d}, vec_prefetcher {1:d} preload_pc: {2:x} size: {3:d} cur_vf_pos_in_pf: {4:d}.tick: {0:d}, release_vec_lane_ownership.tick: {0:d}, vec_prefetcher {1:d} data_resp pc: {2:x}.tick: {0:d}, vec_prefetcher {1:d} expect 1st ld instr's pc: {2:x} to be 8 byte aligned.N7aiv_vec12VecSfuDecodeEuint32_t aiv_vec::VecSfuDecode::get_field(uint64_t, uint32_t, uint32_t)@ void aiv_vec::VecSfuDecode::v4dtrans_decode(aiv_vec::pushq_isa_t)v4dtrans_decodemovemask_decodemove_va_decodemov_ub_to_ub_decodefarti_decodevoid aiv_vec::VecSfuDecode::obj_rpncordiag2_decode(aiv_vec::pushq_isa_t)obj_rpncordiag2_decodeobj_vbs16_decodemov_spr_xn_decodeldvad_decodevtranspose_decodevscsplit_decodevoid aiv_vec::VecSfuDecode::obj_vms4_decode(aiv_vec::pushq_isa_t)obj_vms4_decodevoid aiv_vec::VecSfuDecode::vcshuffle_decode(aiv_vec::pushq_isa_t)vcshuffle_decodefilter_decode      0@P`p 0@                  B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                            ( 0 8 @ H P X ` h p x  -+   void aiv_vec::VecSfuDecode::vnchwconv_decode(aiv_vec::pushq_isa_t)vnchwconv_decodevirtual void aiv_vec::VecSfuDecode::decode(aiv_vec::pushq_isa_t)             !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_sfu_decode.cc%s(xd: %u, xn: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xtValue: 0x%lx, type: %u)%s(xn: %u, xnValue: 0x%lx, n: %u)%s(xn: %u, xm: %u, xnValue: 0x%lx, xmValue: 0x%lx, n: %u, vad: %u)%s(xd: %u, xn: %u, xdValue: 0x%lx, xnValue: 0x%lx, type: %u)%s(xn: %u, xnValue: 0x%lx, v_spr_id: %u)%s(xn: %u, xnValue: 0x%lx, VAd: %u, h: %u)%s(xd: %u, xn: %u, xdValue: 0x%lx, xnValue: 0x%lx)%s(xn: %u, xt: %u, xnValue: 0x%lx, xtValue: 0x%lx, type: %u, VAd: %u)illegal cfg about the para->size[0] paramillegal cfg about the para->size[1] paramillegal cfg about the para->size[2] paramillegal cfg about the para->size[3] param%s(xt: %u, xtValue: 0x%lx, VAd: %u, VAn: %u, type: %u, n: %u, repeat: %u)%s(xd: %u, xn: %u, xm: %u, xt: %u, xdValue: 0x%lx, xnValue: 0x%lx, xmValue: 0x%lx, xtValue: 0x%lx, type: u)%s(xt: %u, xtValue: 0x%lx, dstH: %u, srcH: %u, VAd: %u, VAn: %u, type: %u, repeat: %u, src_stride: %u, dst_stride: %u)tick: {0:d}, instr:({1:s}), pc:0x{2:x}, src_addr:0x{3:x}, dst_addr:0x{4:x} overlap!isa != nullptrN7aiv_vec12VecSfuEngineESt23_Sp_counted_ptr_inplaceIN7aiv_vec6sfuUopESaIS1_ELN9__gnu_cxx12_Lock_policyE2EE@             0@P`p 0@            B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                            ( 0 8 @ H P X ` h p x  virtual void aiv_vec::VecSfuEngine::proc(aiv_vec::pushq_isa_t)-+                !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_sfu_engine.ccvector::_M_range_insertN7aiv_vec10VecSfuFuncEN7aiv_vec6CMP_OPI7tagFp16S1_EEN7aiv_vec6CMP_OPIjjEE@       0@P`p 0@                  B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                            ( 0 8 @ H P X ` h p x  vms4_exec-+   int32_t aiv_vec::FIFR1ADD::operator()(std::vector&, OpInfo&, fpOpStatus&)             !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_sfu_func.cc!src.empty()FIFR1: r1c: 0x{0:x}, dat1: 0x{1:x}, mul_res1: 0x{2:x}FIFR1: add_res1: 0x{0:x}FIFR1: shr_res1: 0x{0:x}, shift1: 0x{1:x}FIFR1: sat_res1: 0x{0:x}FIFR1: rt: 0x{0:x}, dat2: 0x{1:x}, mul_res2: 0x{2:x}FIFR1: add_res2: 0x{0:x}FIFR1: shr_res2: 0x{0:x}, shift2: 0x{1:x}FIFR1: sat_res2: 0x{0:x}N7aiv_vec6VecSFUESt23_Sp_counted_ptr_inplaceIN7aiv_vec8sfuSctrlESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec10VecSfuFuncESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec12VecSfuDecodeESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec12VecSfuEngineESaIS1_ELN9__gnu_cxx12_Lock_policyE2EE@ void aiv_vec::sfuSctrl::instr_retire()      0@P`p 0@                  B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                            ( 0 8 @ H P X ` h p x  -+   virtual void aiv_vec::VecSFU::uop_done()virtual void aiv_vec::VecSFU::chk_resp(uint32_t)virtual void aiv_vec::VecSFU::gen_wr_req()             !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_sfu_top.ccpushq_isa_q_.empty() == falsetick: {0:d}, sfu get isa name: {1:s}, Id: {2:d}, pc: 0x{3:x}tick: {0:d}, access_sfu name: {1:s}, Id: {2:d}tick: {0:d}, gen_rd_uop name: {1:s}, Id: {2:d}tick: {0:d}, uop done name: {1:s}, Id: {2:d}, retire_set: {3:d}cur_rpt == uop->vms4_cur_repeattick: {0:d}, release vms4 next repeat uopi == 0tick: {0:d}, chk_rd_resp name: {1:s}, Id: {2:d}, req_id: {3:d}, latency: {4:d}tick: {0:d}, chk_wr_resp name: {1:s}, Id: {2:d}, req_id: {3:d}, latency: {4:d}tick: {0:d}, send_rd_req name: {1:s}, Id: {2:d}, req_id: {3:d}tick: {0:d}, send_wr_req name: {1:s}, Id: {2:d}, req_id: {3:d}!wr_uop->dst_addr.empty()tick: {0:d}, gen_wr_req name: {1:s}, Id: {2:d}N7aiv_vec18VecSRegFetchEngineEN7aiv_vec6VecAguEN7aiv_vec11IterCounterEN7aiv_vec17CosimInstrCounterEN7aiv_vec11VLoopStatusEN7aiv_vec11Vec_SupportESt23_Sp_counted_ptr_inplaceIN7aiv_vec6VecAguESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceIN7aiv_vec9VecRegMapESaIS1_ELN9__gnu_cxx12_Lock_policyE2EE@  0@P`p 0@           B=a- B=a- B=- ]B=- ] ]a- BXY12]a- BXY12a]- BXY12a] - BXY12!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='!(:<<=='""""""""""""" " [ [ """"" " [ [ "3"3"/"/"9"9[+[+""""""[["?"?":":"7"7[E[E""""""[#[#1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW1111111122222222XXXXXXXXYYYYYYYYWW========================!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='!(:<<='""""""""""""" " [ [ """"" " [ [ "3"3"/"/":":[*[*""""""[["?"?";";"9"9[F[F""""""[$[$fffgggssfffgggssfffgggssfffgggfffgggfffggg======================== !"#$ !"#$ !"#$=====WWWWWW !"#$ !"#$ !"#$=====WWWWWW===== !"#$ !"#$ !"#$WWWWWW===== !"#$ !"#$ !"#$WWWWWW                                        ( 0 8 @ H P X ` h p x  -+   U             !!""""";:"((00001 1 111111333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@ @ @ @ @ A A A A A B B . . . . . , , , - - - ''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W WWX X X X X X X X Y Y Y Y Y Y Y Y ZZ[GF[%$\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~               !!" " """;9"((00001 1 1 1 1 1 1 1 333444555666777888999::;;;;;;;;<<<<<<<<=======>>>>>>>>????????@@@@@AAAAABB.....,,,---''CCCCCCCCDDDEFGHIJJJKKKss)*+###//2 2 2 2 2 2 2 2 TTTTTUUUUUUVVVVVW W W W W W W W X X X X X X X X Y Y Y Y Y Y Y Y ZZ[GE[%#\\]]^^___```aabbbcccdddf f f gggh i j k llmmnnoooqqqrrrtwxyyyz{           !"#$ !"#$ !"#$ !"#$ !"#$ !"#$                    L M N O P Q R S | } ~             vec_support.ccpc is not in map! pc: 0x, cur_iter_: , proc_iter_idx: tick: {0:d}, set_am_const a{1:d} S[{2:d}]: 0x{3:x}, S[{4:d}]: 0x{5:x}, S[{6:d}]: 0x{7:x}, S[{8:d}]: 0x{9:x}.tick: {0:d}, update_am stage{1:d} a{2:d}=0x{3:x} I1: {4:d}, I2: {5:d}, I3: {6:d}, I4: {7:d}tick: {0:d}, pc: 0x{1:x}, name: {2:s}, used A[{3:d}] but not set by VAGtick: {0:d}, set_iter_size: I1 {1:d}, I2 {2:d}, I3 {3:d}, I4 {4:d}.tick: {0:d}, SQZN_SPR copy value: 0x{1:x}.tick: {0:d}, inc_stage: {1:d} counter. I1: {2:d}, I2: {3:d}, I3: {4:d}, I4: {5:d}.tick: {0:d}, VPD check. stage: {1:d}, pop_ptr: {2:d}, is_fake_iter: {3:d}, is_iter_first_instr: {4:d}, proc_ptr: {5:d}, cur_iter: {6:d}tick: {0:d}, update_vloopn_pd_reg, stage: {1:d}, updated_p_index: {2:d}, updated_reg_index: {3:d}, cur_iter: {4:d}tick: {0:d}, ccu_put_src_reg {1:d} index {2:d} value 0x{3:x} to isa pc 0x{4:x} stage {5:d}tick: {0:d}, pass_src_reg_val_to_isa pc: 0x{1:x}, name: {2:s}, reg_type: {3:d}, num: {4:d} tick: {0:d}, get_dst_reg_val_from_isa pc: 0x{1:x}, name: {2:s}, reg_type: {3:d}, num: {4:d}, write_en: {5:d} tick: {0:d}, error instr pc: 0x{1:x}, binary: {2:x}7BasicPb@      ( 0 8 @ H P X ` h p x  -+   basic_pb.ccparameter_buf slot_id: {0:d} is not available.14BasicSequencerSt23_Sp_counted_ptr_inplaceI7BasicPbSaIS0_ELN9__gnu_cxx12_Lock_policyE2EE@                       ( 0 8 @ H P X ` h p x  -+   tick {0:d}: SEQUENCER attach PBid: {1:d} to {2:s}, pc: 0x{3:x}. VF details: xd: {4:x}, imm5_01: {5:x}, imm5_11: {6:x}, VPC: {7:x}tick {0:d}: SEQUENCER detect VRFU PBid: {1:d}, pc: 0x{2:x}. VFRU details: xd: {3:x}, imm5_01: {4:x}, imm5_11: {5:x}, VPC: {6:x}basic_sequencer.ccVEC DUAL ISSQUE ARBITERtick {0:d}: SEQUENCER push pushQ isa: {1:s} to vector issque, pc: {2:x}.tick {0:d}: CCU read SEQUENCER SPR. isa: {1:s}, pc: {2:x}, address: {3:x}, size: {4:d}, req_id_: {5:d}.tick {0:d}: CCU write SEQUENCER PB. isa: {1:s}, pc: {2:x}, address: {3:x}, size: {4:d}, value: {5:x}, req_id_: {6:d}.tick {0:d}: SEQUENCER detect 0x pushQ ISA: {1:s} type: {2:x}. pc: {3:x}.tick {0:d}: SEQUENCER detect 1x pushQ ISA: {1:s} type: {2:x}. pc: {3:x}.N10AiCorePSim24AiCoreSimThreadContainerETickAiCoreThreadEntryStop@ Start-+   aicore_psim.cc[%s] %s:%d %s Error in running AiCoreIdx=%u, ChipId=%u [%s] %s:%d %s Array new (std::nothrow) or free array! [%s] %s:%d %s [%010u] Stop AiCorePSim 10aicpu_core@ -+   aicpu_core.cctoml::Value::Value(toml::Value&&)toml::Value& toml::Value::operator=(toml::Value&&)const toml::Value* toml::Value::findChild(const string&) consttoml::Value::Value(const toml::Value&)toml::Value& toml::Value::operator=(const toml::Value&)toml::Value* toml::Value::findChild(const string&)encountered non table valueinvalid keytype must be array to do push(Value).type must be table to do set(key, v).cfg.cpptype check failedunexpected tokeninline table didn't have ',' for delimiter?inline table has multiple same keys: key=Error: line could not open file: stream is in bad state. file does not exist?Invalid UTF8 BOMerror when parsing group keyparse key failedno equal?Multiple same key: error when parsing key Value/basic_string::erase[error] Failed to find config tab: [error] Config file is invalid. Path: Reason:  QtU >0)+5sHc #V&)Z(-o03s7}:d=`AD+jHK'OBSsV}Zv^Gb#f j#m^quGz3/~XTΊ{s*ؗIgƠ;P+:o rr`sJe|Q73EmqH(19BLBU^gpq {v|ܶ7C 6#*/:FR^jw֜#<2@]O+^!mB| +6BNZfr-;JYhw(9J\m*>Rf{G3HF@`>>A~@~i?[INFO] operator library version: 20190820-1FGGvoid hf_pe_sat_input(fp16_t*, fp16_t*, int, fpOpStatus*)fp16_t hf_pe_slice(fp16_t*, fp16_t*, fp16_t, int, fpOpStatus*, uint8_t)~~}|{zyyxwvvutsrrqpoonmmlkjihgedca`_]\[ZXWVUTRQPONMLKJHGFEDCBA@?>=<<;:98765433210/..-,+**)('&&%$##"!!          IntegerType RoundingDivideByPOT(IntegerType, int) [with IntegerType = int]int16_t bias_relu_deqs16(const int32_t&, const uint64_t&, const uint8_t&, const int16_t&, fpOpStatus*, const uint32_t&)fp16_unit.cclen == 16len == 16 && "the size of cube pe slice array must be 16! "exponent <= 31relu_mode <= 1 && "deqs16 does not support Leaky RELU and PRELU"6OTUUUTUUU~~}|{zyyxwvvutsrrqpoonmmlkjihgedca`_]\[ZXWVUTRQPONMLKJHGFEDCBA@?>=<<;:98765433210/..-,+**)('&&%$##"!!          & 5lF!V- 8tDP\h!u⎁Yњ}j-i!/l> M[jy!'zEμfb g6Q9+k<M`_a$q@֚'fL7-SA7Vyj% +a 6 DU t ̔   9 [ N~ " W G0 U 5z ǟ & 2:azs.Y׃3`S}+J]zW!v@XsǦTvD,zx[Vv=xu$Q~ 9i/a2g C|)dVT\*pG%q YI@fp32_t fp32_pe_slice(fp32_t*, fp32_t*, fp32_t, int, fpOpStatus&)dRet : %lffp32_t.cclen == (4) && "the size of cube fp32 pe slice array must be 4! "get_omg_pathopen_fp_fileload_fp_filerb/etc/HiAI_install.infoInstall_Path_Paramfp_file_op.cc[%s] %s:%d %s hiai_install_file is too long /runtime/bin/[%s] %s:%d %s strcat failed, errno is: %d [%s] %s:%d %s strcpy_s failed, errno is: %d fp32_ln.datfp32_exp.datfp16_ln.datfp16_exp.dat./model/pv_model/src/base/fp/data/fp32_ln.dat[%s] %s:%d %s strcpy_s failed, err = %d File: %s, file path is wrongCan't Open fp32_ln.dat! !./model/pv_model/src/base/fp/data/fp32_exp.datCan't Open fp32_exp.dat! !./model/pv_model/src/base/fp/data/fp16_ln.datCan't Open fp16_ln.dat! !./model/pv_model/src/base/fp/data/fp16_exp.datCan't Open fp16_exp.dat! !The fp file type is not supported! fp32_ln_cache: malloc failed fp32_exp_cache: malloc failed fp16_ln_cache: malloc failed fp16_exp_cache: malloc failed 17BasicBusInterfaceinit@ -+   directWriteAiCoredirectWriteAivCoredirectWriteAicpuCoredirectWriteAiContextSwitchdirectWriteAivContextSwitchdirectWriteAicpuContextSwitchbasic_bus_interface.cc[%s] %s:%d %s memset_s for dma_request_ failed [%s] %s:%d %s memset_s for ai_core_request_ failed [%s] %s:%d %s memset_s for aiv_core_request_ failed [%s] %s:%d %s memset_s for aicpu_core_request_ failed [{:010d}] [{:s} : {:d} : {:s}] Write registers of ai core 0x{:x}[{0:010d}] [hwts : {1:d} : {2:s}] Write registers of ai core {3:d}[{:010d}] [{:s} : {:d} : {:s}] Write registers of aiv core 0x{:x}[{0:010d}] [hwts : {1:d} : {2:s}] Write registers of aiv core {3:d}[{:010d}] [{:s} : {:d} : {:s}] Write registers of aicpu core {:d}, mailbox addr = {:x} [{:010d}] [{:s} : {:d} : {:s}] context switch triggered at core {:d}, swap buffer address = 0x{:x}, 0x{:x} N11util_qschdr5allsqE9BasicHwtsSt23_Sp_counted_ptr_inplaceIN11util_qschdr5allsqESaIS1_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceISt6vectorISt10shared_ptrISt4pairIjS1_I16tagHwtsDDRReqCmdEEESaIS6_EESaIS8_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15BasicQueueEntrySaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI16tagHwtsDDRReqCmdSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceISt4pairIjSt10shared_ptrI16tagHwtsDDRReqCmdEESaIS4_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI15block_schedulerSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI19hwts_sdma_schedulerSaIS0_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceISt6vectorIjSaIjEESaIS2_ELN9__gnu_cxx12_Lock_policyE2EEvirtual void BasicHwts::setRegisterDefaultValue()  @ `      @  @` @ @` @ @ ` @  @` @ @` @ @` @ @` @  @ `    ! !@!$ $@$`$$$$% %@%( (@(`(((() )@), ,@,`,,,,- -@- @` @ @` @ @ ` ! !@!$ $@$`$$$$% %@%( (@(`(((() )@), ,@,`,,,,- -@-virtual bool BasicHwts::configure(VirtualBusPortTbs*)virtual bool BasicHwts::configure(SlaveAccessPort*)virtual void BasicHwts::aiCoreDoneInterrupt(uint32_t)virtual void BasicHwts::aivCoreDoneInterrupt(uint32_t)virtual void BasicHwts::aicpuCoreDoneInterrupt(uint32_t)virtual bool BasicHwts::host_l1_normal_get_mask_interrupt(uint32_t, uint16_t, uint8_t&, uint32_t)virtual bool BasicHwts::host_l1_error_get_mask_interrupt(uint32_t, uint16_t, uint8_t&, uint32_t)virtual bool BasicHwts::host_l2_normal_get_maskX_by_sqid(uint32_t, uint32_t, uint16_t, bool) @virtual void BasicHwts::writeReg(uint64_t, uint64_t)virtual void BasicHwts::lock()virtual void BasicHwts::unlock()virtual uint32_t BasicHwts::lookup_active_sq_id(uint32_t)void BasicHwts::configure_mem_bus(SlaveAccessPort*)isConfigInOmgPath@ virtual BasicHwts::~BasicHwts()isConfigInEnvPath-+   write_entry_bit  @@   @@``@0 1@1 0@0`000014 5@5 4@4`444458 9@9 8@8`888890 1@1 0@0`000014 5@5 4@4`444458 9@9 8@8`88889@@@@@@@|@}@@@@ @ @ @@@@ @!@&@@@B@D@F@H@P@R@T@V@X@`@b@d@f@h@p@x@y@z@{@~@@writeSlotExtis_sq_friendly0 1@100 0@0`0104 5@544 4@4`4548 9@988 8@8`8980 1@100 0@0`0104 5@544 4@4`4548 9@988 8@8`898`p`pinterruptCallbackConfig_taskDoneinterruptCallbackConfig_taskError ``@@  assert_pre_pause_interruptassert_post_pause_interruptsqcq_state_killwait_proc_assert_sq_empty_interruptassert_cq_full_interruptassert_task_paused_interruptremove_aicore_from_idle_listvirtual void BasicHwts::remove_aicore_from_idle_list(uint32_t)assert_event_record_interruptassert_bus_error_interruptsq_update_head_cntsq_update_head_registercq_updatesqcq_state_ctrl_procsqcq_state_pause_proc_sq_event_table_pollingsq_notify_table_pollingsimplify_sqcq_state_proc_req_active_sq_idfree_active_sq_idticktask_blk_fsmvirtual void BasicHwts::send_sdma_done(uint32_t)send_sdma_doneaiv_context_switch_doneACSQ_swap_outDDR_RD_REQID_CHK_COMPLETEDDR_WR_REQID_CHK_COMPLETEDDR_WR_REQDDR_RD_REQsq_prefetchinterruptCallbackProcessACSQ_swap_inacsq_swapin_arbupdate_notify_table_bits_registerupdate_event_table_bits_registerextract_sqe_formatvirtual void BasicHwts::writeExt(uint32_t, uint64_t, uint64_t)writeExt   !!%%))--!!%%))-- "$(0248@BDH "$(0248@BDHfull_sqcq_state_proc_virtual uint64_t BasicHwts::readExt(uint32_t, uint64_t)readExtsqe_state_init_proc_BasicHwts::BasicHwts(uint32_t)BasicHwts"@$@%@basic_hwts.cchwts_regs_ != nullptrAIV_NORUNAIV_RESPAIC_NORUNAIC_RESP[IssueStlErrorInterrupt] error type mask : = 0x%x, type :%s non secure[IssueStlErrorInterrupt] NORUN timeout core bitmap : 0x%x, mode :%s, host = %u secure[IssueStlErrorInterrupt] RESP timeout core bitmap : 0x%x, mode :%s, host = %u bus_port_ != nullptrint_handler_ != nullptrhost_id <= 3(active_sq.size() <= (32)) && "Error: Invalid basicHwts_->active_sq.size."slave_port != nullptr./[%s] %s:%d %s hiai_install_file is too long! /runtime/bincannot open::OMG diropen:: OMG dir open {0:s} hwts_logLD_LIBRARY_PATH[%s] %s:%d %s env LD_LIBRARY_PATH has not set! [%s] %s:%d %s dup_path LD_LIBRARY_PATH failed! open::LD_LIBRARY_PATH [{:010d}] [{:s} : {:d} : {:s}] entry id cannot larger or equal to {:d} : {:d}[{:010d}] [{:s} : {:d} : {:s}] 0x{:08X} is non-addressable, slot : {:d}[{:010d}] [{:s} : {:d} : {:s}] sq slot id cannot larger or equal to {:d} : {:d}[{:010d}] [{:s} : {:d} : {:s}] task_type invalid {:d}[{:010d}] [{:s} : {:d} : {:s}] Configure L1 interrupt reg:0x{:08X} for SQ={:d}, INT_ID={:d}, flag=0x{:08X}, new_status=0x{:08X}[{:010d}] [{:s} : {:d} : {:s}] Configure L1 interrupt reg (host {:d}):0x{:08X} for SQ={:d}, INT_ID={:d}, flag=0x{:08X}, new_status=0x{:08X}[{:010d}] [{:s} : {:d} : {:s}] Configure L2 interrupt reg:0x{:08X} for SQ={:d}, new_status=0x{:08X}[{:010d}] [{:s} : {:d} : {:s}] Configure L2 interrupt reg (host {:d}):0x{:08X} for SQ={:d}, new_status=0x{:08X}[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} sendInterrupt for sq slot, INT ID:{:d}[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} task pre pause interrupt asserts[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} task post pause interrupt asserts[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} task resume[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} SQ empty interrupt asserts[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} CQ full interrupt asserts[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} task paused interrupt asserts[{:010d}] [{:s} : {:d} : {:s}] basic_hwts: AIC core_id: 0x{:x} is not in idle ai core queue.[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} event record Interrupt[{:010d}] [{:s} : {:d} : {:s}] bus_port_ is nullptr[{:010d}] [{:s} : {:d} : {:s}] bus error interrupt asserts[{:010d}] [{:s} : {:d} : {:s}] slot_idx = {:d}, cur_head_cnt = {:d}[{:010d}] [{:s} : {:d} : {:s}] The s_queue_[{:d}] is nullptr![{:010d}] [{:s} : {:d} : {:s}] sq_slot_id={:d}, sq_head={:d}[{:010d}] [{:s} : {:d} : {:s}] Update head register. sq_slot_id={:d}, task_type={:d}, step={:d}, sq_head={:d}, sq_head_pre={:d}, sq_tail={:d}[{:010d}] [{:s} : {:d} : {:s}] sq_head_update : SQ[{:d}] is disabled.[{:010d}] [{:s} : {:d} : {:s}] cq_head={:d}, cq_tail={:d}, cq_length={:d}, cqe_task_id={:d}[{:010d}] [{:s} : {:d} : {:s}] cq_base_addr=0x{:x}, cq_curr_addr=0x{:x}, cq_bound_addr=0x{:x}[{:010d}] [{:s} : {:d} : {:s}] compose cqe msg. cqe_task_id={:d}, sq_head_pre={:d}, cq_head={:d}, cq_tail={:d}, cq_length={:d}[{:010d}] [{:s} : {:d} : {:s}] write cq cfg. cqe_task_id={:d}, cq_tail={:d}[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} prefetch clear[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} enable task kill-wait state[{:010d}] [{:s} : {:d} : {:s}] TASK PAUSE -> IDLE sq slot ID:{:d} pre_p task resume[{:010d}] [{:s} : {:d} : {:s}] TASK PAUSE -> IDLE sq slot ID:{:d} cq full task resume[{:010d}] [{:s} : {:d} : {:s}] TASK PAUSE -> POST_P_END sq slot ID:{:d} post_p task resume[{:010d}] [{:s} : {:d} : {:s}] TASK PAUSE -> RUNNING sq slot ID:{:d} normal task resume[{:010d}] [{:s} : {:d} : {:s}] TASK PASUE -> SQCQ_TASK_PENDING_SWAP_IN_STATE SQ Id:{:d}, wait EVENT id {:d} type:{:d} task resume[{:010d}] [{:s} : {:d} : {:s}] TASK PASUE -> RUNNING SQ Id:{:d}, wait NOTIFY id {:d} type:{:d} task resume[{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d},SQCQ_TASK_PENDING_SWAP_IN_STATE -> SQCQ_TASK_RUNNING_STATE, type {:d}, map Active SQ Id:{:d}[{:010d}] [{:s} : {:d} : {:s}] doorbell_sq_id = {:d} goes to FULL sq fsm.[{:010d}] [{:s} : {:d} : {:s}] doorbell_sq_id = {:d} goes to SIMPLIFIED sq fsm.[{:010d}] [{:s} : {:d} : {:s}] error: complete cannot find SQ ID {:d} in active_sq list. Type:{:d} message, sq_en {:x}[{:010d}] [{:s} : {:d} : {:s}] free up SQ ID {:d} in active_sq list successfully. Type:{:d} message, sq_en {:x}[{:010d}] [{:s} : {:d} : {:s}] nullptr cur_active_qentry slot id = {:d}sdma_scheduler_ != nullptr[{:010d}] [{:s} : {:d} : {:s}] send sdma done to channel {:d}.[{:010d}] [{:s} : {:d} : {:s}] receive context switch req done from core id {:d}, SQ {:d}, BLK ID {:d}[{:010d}] [{:s} : {:d} : {:s}] receive unknown context switch req done from core id {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} delay free core id {:d}[{:010d}] [{:s} : {:d} : {:s}] swap out SQ ID {:d} in active_sq ID {:d}[{:010d}] [{:s} : {:d} : {:s}] sq id={:d} DDR request exists done. DDR Req id={:x}[{:010d}] [{:s} : {:d} : {:s}] sq id={:d} DDR write requesting. DDR Req id={:x}[{:010d}] [{:s} : {:d} : {:s}] sq id={:d} DDR read requesting. DDR Req id={:x}[{:010d}] [{:s} : {:d} : {:s}] doorbell ID {:d} is not found in ACSQ[{:010d}] [{:s} : {:d} : {:s}] s_queue_[{:d}]->prev_head_cnt = {:d}[{:010d}] [{:s} : {:d} : {:s}] s_queue_[{:d}]->cur_head_cnt = {:d}[{:010d}] [{:s} : {:d} : {:s}] N s_queue_[{:d}]->cur_head_cnt = {:d}[{:010d}] [{:s} : {:d} : {:s}] N s_queue_[{:d}]->prev_head_cnt = {:d}[{:010d}] [{:s} : {:d} : {:s}] N sq db = {:d} sq_head = {:d}[{:010d}] [{:s} : {:d} : {:s}] N sq db = {:d} sq_tail = {:d}[{:010d}] [{:s} : {:d} : {:s}] model:hwts:sq_base_addr = 0x{:x}, sq_head :{:d}, sq_tail : {:d}, sq_length : {:d}[{:010d}] [{:s} : {:d} : {:s}] sq_curr_addr = 0x{:x}, sq_bound_addr= 0x0x{:x}[{:010d}] [{:s} : {:d} : {:s}] prev_head_cnt={:d}, sq_head={:d}, slot_idx={:d}[{:010d}] [{:s} : {:d} : {:s}] cur_head_cnt=={:d}, sq_tail={:d}, slot_idx={:d}[{:010d}] [{:s} : {:d} : {:s}] doorbell_sq_idx:{:d} prefetch buffer full[{:010d}] [{:s} : {:d} : {:s}] PUSH SQE slot id({:d}) sqe vector size({:d}) <<<< cur_head_cnt({:d}) task_id({:d})[{:010d}] [{:s} : {:d} : {:s}] SQ id:{:d} Prefetch buffer size is not enough: {:d} , new used size: {:d}[{:010d}] [{:s} : {:d} : {:s}] Active SQ list size: {:d} , SQE num of entry: {:d}[{:010d}] [{:s} : {:d} : {:s}] Interrupt Flag (Error): L1:{:08X}({:08X}) SQ_ID:{:d} L2:{:08X}({:08X}) Host:{:d}[{:010d}] [{:s} : {:d} : {:s}] Interrupt Flag (Error): L1:{:08X}({:08X}) SQ_ID:{:d}[{:010d}] [{:s} : {:d} : {:s}] Interrupt Flag (Normal): L1:{:08X}({:08X}) SQ_ID:{:d} L2:{:08X}({:08X}) Host:{:d}[{:010d}] [{:s} : {:d} : {:s}] Interrupt Flag (Normal): L1:{:08X}({:08X}) SQ_ID:{:d}[{:010d}] [{:s} : {:d} : {:s}] Send a normal interrupt to host:{:d} secure:{:d}[{:010d}] [{:s} : {:d} : {:s}] HWTS_L1_NORMAL_NS_INTERRUPT: 0x{:016X}[{:010d}] [{:s} : {:d} : {:s}] HWTS_L1_NORMAL_NS_INTERRUPT_PENDING0: 0x{:016X}[{:010d}] [{:s} : {:d} : {:s}] HWTS_L1_NORMAL_NS_INTERRUPT_PENDING1: 0x{:016X}[{:010d}] [{:s} : {:d} : {:s}] HWTS_L1_NORMAL_NS_INTERRUPT_PENDING2: 0x{:016X}[{:010d}] [{:s} : {:d} : {:s}] Send a error interrupt to host:{:d} secure:{:d}[{:010d}] [{:s} : {:d} : {:s}] Send a debug interrupt to host:{:d} secure:{:d}[{:010d}] [{:s} : {:d} : {:s}] sq id={:d} request active SQ ID fail, no free ACSQ[{:010d}] [{:s} : {:d} : {:s}] Requesting Doorbell sq id={:d} maps to Active sq id=0x{:x}. DDR Req_id={:x}[{:010d}] [{:s} : {:d} : {:s}] Write SQ configuration Doorbell sq id={:d} maps to Active sq id=0x{:x}. DDR Req_id={:x}[{:010d}] [{:s} : {:d} : {:s}] Write CQ configuration Doorbell sq id={:d} maps to Active sq id=0x{:x}.[{:010d}] [{:s} : {:d} : {:s}] CLEAR sq id={:d}.[{:010d}] [{:s} : {:d} : {:s}] sq id={:d} swap in[{:010d}] [{:s} : {:d} : {:s}] Invalid SQ ID 0x{:x}.[{:010d}] [{:s} : {:d} : {:s}] Invalid Notify ID 0x{:x}.[{:010d}] [{:s} : {:d} : {:s}] SQ[{:d}] TYPE_SQE_FORMAT_NOTIFY_REC -> COMPLETE event id:{:d} completes normally[{:010d}] [{:s} : {:d} : {:s}] SQ[{:d}] TYPE_SQE_FORMAT_WAIT_NOTIFY -> COMPLETE event id:{:d} completes normally[{:010d}] [{:s} : {:d} : {:s}] SQ[{:d}] TYPE_SQE_FORMAT_WAIT_NOTIFY -> PAUSE event id:{:d} set notify flag[{:010d}] [{:s} : {:d} : {:s}] Invalid SQE tyoe 0x{:x}.[{:010d}] [{:s} : {:d} : {:s}] Invalid EVENT ID 0x{:x}.[{:010d}] [{:s} : {:d} : {:s}] SQ[{:d}] TYPE_SQE_FORMAT_EVENT_REC -> COMPLETE event id:{:d} completes normally[{:010d}] [{:s} : {:d} : {:s}] SQ[{:d}] TYPE_SQE_FORMAT_WAIT_EVENT -> COMPLETE event id:{:d} completes normally[{:010d}] [{:s} : {:d} : {:s}] SQ[{:d}] TYPE_SQE_FORMAT_WAIT_EVENT -> PAUSE event id:{:d} set pending flag[{:010d}] [{:s} : {:d} : {:s}] num_ext_pkt = {:d}, interrupt_en = {:d}, pre_p = {:d}, post_p = {:d}, type = {:d}, block_dimen = {:d}, sub_stream_id = {:d}, task_id = {:d}[{:010d}] [{:s} : {:d} : {:s}] address wrap around SQ bound : sqe_cur_addr=0x{:x}, bound_addr=0x{:x}[{:010d}] [{:s} : {:d} : {:s}] VQ6 kernel_credit cannot be zero[{:010d}] [{:s} : {:d} : {:s}] TOF kernel_credit cannot be zeroNSSETCLR[{:010d}] [{:s} : {:d} : {:s}] hwts sqe size is 64B mode. val=0x{:x}[{:010d}] [{:s} : {:d} : {:s}] hwts sqe size is 128B mode. val=0x{:x}[{:010d}] [{:s} : {:d} : {:s}] hwts SQ friendly scheduling TOF:{:d} VQ6:{:d} SDMA:{:d} AICPU:{:d} VEC:{:d} AIC:{:d}[{:010d}] [{:s} : {:d} : {:s}] Done! WRITE HWTS32_AICPU_BLK_CFG_NS, address:{:x}, value:{:x} aicpu:{:d}[{:010d}] [{:s} : {:d} : {:s}] Done! WRITE HWTS32_AICPU_BLK_CFG_S, address:{:x}, value:{:x} aicpu:{:d}[{:010d}] [{:s} : {:d} : {:s}] HWTS32_HWTS_CROSS_SOC_EVENT_TABLE is read only[{:010d}] [{:s} : {:d} : {:s}] Clear L1 register 0x{:08X}, l1_int_mask=0x{:08X}[{:010d}] [{:s} : {:d} : {:s}] L1 register 0x{:08X}, value=0x{:08X}[{:010d}] [{:s} : {:d} : {:s}] HWTS_L1_NORMAL_{:s}_MASK{:d}_{:s}: address=0x{:x}, value=0x{:x}[{:010d}] [{:s} : {:d} : {:s}] HWTS_L1_DEBUG_{:s}_MASK{:d}_{:s}: address=0x{:x}, value=0x{:x}[{:010d}] [{:s} : {:d} : {:s}] HWTS_L1_ERROR_{:s}_MASK{:d}_{:s}: address=0x{:x}, value=0x{:x}[{:010d}] [{:s} : {:d} : {:s}] HWTS_L1_STL_ERROR_{:s}_MASK{:d}_{:s}: address=0x{:x}, value=0x{:x}[{:010d}] [{:s} : {:d} : {:s}] General hwts write register address out of range, address=0x{:08X}, value=0x{:08X}[{:010d}] [{:s} : {:d} : {:s}] sqid {:d} is paused[{:010d}] [{:s} : {:d} : {:s}] MEMCPY STATE -> SQCQ_TASK_RUNNING_STATE:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] nullptr sdma_scheduler_ pointer!!:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, write value requests. address {:x}, size {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, write value address {:x}, size {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_VQ6 write mbx_source, address 0x{:x}, value 0x{:x} [{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_VQ6 read mbx_source, address 0x{:x} [{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_VQ6 read mbx_imask, address 0x{:x} [{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_VQ6 write imask, address 0x{:x}, value 0x{:x} [{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_VQ6 copy payload, address 0x{:x} [{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_VQ6 send, address 0x{:x}, value 0x{:x} [{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_TOF[{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_TOF copy calc, address 0x{:x}[{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d}, KS_TOF copy payload, address 0x{:x} [{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d} , blk granted SQCQ_TASK_READY_STATE -> SQCQ_TASK_RUNNING_STATE, type {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ slot id:{:d} , block dim shouldn't be ZERO, back to idle via complete state. type {:d}[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} task paused actively, type {:d}[{:010d}] [{:s} : {:d} : {:s}] SDMA MEMCPY : running->complete, SQ ID {:d} removed successfully. Type:{:d} message[{:010d}] [{:s} : {:d} : {:s}] nullptr sdma_scheduler_ pointer!!r:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] Write value : running->complete, SQ ID {:d} removed successfully. Type:{:d} message[{:010d}] [{:s} : {:d} : {:s}] AIC CMD : running->complete, SQ ID:{:d} task complete[{:010d}] [{:s} : {:d} : {:s}] SQCQ TASK COMPLETE! SQ slot id:{:d}, task_id:{:d} type:{:d} complete.[{:010d}] [{:s} : {:d} : {:s}] Call interruptCallbackConfig_taskDone, SQ={:d}, task_id={:d}, task_type:{:d}[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} enables post puase state, type {:d}[{:010d}] [task_end] : RTSQ={:d}, task_type={:d}, task_id={:d}, substream_id={:d}[{:010d}] [task_end] : RTSQ={:d}, task_type={:d}, task_id={:d}[{:010d}] [{:s} : {:d} : {:s}] Done! read HWTS32_AICPU_BLK_CFG_NS, address:{:x}, value:0x{:x} aicpu:{:d}[{:010d}] [{:s} : {:d} : {:s}] Done! read HWTS32_AICPU_BLK_CFG_S, address:{:x}, value:0x{:x} aicpu:{:d}[{:010d}] [{:s} : {:d} : {:s}] Read prefetch: Doorbell SQ {:d} opcode = {:d}[{:010d}] [{:s} : {:d} : {:s}] slot id cannot larger than 1024 : {:d}[{:010d}] [{:s} : {:d} : {:s}] active id cannot larger than {:d} : {:d}[{:010d}] [{:s} : {:d} : {:s}] sq slot id cannot larger than 1024 : {:d}[{:010d}] [{:s} : {:d} : {:s}] cq slot id cannot larger than 1024 : {:d}[{:010d}] [{:s} : {:d} : {:s}] sq cq slot id cannot larger than 1024 : {:d}[{:010d}] [{:s} : {:d} : {:s}] HWTS32_HWTS_SQ_SEC_EN Secure mode enabled. slot id : {:d} , address : 0x{:x}, value: 0x{:x}[{:010d}] [{:s} : {:d} : {:s}] non per SQ,CQ slot (0~1023) or per entry (0~1023) id : {:d}, address 0x{:x}[{:010d}] [task_start] : RTSQ={:d}, task_type={:d}, task_id={:d}, blkdim={:d}, substream_id={:d}[{:010d}] [task_start] : RTSQ={:d}, task_type={:d}, task_id={:d}[{:010d}] [{:s} : {:d} : {:s}] GET sq slot ID:{:d} Active SQ remained: {:d}. Active SQ grant flag:{:d} task_id:{:d}[{:010d}] [{:s} : {:d} : {:s}] cq_head: {:d}, cq_len: {:d}, cq_tail: {:d}[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} CQ full insterrupt asserts.[{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} enable task pre-pause state[{:010d}] [{:s} : {:d} : {:s}] sq ID:{:d} L1 lock[{:010d}] [{:s} : {:d} : {:s}] sq ID:{:d} L1 unlock[{:010d}] [{:s} : {:d} : {:s}] sq ID:{:d} L1 is in lock[{:010d}] [{:s} : {:d} : {:s}] Cannot get core: num({:d}) slot ID:{:d} type {:d} message [{:010d}] [{:s} : {:d} : {:s}] Cannot get IP: slot ID:{:d} type {:d} message [{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} READY STATE get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] sq slot ID:{:d} (L1 is locked) READY STATE get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] PLACE HOLDER sq slot ID:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] EVENT REC sq slot ID:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] WAIT EVENT sq slot ID:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] NOTIFY REC sq slot ID:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] WAIT NOTIFY sq slot ID:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] SDMA MEMCPY STATE -> SQCQ_TASK_READY_STATE:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] WRITE VALUE -> SQCQ_TASK_READY_STATE:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] KS_VQ6 sq slot ID:{:d} get type {:d} message [{:010d}] [{:s} : {:d} : {:s}] KS_TOF sq slot ID:{:d} get type {:d} message Project.name21BasicInterruptHandlerregTriggerInterruptregHostTriggerInterruptboExceptionType2StrinterruptCallbackToHost@ aicpuCoreDoneInterruptaiCoreDoneInterruptaivCoreDoneInterrupt-+   basic_interrupt_handler.cc[%s] %s:%d %s reg Trigger Interrupt is null [%s] %s:%d %s reg host Trigger Interrupt is null [%s] %s:%d %s host id is %u, which bigger than %u [%s] %s:%d %s SP_LEVEL_NUM_BO_EXCEPTION [%s] %s:%d %s TWO_TASK_OVERRIDE_BITMAP_CONFLICT_BO_EXCEPTIONI [%s] %s:%d %s MORE_THAN_2_TASK_EXEC_SIMULTANEOUSLY_BO_EXCEPTIOIN [%s] %s:%d %s PING_PONG_MODE_BO_EXCEPTION FATAL[%s] %s:%d %s unknow bo exceotion Type [%s] %s:%d %s Interrupt Callback to Host, interrupt_num: {:d}, counter: {:d} [%s] %s:%d %s Interrupt Callback to Host completed, interrupt_num: {:d}, counter: {:d} [%s] %s:%d %s Error in host_id:{:d}, interrupt_num: {:d} [%s] %s:%d %s basic_interrupt_handler.cc: returned done AICPU Core Num is invalid. [%s] %s:%d %s basic_interrupt_handler.cc: returned done Ai Core Num is invalid. [%s] %s:%d %s basic_interrupt_handler.cc: returned done AIV Core Num is invalid. 15BasicQueueEntryvirtual uint32_t BasicQueueEntry::allocAiCore()virtual uint32_t BasicQueueEntry::getAssignAiCoreNum()@ virtual void BasicQueueEntry::assignAiCore(uint32_t)virtual uint32_t BasicQueueEntry::allocOverrideAiCore()-+   setInterruptNumgetAndResetInterruptNumbasic_qentry.ccalloc_table_ != nullptrai_core_task_map_ != nullptr[{0:010d}] [hwts : {1:d} : {2:s}] setInterruptNum {3:d} [{0:010d}] [hwts : {1:d} : {2:s}] getInterruptNum {3:d} resetInterruptNum {4:d}12SQCQTaskSlotvirtual void SQCQTaskSlot::readExt(uint64_t, uint64_t&)virtual uint64_t SQCQTaskSlot::readExt(uint64_t)virtual void SQCQTaskSlot::writeExt(uint64_t, uint64_t)virtual void SQCQTaskSlot::serveTaskPause()virtual uint32_t SQCQTaskSlot::getAssignAiCoreNum()@ virtual void SQCQTaskSlot::assignAivCore(uint32_t, bool)virtual void SQCQTaskSlot::assignAicpuCore(uint32_t, bool)virtual void SQCQTaskSlot::assignAiCore(uint32_t, bool)void HwtsAiCoreAllocTable::freeCoreid(uint32_t)bool HwtsAiCoreAllocTable::doneAiCore(uint32_t)virtual uint32_t SQCQTaskSlot::allocOverrideAiCore()virtual uint32_t SQCQTaskSlot::allocAiCore(uint32_t)virtual void SQCQTaskSlot::taskBlockContextSwitchWaitingReqDone(uint16_t, uint32_t)virtual void SQCQTaskSlot::completeAiCoreDone(uint32_t, uint32_t)-+   virtual void SQCQTaskSlot::sendTask2AiCore(uint32_t, uint32_t, uint32_t)sendTask2AiCoresetInterruptNumgetAndResetInterruptNumtaskBlkFsmPerSlottaskBlockContextSwitchReqget_next_blkidget_context_switch_buffind_context_switch_bufvirtual void SQCQTaskSlot::sendTask2AivCore(uint32_t, uint32_t, uint32_t)sendTask2AivCorevirtual void SQCQTaskSlot::sendTask2AicpuCore(uint32_t, uint32_t, uint32_t)sendTask2AicpuCorefree_context_switch_bufserveAiCoreDonebasic_task_slot.h: core_id: 0x is not in busy ai core queuecore_id: 0x is not in ready_ai_core_ queuebasic_qtask_slot.ccbasicHwts_ != nullptrinterrupt_handler_ != nullptralloc_aic_table_ != nullptralloc_aiv_table_ != nullptralloc_aicpu_table_ != nullptrbus_interface_ != nullptr[{:010d}] [{:s} : {:d} : {:s}] HWTS scheduler alloc AI Core 0x{:x} to sq slot {:d}, blk id {:d}[{:010d}] [{:s} : {:d} : {:s}] setInterruptNum {:d} [{:010d}] [{:s} : {:d} : {:s}] getInterruptNum {:d} resetInterruptNum {:d}[{:010d}] [{:s} : {:d} : {:s}] cur_active_qentry is null pointer. cur_block_id({:d})[{:010d}] [{:s} : {:d} : {:s}] slot:{:d} is already occupied.[{:010d}] [{:s} : {:d} : {:s}] alloc_table_ is nullptr [{:010d}] [{:s} : {:d} : {:s}] context switch core id not found, SQ {:d}, BLK ID {:d} [{:010d}] [block_start] : RTSQ={:d}, task_type={:d}, task_id={:d}, blkID={:d}, coreID={:d}, sub_stream_id={:d}[{:010d}] [{:s} : {:d} : {:s}] AICPU core ID {:d} will be re-used by blk ID {:d} [{:010d}] [{:s} : {:d} : {:s}] block is completed. cur_block_id({:d}) curRunningBlockNum({:d}) remain blk({:d})[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} BLKID {:d} get context switch buffer {:x}[{:010d}] [block_switch_out] : RTSQ={:d}, task_type={:d}, task_id={:d}, blkID={:d}, coreID={:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} BLKID {:d} find context switch buffer {:x}aiv_core_task_map_ != nullptrcontext_switch_buf_addr != 0xFFFFFFFFFFFFFFFFULL[{:010d}] [{:s} : {:d} : {:s}] context switch resume sq slot {:d}, blk id {:d} on core 0x{:x}, context buffer = {:x}[{:010d}] [{:s} : {:d} : {:s}] HWTS scheduler alloc AIV Core 0x{:x} to sq slot {:d}, blk id {:d}aicpu_core_task_map_ != nullptr[{:010d}] [{:s} : {:d} : {:s}] HWTS re-use AICPU Core {:d} to sq slot {:d}, blk id {:d}[{:010d}] [{:s} : {:d} : {:s}] context switch resume sq slot {:d}, blk id {:d} on core {:d}, context buffer = {:x}[{:010d}] [{:s} : {:d} : {:s}] HWTS scheduler alloc AICPU Core {:d} to sq slot {:d}, blk id {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} BLKID {:d} free context switch buffer index {:d}[{:010d}] [block_end] : RTSQ={:d}, task_type={:d}, task_id={:d}, blkID={:d}, coreID={:d}, sub_stream_id={:d}, remain_blk_num={:d}[{:010d}] [{:s} : {:d} : {:s}] core ID {:d} is L1 locked by SQ {:d} for blk ID {:d}[{:010d}] [{:s} : {:d} : {:s}] core ID {:d} is L1 unlocked by SQ {:d} for blk ID {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} block is completed. cur_block_id({:d}) curRunningBlockNum({:d}) remain blk({:d})15block_schedulertoken_gen_process@ -+   context_switch_detectionget_stl_cfgset_blk_vldprepare_core_ackget_num_free_corel2_cache_friendly_checksq_is_doneadd_num_blk_grantdecr_free_coreremove_core_from_idle_listset_core_ackincr_free_corestl_donestl_kickstartcheck_stl_periodconfig_coreai_core_pool_processst2_processruntickblock_scheduler.cc[%s] %s:%d %s an error occured, i is %d and total credit exp is%d hwts_aic_bs_loghwts_aicpu_bs_loghwts_aiv_bs_log[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] higher priority SQ {4:d} context switch lowest priority SQ {5:d} blk ID {6:d}[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} resume STL[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} request block[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} core {5:d} prepare ack[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} is un-blocked[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} is blocked[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} blocked by L2 friendly scheduling[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} is done, free blocked list[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} blk id {5:d} will reuse aicpu core[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} blk dim {5:d} all blk done[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} ALLOC, SQ {5:d}[{:010d}] [{:s} : {:d} : {:s}] block_scheduler_{:d} core {:d} is not found in idle list[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} ack[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} FREE[{:010d}] [{:s} : {:d} : {:s}] block_scheduler_{:d} core {:d} FREE[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} COMPLETE STL[{:010d}] [{:s} : {:d} : {:s}] block_scheduler_{:d} core {:d} RUN STL[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} RUN STL[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] CORE {4:d} STL RSP TIMEOUT[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] CORE {4:d} STL NORUN TIMEOUT[{:010d}] [{:s} : {:d} : {:s}] block_scheduler_{:d} non-secure pool {:d} core {:d} enable[{:010d}] [{:s} : {:d} : {:s}] block_scheduler_{:d} non-secure pool {:d} core {:d} disable[{:010d}] [{:s} : {:d} : {:s}] block_scheduler_{:d} secure pool {:d} core {:d} enable[{:010d}] [{:s} : {:d} : {:s}] block_scheduler_{:d} secure pool {:d} core {:d} disable[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} blk_vld = 1[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} batch mode start[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} blkdim {5:d} batch mode hold, free core num {6:d}[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] core {4:d} is assigned to SQ id {5:d}[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} set L2 pending[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] high priority group pri_lvl = {4:d}, blk_vld_idx = {5:d}[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] low priority group pri_lvl = {4:d}, blk_vld_idx = {5:d}[{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] low priority group RR blk_vld_idx = {4:d}[%s] %s:%d %s token_gen_process failed [{0:010d}] [block_scheduler_{1:d} : {2:d} : {3:s}] SQ {4:d} ACK[%s] %s:%d %s weight cnt of index %d is zero [%s] %s:%d %s block_scheduler run faield [{:010d}] [{:s} : {:d} : {:s}] block_scheduler_{:d} core {:d} is assigned to SQ {:d}assignConfigPathgetConfigPathupdateConfigPathconfig_file.cc[%s] %s:%d %s Using config file [%s] [%s] %s:%d %s Config file [%s] not found. [%s] %s:%d %s Invalid config file. davinci_mini.speclib_pvmodel.solibcamodel.so[%s] %s:%d %s Config file is found, path is %s [%s] %s:%d %s Config file not found: %s [%s] %s:%d %s Using user config file [%s] [%s] %s:%d %s Unable to assign user config file [%s] ca_model/etcmodelmodel/model_BS9SX1AAmodel_BS9SX1AA../../../../etc../model/ca_model/etc../model/pv_model/etc19hwts_sdma_scheduler@ -+   set_blk_vldsdma_donevoid hwts_sdma_scheduler::sdma_free(uint32_t)sdma_freeconfig_sdma_chsdma_fsmhwts_sdma_scheduler.cc[{:010d}] [{:s} : {:d} : {:s}] New SDMA request SQ id {:d}[{:010d}] [{:s} : {:d} : {:s}] SDMA channel {:d} donesq_slot_id < (1024)[{:010d}] [{:s} : {:d} : {:s}] SDMA free channel, sq {:d}[{:010d}] [{:s} : {:d} : {:s}] SDMA pool {:d} non-secure channel {:d} enable[{:010d}] [{:s} : {:d} : {:s}] SDMA {:d} non-secure channel {:d} disable[{:010d}] [{:s} : {:d} : {:s}] SDMA pool {:d} secure channel {:d} enable[{:010d}] [{:s} : {:d} : {:s}] SDMA {:d} secure channel {:d} disable[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} gets SDMA channel {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA secure channel {:d} writes SQE to address {:x}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA secure channel {:d} updates SQ tail {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA non-secure channel {:d} writes SQE to address {:x}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA non-secure channel {:d} updates SQ tail {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA secure channel {:d} updates CQ head {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA secure channel {:d} updates CQ head Done {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA non-secure channel {:d} updates CQ head {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA non secure channel {:d} updates CQ head Done {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA free secure channel {:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} SDMA free non-secure channel {:d}N11util_qschdr16util_qschdr_baseE@ -+   hwts_util.cc19hwts_virtualizationSt23_Sp_counted_ptr_inplaceISt6vectorItSaItEESaIS2_ELN9__gnu_cxx12_Lock_policyE2EE@ -+   refill_tokenvoid hwts_virtualization::add_vm_run_count(uint32_t)add_vm_run_countpool_arbitermain_fsmvm_arbitervmg_sqdb_list_insertupdate_pool_statusVM_PRI_HIGHVM_PRI_NORMCOMMON[{:010d}] [{:s} : {:d} : {:s}] VMG {:s} enable priority {:s}, active SQid {:d}[{:010d}] [{:s} : {:d} : {:s}] VMG {:s} disable priority {:s}, active SQid {:d}[{:010d}] [{:s} : {:d} : {:s}] VMG {:s} ACSQ register status:0x{:032x}hwts_virtualization.cc[{:010d}] [{:s} : {:d} : {:s}] VM {:d} current token = {:d}sqid < (1024)vm_id[sqid] < (32)[{:010d}] [{:s} : {:d} : {:s}] Strict mode unlock VMG {:d} @ VM {:d} runtime={:d} token={:d}[{:010d}] [{:s} : {:d} : {:s}] SQ {:d} in VM {:d} runtime counter = {:d}[{:010d}] [{:s} : {:d} : {:s}] NORMAL POOL VMG@VM{:d}={:d} gives Active SQ idx = {:d}.[{:010d}] [{:s} : {:d} : {:s}] COMMON POOL VMG@VM{:d}={:d} gives Active SQ idx = {:d}.[{:010d}] [{:s} : {:d} : {:s}] HIGH NORMAL POOL VMG@VM{:d}={:d} gives Active SQ idx = {:d}.[{:010d}] [{:s} : {:d} : {:s}] HIGH COMMON POOL VMG@VM{:d}={:d} gives Active SQ idx = {:d}.[{:010d}] [{:s} : {:d} : {:s}] SQ DB Id {:d} @ VM={:d}, VMG={:d} grants Active SQ Id={:d}[{:010d}] [{:s} : {:d} : {:s}] invalid VMG SQDB pointer vm_id (0~3) = {:d}.[{:010d}] [{:s} : {:d} : {:s}] invalid SQ doorbell idx {:d}.[{:010d}] [{:s} : {:d} : {:s}] INIT or RELAX MODE got VM {:d} for SQ doorbell idx {:d}.[{:010d}] [{:s} : {:d} : {:s}] STRICT MODE got VM {:d} for SQ doorbell idx {:d}.N11util_qschdr4acsqE12ip_scheduler13vq6_scheduler13tof_schedulerSt23_Sp_counted_ptr_inplaceIN11util_qschdr4acsqESaIS1_ELN9__gnu_cxx12_Lock_policyE2EE@ -+   ip_scheduler::ip_scheduler(BasicHwts*, uint16_t, const char*)ip_schedulerip_doneips_fsmip_scheduler.cchwts != nullptr[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} init ======[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} receive done sq_id: {:d} with exception[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} receive done sq_id: {:d}[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} IP_STATE changes from IN_USE to IDLE.[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} IP_STATE changes from PROTECTED to IDLE.[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} Blkvld is zero.[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} IP granted to SQ:{:d} ACSQ:{:d}[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} prepare to process sq_id: {:d}, task_id: {:d}[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} unable to locate sq_id: {:d}[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} process sq_id: {:d}, task_id: {:d}[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} prepare to write CQE for sq_id: {:d}, task_id: {:d}[{:010d}] [{:s} : {:d} : {:s}] IP_Schdr_{:s} done CQE for sq_id: {:d}12l2_schedulerst1_processst2_processrun@ -+   l2_sche_fsmtickset_sqcq_l2_lock_reqclear_sqcq_l2_lock_reqget_sqcq_own_l2l2_scheduler.cc[%s] %s:%d %s there is a error here, weight cnt is zero hwts_l2_sche_log[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} new (std::nothrow) request L2 buffer[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} will take L2 buffer, SWAP in[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} request L2 buffer, existing owner SQ{4:d}[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} SWAP out done[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} SWAP out[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} SWAP in done[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} SWAP in[%s] %s:%d %s l2 scheduler run failed [{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} L2 buffer lock request[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} L2 buffer unlock[{0:010d}] [L2_scheduler : {1:d} : {2:s}] SQ{3:d} own l2 = {4:d}9l2_sq_fsmSt23_Sp_counted_ptr_inplaceISt6vectorISt10shared_ptrI17l2_sq_proc_statusESaIS3_EESaIS5_ELN9__gnu_cxx12_Lock_policyE2EESt23_Sp_counted_ptr_inplaceI17l2_sq_proc_statusSaIS0_ELN9__gnu_cxx12_Lock_policyE2EEprint@ -+   lock_requnlock_reqrunl2_sq_fsm.cc[%s] %s:%d %s ========== L2 buffer lock fsm ========== [%s] %s:%d %s pv_l2_active_sq_ addr.: 0x%08lx [%s] %s:%d %s pv_l2_active_sq_ size: %lu [%s] %s:%d %s ------------------------------------------- [%s] %s:%d %s l2buf SQ req[%d] [%s] %s:%d %s SQ ID : %d [%s] %s:%d %s State : [%s] %s:%d %s L2_SQ_FSM_STATE_IDLE [%s] %s:%d %s L2_SQ_FSM_STATE_LOCK_REQ [%s] %s:%d %s L2_SQ_FSM_STATE_LOCK_GRANT [%s] %s:%d %s L2_SQ_FSM_STATE_UNLOCK_REQ [%s] %s:%d %s L2_SQ_FSM_STATE_UNLOCK_GRANT [%s] %s:%d %s L2_SQ_FSM_STATE_SWAPOUT_REQ [%s] %s:%d %s L2_SQ_FSM_STATE_SWAPOUT_DONE_AND_BREAK [%s] %s:%d %s L2_SQ_FSM_STATE_SWAPIN_REQ [%s] %s:%d %s L2_SQ_FSM_STATE_SWAPIN_DONE [%s] %s:%d %s L2_SQ_FSM_STATE_RUNNING [{0:010d}] [l2_sq_fsm : {1:d} : {2:s}] SQ id {3:d} pv_l2_active_sq_ queue is nullptr.[{0:010d}] [l2_sq_fsm : {1:d} : {2:s}] SQ id {3:d} l2 lock done![{0:010d}] [l2_sq_fsm : {1:d} : {2:s}] SQ id {3:d} can't request l2 unlock since lock_gnt={4:d} & own={5:d} are not both set. OR state is not LOCK_GRANT:{6:d}[{0:010d}] [l2_sq_fsm : {1:d} : {2:s}] SQ id {3:d} l2 unlock done![{0:010d}] [l2_sq_fsm : {1:d} : {2:s}] remove SQ id {3:d} from L2 lock[{:010d}] [{:s} : {:d} : {:s}] SQ id {:d} previous STATE({:d}) ==> STATE({:d})convert_datatypeconvert_datatypecalculateconvert_datatypeshift_opcalculateconvert_2_normal_typeconvert_2_normal_typeint_num_t.cc[ERROR] Unable to read environment variable [].[INFO] Config file from absolute path: [ERROR] Config file cannot be found from absolute path: [INFO] Config file [] from environment variable [LD_LIBRARY_PATH]. Path: TOOLCHAIN_HOME] from environment variable [TOOLCHAIN_HOME]. Path: ] from current working directory. Path: ./etc/] from [./etc] directory. Path: [ERROR] Config file [] cannot be found.-cfg-noschema-class-schemaOverrideCfg-schemaOverrideScope-cpp-h-namespace-singleton.cpp.hr'cannot open 'w Invalid namespace '%s'unknown argument '%s' usage: %s -cfg -class options are: -noschema Do not generate a schema -schemaOverrideCfg -schemaOverrideScope -cpp default is .cpp -h default is .h -namespace X::Y::Z default is the global scope -singleton generate a singleton class -----------------------------------//%s%s Do not edit.// WARNING: This file was generated by %s. %s // access to an embedded// Description: a class providing %s // configuration string. #ifndef %s_h #define %s_h #include namespace %s { class %s { public: //-------- these would be private // Constructor and destructor. Ideally %s initialize the singleton. // but they have to be public so we can %s // Constructor and destructor. %s(); ~%s(); the singleton object // Get the configuration string from %s static const char * getString() { return s_singleton.m_str.c_str(); } // Get the configuration's schema int & schemaSizeconst char **& schema static void getSchema(%s, %s) s_singleton schema = %s.m_schema; schemaSize = %d; null terminated arraygetSchema static const char ** %s() // %s return s_singleton.m_schema; // Get the configuration string const char * getString() return m_str.c_str(); void getSchema(%s, %s) schema = m_schema; const char ** getSchema() // %s return m_schema; private: // Variables CONFIG4CPP_NAMESPACE::StringBuffer m_str; m_schema const char * %s[%d]; static %s s_singleton; // The following are not implemented %s & operator=(const %s &); %s(const %s &); }; }; // namespace %s #endif #include "%s%s" //-------- // Define the singleton object %s %s::s_singleton; %s::%s() m_schema[%d] = "%s"; m_schema[%d] = 0; m_str << ""; m_str << ""; } %s::~%s() // Nothing to do \\\t\n\"%s%s%s%t%n%%%" = ""; = [", ]; { } ConfigItem.cc0void config4cpp::ConfigItem::dump(config4cpp::StringBuffer&, const char*, bool, int) constN10config4cpp10ConfigItemE@copyFrom@else@elseIf@error@if@ifExists@in@include@matches@remove configFile(configType(exec(fileToDir(getenv(isFileReadable(join(osDirSeparator(osPathSeparator(osType(readFile(replace(siblingScope(split(N10config4cpp9ConfigLexEConfigParser.ccm_type == Configuration::CFG_STRINGm_type == Configuration::CFG_LISTm_listVal != 0m_type == Configuration::CFG_SCOPEm_scope != 0exec#0expecting identifier, line : cannot use '.' at start of the declaration of a variable or scope,expecting identifier or 'include'expecting ';' or '+'expecting '=', '?=' or '{'expecting 'include'The '@include' command cannot be used inside a scopecannot include "" due to security restrictionsfile#expecting ';' or '@ifExists' (included from )expecting 'if'expecting '('expecting ')'expecting '{'expecting '}'rexpecting '(', or a string expressionexpecting '@copyFrom'copy statement: cannot copy from own scope.copy statement: cannot copy from a parent scopeexpecting ';'copy statement: scope '' does not existcopy statement: '' is not a scopefromScope != 0item != 0expecting 'remove'expecting an identifier: can remove entries from only the current scope: '' does not exist in the current scopeexpecting 'error'expecting an identifier or '}'identifier '' not previously declaredexpecting a string, identifier or '['unix/:stringlistscopeno_value' is a scope instead of a string' is a list instead of a stringexpecting a string or identifierexpecting 'getenv('expecting ','cannot access the '' environment variableexpecting 'siblingScope('The siblingScope() function cannot be used in the root scopeexpecting 'read.file('error reading expecting 'join('expecting 'replace('expecting 'split('expecting 'os.exec('cannot execute "os.exec("") failed: execStatus == trueexpecting ']'' is not a listexpecting an identifier or '['i > 0expecting a string or ']''' is not a built-in function'.' is not a valid identifier'..' appears in identified 'end-of-line not allowed in string 'end-of-file encountered in block string starting at line is not a legal identifier near "" near 'config4cpp::ConfigParser::ConfigParser(config4cpp::Configuration::SourceType, const char*, const char*, const char*, config4cpp::ConfigurationImpl*, bool)void config4cpp::ConfigParser::parseCopyStmt()config4cpp::ConfigScope* config4cpp::ConfigItem::scopeVal() constconst char* config4cpp::ConfigItem::stringVal() constconfig4cpp::StringVector& config4cpp::ConfigItem::listVal() constvoid config4cpp::ConfigParser::parseRhsAssignStmt(config4cpp::LexToken&, short int)void config4cpp::ConfigParser::parseString(config4cpp::StringBuffer&)void config4cpp::ConfigParser::parseExec(config4cpp::StringBuffer&)void config4cpp::ConfigParser::getDirectoryOfFile(const char*, config4cpp::StringBuffer&)ConfigScope.ccm_type == Configuration::CFG_SCOPEm_scope != 0name[0] == '\0'.countWanted + countUnwanted == m_numEntriesitem->type() & Configuration::CFG_VARIABLESitem->type() == Configuration::CFG_SCOPEconfig4cpp::ConfigScope::ConfigScope(config4cpp::ConfigScope*, const char*)config4cpp::ConfigScope* config4cpp::ConfigItem::scopeVal() constvoid config4cpp::ConfigScope::listLocalNames(config4cpp::Configuration::Type, config4cpp::StringVector&) constvoid config4cpp::ConfigScope::dump(config4cpp::StringBuffer&, bool, int) const.Configuration.ccwStrLen != -1wPatternLen != -1static bool config4cpp::Configuration::patternMatch(const char*, const char*)N10config4cpp13ConfigurationEexec#file#ConfigurationImpl.ccm_type == Configuration::CFG_STRINGm_type == Configuration::CFG_LISTm_listVal != 0m_type == Configuration::CFG_SCOPEm_scope != 0cannot set default configuration: allow_patternsdeny_patternstrusted_directoriescannot set security configuration: cannot parse output of executing "" due to security restrictions0: variable '' was previously used as a scope: '' does not exist'scopeObj != 0i == len - 1scope != 0'' is not an entry' is not a scope' is a scope instead of a string' is a list instead of a string: no value specified for '' is a scope instead of a list' is a string instead of a list: bad value ('') specified for ''; should be one of: '',falsetrueboolean%d%d%c: non-integer value for 'str: Failed to extract uint64_t value from '%f%c: non-numeric value for ' value specified for '%f %s%s %%f%%c%d %s: invalid ('': should be ' ' where are,%s %%d%%c ' ' where aremicrosecondmicrosecondsmillisecondmillisecondssecondsecondsminuteminuteshourhoursdaydaysweekweeks infinitebytebytesBKBMBGBTBPB ' ' where are ' ' where aredurationMicrosecondscountDurationMicrosecondsInfo == countAllowedDurationMicrosecondsUnits; alternatively, you can use 'infinite'durationMillisecondsi < countDurationMillisecondsInfodurationSecondsi < countDurationSecondsInfo%d microseconds%d milliseconds%d secondsi < unitsInfoSizememorySizeBytesmemorySizeKBmemorySizeMB%d KB%d MB%f' is a string instead of a scope' is a list instead of a scope: scope '' does not existsize > 0strcmp(m_fileNameStack[size-1], fileName) == 0: line , circular include of 'scope '.' was previously used as a variable name/virtual void config4cpp::ConfigurationImpl::parse(config4cpp::Configuration::SourceType, const char*, const char*)const char* config4cpp::ConfigItem::stringVal() constconfig4cpp::StringVector& config4cpp::ConfigItem::listVal() constvirtual void config4cpp::ConfigurationImpl::remove(const char*, const char*)config4cpp::ConfigScope* config4cpp::ConfigItem::scopeVal() constconfig4cpp::ConfigItem* config4cpp::ConfigurationImpl::lookupHelper(config4cpp::ConfigScope*, const config4cpp::StringVector&) constvirtual const char* config4cpp::ConfigurationImpl::lookupString(const char*, const char*, const char*) constvirtual const char* config4cpp::ConfigurationImpl::lookupString(const char*, const char*) constvirtual void config4cpp::ConfigurationImpl::lookupList(const char*, const char*, const char**&, int&, const char**, int) constvirtual void config4cpp::ConfigurationImpl::lookupList(const char*, const char*, const char**&, int&) constvirtual void config4cpp::ConfigurationImpl::lookupList(const char*, const char*, config4cpp::StringVector&, const config4cpp::StringVector&) constvirtual void config4cpp::ConfigurationImpl::lookupList(const char*, const char*, config4cpp::StringVector&) constvirtual uint64_t config4cpp::ConfigurationImpl::stringToUint64(const char*, const char*, const char*) constvirtual int config4cpp::ConfigurationImpl::stringToDurationMicroseconds(const char*, const char*, const char*) constvirtual int config4cpp::ConfigurationImpl::stringToDurationMilliseconds(const char*, const char*, const char*) constvirtual int config4cpp::ConfigurationImpl::stringToDurationSeconds(const char*, const char*, const char*) constint config4cpp::ConfigurationImpl::stringToMemorySizeGeneric(const char*, config4cpp::SpellingAndValue*, int, const char**, const char*, const char*, const char*) constvirtual void config4cpp::ConfigurationImpl::lookupScope(const char*, const char*) constvoid config4cpp::ConfigurationImpl::popIncludedFilename(const char*)N10config4cpp17ConfigurationImplE#----------------------------------------------------------------------- # Default security checks for Config4* # ------------------------------------ # # allow_patterns is a list of wildcarded command lines that are allowed # to be executed (if the command resides in a directory listed in # trusted_directories). # deny_patterns is a list of wildcarded command lines that are # disallowed. # The wildcarded command-lines can contain "*", which denotes zero or # more characters. # trusted_directories is a list of directories in which the commands # listed in allow_patterns must be found. @if (osType() == "unix") { #-------- # Allow only a few commands that might be useful. allow_patterns = [ "curl *", "hostname", "uname", "uname *", "ifconfig" ]; # Disallow `...` (nested commands) and piped commands since we # have no idea what they might contain. deny_patterns = ["*`*", "*|*", "*>*"]; trusted_directories = ["/bin", "/usr/bin", "/usr/local/bin", "/sbin", "/usr/sbin"]; } @elseIf (osType() == "windows") { # Cygwin (or some other collection of UNIX-like tools) might # be installed on a Windows machine so the security # configuration is written accordingly. # The main difference from the UNIX settings is that # "deny_patterns" forbids the use of both UNIX and Windows-style # environment variables, that is, $NAME and %NAME%. "ipconfig" trusted_directories = [getenv("SYSTEMROOT") + "\system32"]; } @else { # If we don't know what operating system we are running on then # don't trust anything. allow_patterns = []; deny_patterns = ["*"]; trusted_directories = []; }; Config4* default securityallow_patternsdeny_patternstrusted_directories%s N10config4cpp28DefaultSecurityConfigurationELexBase.ccm_currSize > 1cannot open : cannot parse 'exec#': 0Invalid multi-byte character on line ?=!=!+&&||===;[]{}(),<...Fd%0{;K8m_ch == '"'Invalid escape sequence (%) in string on line config4cpp::LexBase::LexBase(config4cpp::Configuration::SourceType, const char*, config4cpp::UidIdentifierProcessor*)void config4cpp::StringBuffer::deleteLastChar()void config4cpp::LexBase::consumeString(config4cpp::LexToken&)N10config4cpp27UidIdentifierDummyProcessorEN10config4cpp7LexBaseEN10config4cpp8LexTokenE@ignoreEverythingIn@ignoreScopesIn@ignoreVariablesIn@optional@required@typedefN10config4cpp9SchemaLexEexpecting an identifier or keywordThere are multiple rules for ''expecting an identifieruid-Use of '@required' is incompatible with the uid- entry ('') in rule 'expecting '='Unknown type '' in rule 'expecting '['expecting an identifier, string or ']'expecting ','expecting ']'expecting expecting '@typedef'' in user-type definition 'error in validation rule '': near '; : bad value ('') for ''N10config4cpp10SchemaTypeEThe '' type should not take arguments in rule ''the value should be one of: 'false', 'true'N10config4cpp17SchemaTypeBooleanEThe '' type should take either no arguments or 2 arguments (denoting min and max durations) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be 'infinite' or in the format ' ' where is one of: 'microsecond', 'microseconds', 'second', 'seconds', 'minute', 'minutes' value for the second ('max') SchemaTypeDurationMicroseconds.ccmax == -1the value is outside the permitted range [, ]the value should be in the format ' ' microsecond, microseconds, second, seconds, minute, minutes; alternatively, you can use 'infinite'virtual bool config4cpp::SchemaTypeDurationMicroseconds::isA(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, int, config4cpp::StringBuffer&) constN10config4cpp30SchemaTypeDurationMicrosecondsEThe '' type should take either no arguments or 2 arguments (denoting min and max durations) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be 'infinite' or in the format ' ' where is one of: 'millisecond', 'milliseconds', 'second', 'seconds', 'minute', 'minutes', 'hour', 'hours', 'day', 'days', 'week', 'weeks value for the second ('max') SchemaTypeDurationMilliseconds.ccmax == -1the value is outside the permitted range [, ]the value should be in the format ' ' millisecond, milliseconds, second, seconds, minute, minutes, hour, hours, day, days, week, weeks; alternatively, you can use 'infinite'virtual bool config4cpp::SchemaTypeDurationMilliseconds::isA(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, int, config4cpp::StringBuffer&) constN10config4cpp30SchemaTypeDurationMillisecondsEThe '' type should take either no arguments or 2 arguments (denoting min and max durations) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be 'infinite' or in the format ' ' where is one of: 'second', 'seconds', 'minute', 'minutes', 'hour', 'hours', 'day', 'days', 'week', 'weeks value for the second ('max') SchemaTypeDurationSeconds.ccmax == -1the value is outside the permitted range [, ]the value should be in the format ' ' where is one of: second, seconds, minute, minutes, hour, hours, day, days, week, weeks; alternatively, you can use 'infinite'virtual bool config4cpp::SchemaTypeDurationSeconds::isA(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, int, config4cpp::StringBuffer&) constN10config4cpp25SchemaTypeDurationSecondsEThe '' type should take one or more arguments (denoting enum values) in rule ''the value should be one of: '',N10config4cpp14SchemaTypeEnumEthe '' type should take either no arguments or 2 arguments (denoting min and max values) in rule ''the first ('min') value is larger than the second ('max') argument in rule 'non-float value for the first ('min') argument in rule 'non-float value for the second ('max') argument in rule 'the value is outside the permitted range [, ]N10config4cpp15SchemaTypeFloatEThe '' type should take one or more arguments (denoting units) in rule ''the value should be in the format ' ' where is one of: '',N10config4cpp24SchemaTypeFloatWithUnitsEthe '' type should take either no arguments or 2 arguments (denoting min and max values) in rule ''the first ('min') value is larger than the second ('max') argument non-integer value for the first ('min') argument in rule 'non-integer value for the second ('max') argument in rule 'the value is outside the permitted range [, ]N10config4cpp13SchemaTypeIntEthe '' type should take one or more arguments (denoting units) in rule ''the value should be in the format ' ' where is one of: '',N10config4cpp22SchemaTypeIntWithUnitsEthe '' type requires one type argument in rule ''unknown type '' in rule 'you cannot embed a list type ('') inside another list in rule 'you cannot embed a scope type ('') inside a list in rule 'SchemaTypeList.cc0typeArgs.length() == 1elemTypeDef->cfgType() == Configuration::CFG_STRING; : bad value ('') for '[]'virtual void config4cpp::SchemaTypeList::checkRule(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const config4cpp::StringVector&, const char*) constvirtual void config4cpp::SchemaTypeList::validate(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const char*, const char*, const config4cpp::StringVector&, int) constN10config4cpp14SchemaTypeListEThe '' type should take either no arguments or 2 arguments (denoting min and max memory sizes) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be in the format ' ' where is one of: 'byte', 'bytes', 'KB', 'MB', GB value for the second ('max') the value is outside the permitted range [, ]the value should be in the format ' ' where is one of: 'byte', 'bytes', 'KB', 'MB', GBN10config4cpp25SchemaTypeMemorySizeBytesEThe '' type should take either no arguments or 2 arguments (denoting min and max memory sizes) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be in the format ' ' where is one of: 'KB', 'MB', 'GB', 'TB' value for the second ('max') ''KB', 'MB', 'GB', 'TB'the value is outside the permitted range [, ]the value should be in the format ' ' where is one of: 'KB', 'MB', 'GB', 'TB'N10config4cpp22SchemaTypeMemorySizeKBEThe '' type should take either no arguments or 2 arguments (denoting min and max memory sizes) in rule ''The 'min' and 'max' of a cannot be negative in rule '; min=; max=The first ('min') argument is larger than the second ('max') argument in rule 'Bad value for the first ('min') argument in rule ''; should be in the format ' ' where is one of: 'MB', 'GB', 'TB', 'PB' value for the second ('max') the value is outside the permitted range [, ]the value should be in the format ' ' where is one of: 'MB', 'GB', 'TB', 'PB'N10config4cpp22SchemaTypeMemorySizeMBEthe '' type should not take arguments in rule ''N10config4cpp15SchemaTypeScopeEthe '' type should take either no arguments or 2 arguments (denoting min_length and max_length values) in rule ''the 'min_length' and 'max_length' of a string cannot be negative in rule 'the first ('min_length') argument is larger than the second ('max_length') argument in rule 'non-integer value for the first ('min_length') argument non-integer value for the second ('max_length') argument its length is outside the permitted range [, ]N10config4cpp16SchemaTypeStringEthe '' type requires pairs of column-type and column-name arguments in rule ''unknown type '' in rule 'you cannot embed a list type ('') inside a table in rule 'you cannot embed a scope type ('SchemaTypeTable.cc0typeArgsSize != 0typeArgsSize % 2 == 0: the number of entries in the '' is not a multiple of ; : bad value ('') for the '' column in row of the 'virtual void config4cpp::SchemaTypeTable::checkRule(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const config4cpp::StringVector&, const char*) constvirtual void config4cpp::SchemaTypeTable::validate(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const char*, const char*, const config4cpp::StringVector&, int) constN10config4cpp15SchemaTypeTableEthe '' type requires pairs of type and name arguments in rule ''unknown type '' in rule 'you cannot embed a list type ('') inside a tuple in rule 'you cannot embed a scope type ('SchemaTypeTuple.cc0typeArgsSize != 0typeArgsSize % 2 == 0: there should be entries in the '' ; entries denote ',; : bad value ('') for element ('') of the 'virtual void config4cpp::SchemaTypeTuple::checkRule(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const config4cpp::StringVector&, const char*) constvirtual void config4cpp::SchemaTypeTuple::validate(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const char*, const char*, const config4cpp::StringVector&, int) constN10config4cpp15SchemaTypeTupleEyou cannot specify arguments when using user-defined type '' in ''SchemaTypeTypedef.cctypeArgs.length() == 0baseTypeDef != 0virtual void config4cpp::SchemaTypeTypedef::validate(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const char*, const char*, const config4cpp::StringVector&, int) constvirtual bool config4cpp::SchemaTypeTypedef::isA(const config4cpp::SchemaValidator*, const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, int, config4cpp::StringBuffer&) constN10config4cpp17SchemaTypeTypedefEThe '' type should take one or more arguments (denoting units) in rule ''the value should be in the format ' ' where is one of: '',N10config4cpp24SchemaTypeUnitsWithFloatEThe '' type should take one or more arguments (denoting units) in rule ''the value should be in the format ' ' where is one of: '',N10config4cpp22SchemaTypeUnitsWithIntEconfig4cpp::SchemaTypeBoolanbooleanconfig4cpp::SchemaTypeDurationMicrosecondsdurationMicrosecondsconfig4cpp::SchemaTypeDurationMillisecondsdurationMillisecondsconfig4cpp::SchemaTypeDurationSecondsdurationSecondsconfig4cpp::SchemaTypeDummyconfig4cpp::SchemaTypeEnumenumconfig4cpp::SchemaTypeFloatfloatconfig4cpp::SchemaTypeFloatWithUnitsfloat_with_unitsconfig4cpp::SchemaTypeIntintconfig4cpp::SchemaTypeIntWithUnitsint_with_unitsconfig4cpp::SchemaTypeListlistconfig4cpp::SchemaTypeMemorySizeBytesmemorySizeBytesconfig4cpp::SchemaTypeMemorySizeKBmemorySizeKBconfig4cpp::SchemaTypeMemorySizeMBmemorySizeMBconfig4cpp::SchemaTypeScopescopeconfig4cpp::SchemaTypeStringstringconfig4cpp::SchemaTypeTabletableconfig4cpp::SchemaTypeTupletupleconfig4cpp::SchemaTypeTypedefconfig4cpp::SchemaTypeUnitsWithFloatunits_with_floatconfig4cpp::SchemaTypeUnitsWithIntunits_with_intSchemaValidator.cc*result != 0typeDef != 00schema type '' is already registed---- config4cpp::SchemaValidator::parseSchema() %s: start %s: end %s: error: %s ---- config4cpp::SchemaValidator::validate() ignoring '%s' : the '' scope is unknown.' variable is unknown. %s: error: %s uid-: the '' does not existstrstr(nameInRule, "uid-") != 0symbol == SchemaLex::LEX_IGNORE_SCOPES_IN_SYM typeArgs = ["%s", ]typeName = "%s"; typeArgs = [start %s::checkRule() rule = "%s" end %s::checkRule() exception thrown from %s::checkRule(): %s start %s::validate() scope = "%s"; name = "%s" typeName = "%s"; origTypeName = "%s" end %s::validate() exception thrown from %s::validate(): %s start %s::isA() value = "%s" end %s::isA() truefalseresult = %s; errSuffix = "%s" exception thrown from %s::isA(): %s config4cpp::SchemaType* config4cpp::SchemaValidator::findType(const char*) constconfig4cpp::SchemaValidator::SchemaValidator()void config4cpp::SchemaValidator::validate(const config4cpp::Configuration*, const char*, const char*, const config4cpp::StringVector&, config4cpp::SchemaValidator::ForceMode) constvoid config4cpp::SchemaValidator::validateRequiredUidEntry(const config4cpp::Configuration*, const char*, config4cpp::SchemaIdRuleInfo*) constbool config4cpp::SchemaValidator::shouldIgnore(const config4cpp::Configuration*, const char*, const char*, const char*) constN10config4cpp15SchemaTypeDummyEN10config4cpp15SchemaValidatorE%d%fStringVector.ccinitialCapacity > 0index < m_currSizem_array[m_currSize] == 0m_currSize > 0config4cpp::StringVector::StringVector(int)void config4cpp::StringVector::replace(int, const char*)void config4cpp::StringVector::replaceWithOwnership(int, char*)void config4cpp::StringVector::c_array(const char**&, int&) constconst char** config4cpp::StringVector::c_array() constvoid config4cpp::StringVector::removeLast()const char* config4cpp::StringVector::operator[](int) constuid-.'' is not a legal identifierUidIdentifierProcessor.ccm_count < 1000 * 1000 * 1000%09ld-count > 0void config4cpp::UidIdentifierProcessor::expandOne(config4cpp::StringBuffer&)N10config4cpp22UidIdentifierProcessorEplatform.ccm_currSize > 1 2>&1rcannot execute '': popen() failed/m_file == 0m_file != 0void config4cpp::StringBuffer::deleteLastChar()bool config4cpp::BufferedFileReader::open(const char*)int config4cpp::BufferedFileReader::getChar()Cache configurations must be of the form sets:ways:blocksizewhere sets, ways, and blocksize are positive integers, withsets and blocksize both powers of two and blocksize at least 8. Bytes Read: Bytes Written: Read Accesses: Write Accesses: Read Misses: Write Misses: Writebacks: Miss Rate: Bbasic_string::_S_construct null not valid14fa_cache_sim_t11cache_sim_t 7clint_t trap_load_address_misalignedtrap_store_address_misalignedoo@o@s${s$@# D@tcs$@D@t$o#&ss$ {#"g0s$@#$s$ {s {hERROR: invalid load from debug module: %zd bytes at 0x%016lx debug_module.cclen == 4ERROR: invalid store to debug module: %zd bytes at 0x%016lx dmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true dmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true vector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)virtual bool debug_module_t::store(reg_t, size_t, const uint8_t*)17trigger_matched_t22trap_load_access_fault29trap_store_address_misaligned28trap_load_address_misaligned10mem_trap_t14debug_module_t Plugin device type "" already registered!map::at5bus_t trap_load_address_misaligneddummy_roccZN19register_dummy_roccC4EvEUlvE_12dummy_rocc_t trap_instruction_address_misaligned0x%04x0x%08x0x%016lx0x%016lx%016lx#Fi;^ 0Sv%Hk=`2Ux'Jm?b4Wz ) L o  A d  6 Y |  + N q C f 8[~ -Ps"Eh:] /Ru$Gj<_1Tw&Il>a3Vy(Kn@c5X{*MpBe7Z} ,Or! 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"."Q"t""""###F#i#####$;$^$$$$$ %0%S%v%%%%&%&H&k&&&&&'='`'''''(2(U(x(((()')J)m)))))*?*b*****+4+W+z++++,),L,o,,,,,-A-d-----.6.Y.|..../+/N/q///// 0C0f00000181[1~1111 2-2P2s22222"3E3h333334:4]44444 5/5R5u55556$6G6j666667<7_77777818T8w88889&9I9l99999:>:a:::::;3;V;y;;;;<(<K<n<<<<<=@=c=====>5>X>{>>>>?*?M?p?????@B@e@@@@@A7AZA}AAAA B,BOBrBBBBB!CDCgCCCCCD9D\DDDDD E.EQEtEEEEF#FFFiFFFFFG;G^GGGGG H0HSHvHHHHI%IHIkIIIIIJ=J`JJJJJK2KUKxKKKKL'LJLmLLLLLM?MbMMMMMN4NWNzNNNNO)OLOoOOOOOPAPdPPPPPQ6QYQ|QQQQR+RNRqRRRRR SCSfSSSSST8T[T~TTTT U-UPUsUUUUU"VEVhVVVVVW:W]WWWWW X/XRXuXXXXY$YGYjYYYYYZ]a]]]]]^3^V^y^^^^_(_K_n_____`@`c`````a5aXa{aaaab*bMbpbbbbbcBcecccccd7dZd}dddd e,eOereeeee!fDfgfffffg9g\ggggg h.hQhthhhhi#iFiiiiiiij;j^jjjjj k0kSkvkkkkl%lHlklllllm=m`mmmmmn2nUnxnnnno'oJomooooop?pbpppppq4qWqzqqqqr)rLrorrrrrsAsdssssst6tYt|ttttu+uNuquuuuu vCvfvvvvvw8w[w~wwww x-xPxsxxxxx"yEyhyyyyyz:z]zzzzz {/{R{u{{{{|$|G|j|||||}<}_}}}}}~1~T~w~~~~&Il>aʀ3Vy(Knׂ@c̃5X{*MpمBeΆ7Z}Ç ,Orۈ!DgЉ9\Ŋ .Qt݋35trap_instruction_address_misaligned trap_illegal_instructiona COP exception was posted, but interrupts are disabled!11extension_t24trap_illegal_instruction lib.socouldn't find extension '%s' (or library '%s') context.ccthis != curcontext_t::~context_t()void context_t::switch_to()%lubcdidentitydevice.cccmd < command_t::MAX_COMMANDSstrlen(name) < IDENTITY_SIZEaddr % IDENTITY_SIZE == 0strlen(identity()) < IDENTITY_SIZEreadwritecould not open could not stat disk size=could not read @ could not write num_devices < command_t::MAX_DEVICESbasic_string::_S_construct null not validvoid device_t::register_command(size_t, device_t::command_func_t, const char*)void device_t::handle_identify(command_t)void device_list_t::register_device(device_t*)St5_BindIFM6disk_tFv9command_tEPS0_St12_PlaceholderILi1EEEESt5_BindIFM5bcd_tFv9command_tEPS0_St12_PlaceholderILi1EEEESt5_BindIFM8device_tFv9command_tEPS0_St12_PlaceholderILi1EEEE13null_device_t6disk_t5bcd_t8device_tSt17_Weak_result_typeIM6disk_tFv9command_tEESt17_Weak_result_typeIM5bcd_tFv9command_tEESt17_Weak_result_typeIM8device_tFv9command_tEESt22_Weak_result_type_implIM6disk_tFv9command_tEESt22_Weak_result_type_implIM5bcd_tFv9command_tEESt22_Weak_result_type_implIM8device_tFv9command_tEEdtm.ccresp_buf.resp == 0program_n <= ram_wordsdata_n <= data_wordsOTHERERROR: %s:%d, Debug Abstract Command Error #%d (%s)ERROR: %s:%d, Should die, but allowing simulation to continue and fail.OKBUSYNOT_SUPPORTEDEXCEPTIONHALT/RESUMEFESVR DTM Does not support 128-bitFESVR DTM can't determine XLEN. Aborting(((hartinfo) & ((0xf << 20))) / (((0xf << 20)) & ~(((0xf << 20)) << 1))) > 0(((hartinfo) & ((0x1 << 16))) / (((0x1 << 16)) & ~(((0x1 << 16)) << 1)))resp_waituint32_t dtm_t::do_command(dtm_t::req)uint32_t dtm_t::run_abstract_command(uint32_t, const uint32_t*, size_t, uint32_t*, size_t)void dtm_t::producer_thread()void dtm_t::tick(bool, bool, dtm_t::resp)5dtm_telfloader.ccfd != -1buf != ((void *) -1)size >= sizeof(Elf64_Ehdr)(((*eh64).e_ident[0] == 0x7f && (*eh64).e_ident[1] == 'E' && (*eh64).e_ident[2] == 'L' && (*eh64).e_ident[3] == 'F') && (*eh64).e_ident[4] == 1) || (((*eh64).e_ident[0] == 0x7f && (*eh64).e_ident[1] == 'E' && (*eh64).e_ident[2] == 'L' && (*eh64).e_ident[3] == 'F') && (*eh64).e_ident[4] == 2)size >= eh->e_phoff + eh->e_phnum*sizeof(*ph)size >= ph[i].p_offset + ph[i].p_fileszsize >= eh->e_shoff + eh->e_shnum*sizeof(*sh)eh->e_shstrndx < eh->e_shnumsize >= sh[eh->e_shstrndx].sh_offset + sh[eh->e_shstrndx].sh_sizesh[i].sh_name < sh[eh->e_shstrndx].sh_sizestrnlen(shstrtab + sh[i].sh_name, max_len) < max_lensize >= sh[i].sh_offset + sh[i].sh_size.strtab.symtabsym[i].st_name < sh[strtabidx].sh_sizestrnlen(strtab + sym[i].st_name, max_len) < max_lenvector::_M_default_appendstd::map, long unsigned int> load_elf(const char*, memif_t*, reg_t*)syscall_proxyhtifnone//riscv64-unknown-elf/bin/could not open (did you misspell it? If VCS, did you forget +permissive/+permissive-off?)tohostfromhostwarning: tohost and fromhost symbols not in ELF; can't communicate with target begin_signatureend_signaturehtif.ccsigs && "can't open signature file!"sig_len % incr == 0helprfbdisksignaturechroot-hUser quered htif_t help text--disk/+disk unsupported (use a ramdisk)Unknown argument (did you mean to enable +permissive parsing?)+rfb+rfb=+disk=+signature=+chroot=+permissive-offFound +permissive-off when not parsing permissively+permissiveFound +permissive when already parsing permissivelyNo binary specified (Did you forget it? Did you forget '+permissive-off' if running with +permissive?)Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]... Run a BINARY on the Rocket Chip emulator. Mandatory arguments to long options are mandatory for short options too. EMULATOR OPTIONS Consult emulator.cc if using Verilator or VCS documentation if using VCS for available options. EMUALTOR VERILOG PLUSARGS Consult generated-src*/*.plusArgs for available options HOST OPTIONS -h, --help Display this help and exit +permissive The host will ignore any unparsed options up until +permissive-off (Only needed for VCS) +permissive-off Stop ignoring options. This is mandatory if using +permissive (Only needed for VCS) --rfb=DISPLAY Add new remote frame buffer on display DISPLAY +rfb=DISPLAY to be accessible on 5900 + DISPLAY (default = 0) --signature=FILE Write torture test signature to FILE +signature=FILE --chroot=PATH Use PATH as location of syscall-servicing binaries +chroot=PATH HOST OPTIONS (currently unsupported) --disk=DISK Add DISK device. Use a ramdisk since this isn't +disk=DISK supported TARGET (RISC-V BINARY) OPTIONS These are the options passed to the program executing on the emulated RISC-V microprocessor. vector::_M_realloc_insert*St5_BindIFZN6htif_t3runEvEUlPSt5queueImSt5dequeImSaImEEEmE_S6_St12_PlaceholderILi1EEEE*ZN6htif_t12load_programEvE21preload_aware_memif_t*St17_Weak_result_typeIZN6htif_t3runEvEUlPSt5queueImSt5dequeImSaImEEEmE_E*St22_Weak_result_type_implIZN6htif_t3runEvEUlPSt5queueImSt5dequeImSaImEEEmE_E*St22_Maybe_get_result_typeIZN6htif_t3runEvEUlPSt5queueImSt5dequeImSaImEEEmE_vEvirtual void htif_t::stop()6htif_t15chunked_memif_t9syscall_thtif_hexwriter.cclen % chunk_align() == 0taddr < width*depthtaddr+len <= width*depth00vector::_M_fill_insertvirtual void htif_hexwriter_t::read_chunk(addr_t, size_t, void*)virtual void htif_hexwriter_t::write_chunk(addr_t, size_t, const void*)16htif_hexwriter_tdeque::_M_new_elements_at_frontdeque::_M_new_elements_at_back14htif_pthread_tmisaligned address7memif_toption_parser.ccargv0no argument allowed for optionargument required for optionunrecognized option%s: %s %s vector::_M_realloc_insertconst char* const* option_parser_t::parse(const char* const*)%drfbconfigureset_addresscould not acquire tcp socketcould not bind to port could not listen on port could not accept connectionRFB 003.003 bad client versionRISC-Vbad pixel formatcould not writecould not readreceived oversized packetyou must only set the rfb configuration oncerfb requires 32 bpp true colorrfb size must be a multiple of could not create threadrfb address must be -byte alignedbasic_string::_S_construct null not validSt5_BindIFM5rfb_tFv9command_tEPS0_St12_PlaceholderILi1EEEE5rfb_tSt17_Weak_result_typeIM5rfb_tFv9command_tEESt22_Weak_result_type_implIM5rfb_tFv9command_tEE%lusyscall_proxysyscallcould not dup stdin/stdout/*** FAILED *** (tohost = )bad syscall #could not chroot to %s vector::_M_default_appendbasic_string::_S_construct null not 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trap_illegal_instruction trap_illegal_instruction  trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instructiontrap_store_address_misaligned trap_illegal_instruction trap_store_address_misaligned  trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction      trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction  trap_illegal_instruction trap_illegal_instruction trap_illegal_instruction  trap_illegal_instruction trap_store_address_misaligned trap_illegal_instruction   trap_load_address_misalignedtrap_interactive runrrsregfregfregsfregdpcmemstruntilwhilequitqhelph: Unknown command %s Interactive commands: reg [reg] # Display [reg] (all if omitted) in fregs # Display single precision in fregd # Display double precision in pc # Show current PC in mem # Show contents of physical memory str # Show NUL-terminated C string until reg # Stop when in hits until pc # Stop when PC in hits until mem # Stop when memory becomes while reg # Run while in is while pc # Run while PC in is while mem # Run while memory is run [count] # Resume noisy execution (until [count] insns) r [count] Alias for run rs [count] # Resume silent execution (until [count] insns) quit # End the simulation q Alias for quit help # This screen! h Alias for help Note: Hitting enter is the same as: run 1 0x%016lx fflagsfrmfcsrcycletimeinstrethpmcounter3hpmcounter4hpmcounter5hpmcounter6hpmcounter7hpmcounter8hpmcounter9hpmcounter10hpmcounter11hpmcounter12hpmcounter13hpmcounter14hpmcounter15hpmcounter16hpmcounter17hpmcounter18hpmcounter19hpmcounter20hpmcounter21hpmcounter22hpmcounter23hpmcounter24hpmcounter25hpmcounter26hpmcounter27hpmcounter28hpmcounter29hpmcounter30hpmcounter31sstatussiestvecscounterensscratchsepcscausestvalsipsatpmstatusmisamedelegmidelegmiemtvecmcounterenmscratchmepcmcausemtvalmippmpcfg0pmpcfg1pmpcfg2pmpcfg3pmpaddr0pmpaddr1pmpaddr2pmpaddr3pmpaddr4pmpaddr5pmpaddr6pmpaddr7pmpaddr8pmpaddr9pmpaddr10pmpaddr11pmpaddr12pmpaddr13pmpaddr14pmpaddr15tselecttdata1tdata2tdata3dcsrdpcdscratchmcycleminstretmhpmcounter3mhpmcounter4mhpmcounter5mhpmcounter6mhpmcounter7mhpmcounter8mhpmcounter9mhpmcounter10mhpmcounter11mhpmcounter12mhpmcounter13mhpmcounter14mhpmcounter15mhpmcounter16mhpmcounter17mhpmcounter18mhpmcounter19mhpmcounter20mhpmcounter21mhpmcounter22mhpmcounter23mhpmcounter24mhpmcounter25mhpmcounter26mhpmcounter27mhpmcounter28mhpmcounter29mhpmcounter30mhpmcounter31mhpmevent3mhpmevent4mhpmevent5mhpmevent6mhpmevent7mhpmevent8mhpmevent9mhpmevent10mhpmevent11mhpmevent12mhpmevent13mhpmevent14mhpmevent15mhpmevent16mhpmevent17mhpmevent18mhpmevent19mhpmevent20mhpmevent21mhpmevent22mhpmevent23mhpmevent24mhpmevent25mhpmevent26mhpmevent27mhpmevent28mhpmevent29mhpmevent30mhpmevent31mvendoridmarchidmimpidmhartidcyclehtimehinstrethhpmcounter3hhpmcounter4hhpmcounter5hhpmcounter6hhpmcounter7hhpmcounter8hhpmcounter9hhpmcounter10hhpmcounter11hhpmcounter12hhpmcounter13hhpmcounter14hhpmcounter15hhpmcounter16hhpmcounter17hhpmcounter18hhpmcounter19hhpmcounter20hhpmcounter21hhpmcounter22hhpmcounter23hhpmcounter24hhpmcounter25hhpmcounter26hhpmcounter27hhpmcounter28hhpmcounter29hhpmcounter30hhpmcounter31hmcyclehminstrethmhpmcounter3hmhpmcounter4hmhpmcounter5hmhpmcounter6hmhpmcounter7hmhpmcounter8hmhpmcounter9hmhpmcounter10hmhpmcounter11hmhpmcounter12hmhpmcounter13hmhpmcounter14hmhpmcounter15hmhpmcounter16hmhpmcounter17hmhpmcounter18hmhpmcounter19hmhpmcounter20hmhpmcounter21hmhpmcounter22hmhpmcounter23hmhpmcounter24hmhpmcounter25hmhpmcounter26hmhpmcounter27hmhpmcounter28hmhpmcounter29hmhpmcounter30hmhpmcounter31h%-4s: 0x%016lx 0x%016lx%016lx %g vector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)vector::_M_realloc_insert16trap_interactive      trap_instruction_access_faulttrap_load_access_faulttrap_store_access_faulttrap_instruction_page_faulttrap_load_page_faulttrap_store_page_faultvector::_M_realloc_insert16memtracer_list_t11memtracer_t27trap_instruction_page_fault29trap_instruction_access_fault %utrap_illegal_instructionerror: bad --isa option %s imafdqcrv32rv64rvimafdcimafdPC Histogram support has not been properly enabled; please re-build the riscv-isa-run project using "configure --enable-histogram". processor.ccprv <= 3core %3d: exception %s, epc 0x%016lx core %3d: tval 0x%016lx core %3d: Executed %lx times core %3d: 0x%016lx (0x%08lx) %s xlen == max_xlenonly one extension may be registeredvector::_M_realloc_insertbasic_string::_S_construct null not validreg_t processor_t::legalize_privilege(reg_t)int processor_t::paddr_bits()11processor_t zeroraspgptpt0t1t2s0s1a0a1a2a3a4a5a6a7s2s3s4s5s6s7s8s9s10s11t3t4t5t6ft0ft1ft2ft3ft4ft5ft6ft7fs0fs1fa0fa1fa2fa3fa4fa5fa6fa7fs2fs3fs4fs5fs6fs7fs8fs9fs10fs11ft8ft9ft10ft11remote_bitbang failed to make socket: %s (%d) remote_bitbang failed setsockopt: %s (%d) remote_bitbang failed to bind socket: %s (%d) remote_bitbang failed to listen on socket: %s (%d) remote_bitbang getsockname failed: %s (%d) Listening for remote bitbang connection on port %d. failed to accept on socket: %s (%d) remote_bitbang got unsupported command '%c' failed to write to socket: %s (%d) remote_bitbang failed to read on socket: %s (%d) Remote Bitbang received 'Q' Received nothing. Quitting. %luzero bytes of target memory requestedcouldn't allocate bytes of target memoryRV32IMTEST2048vector::_M_realloc_insertbasic_string::_S_construct null not validNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvP5sim_tES4_EEEEEEPFP17abstract_device_tRKSsE5mem_tFP17abstract_device_tRKSsE vector::_M_realloc_insert6rocc_t 12rom_device_t trap_load_address_misalignedtrap_store_address_misalignedNumber of specified hartids doesn't match number of processorsFailed to fork dts child: Failed to write dts: Failed to fork dtb child: dtb-O/usr/bin/dtcFailed to run /usr/bin/dtc: Failed to read dtb: Child dts process failedChild dtb process failed/dts-v1/; / { #address-cells = <2>; #size-cells = <2>; compatible = "ucbbar,spike-bare-dev"; model = "ucbbar,spike-bare"; cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <>; CPU: cpu@ { device_type = "cpu"; reg = <>; status = "okay"; compatible = "riscv"; riscv,isa = ""; mmu-type = "riscv,sv32sv48"; clock-frequency = <>; CPU_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; }; memory@ { device_type = "memory"; reg = <0x 0x>; }; soc { #address-cells = <2>; #size-cells = <2>; compatible = "ucbbar,spike-bare-soc", "simple-bus"; ranges; clint@ { compatible = "riscv,clint0"; interrupts-extended = <&CPU_intc 3 &CPU_intc 7 >; reg = <0x>; }; }; htif { compatible = "ucb,htif0"; }; }; sim.cclen == 8vector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)vector::_M_default_appendvector::_M_range_insertvirtual void sim_t::read_chunk(addr_t, size_t, void*)virtual void sim_t::write_chunk(addr_t, size_t, const void*)5sim_t7simif_tɴ}šC)ڵ퍷ƈm$ấB!-Əx(i\5Rt>Jh+C^co׭ƣz<2~,֡w ۍv;md\]VPUKyFB %d%lu, (fflagsfrmfcsrcycletimeinstrethpmcounter3hpmcounter4hpmcounter5hpmcounter6hpmcounter7hpmcounter8hpmcounter9hpmcounter10hpmcounter11hpmcounter12hpmcounter13hpmcounter14hpmcounter15hpmcounter16hpmcounter17hpmcounter18hpmcounter19hpmcounter20hpmcounter21hpmcounter22hpmcounter23hpmcounter24hpmcounter25hpmcounter26hpmcounter27hpmcounter28hpmcounter29hpmcounter30hpmcounter31sstatussiestvecscounterensscratchsepcscausestvalsipsatpmstatusmisamedelegmidelegmiemtvecmcounterenmscratchmepcmcausemtvalmippmpcfg0pmpcfg1pmpcfg2pmpcfg3pmpaddr0pmpaddr1pmpaddr2pmpaddr3pmpaddr4pmpaddr5pmpaddr6pmpaddr7pmpaddr8pmpaddr9pmpaddr10pmpaddr11pmpaddr12pmpaddr13pmpaddr14pmpaddr15tselecttdata1tdata2tdata3dcsrdpcdscratchmcycleminstretmhpmcounter3mhpmcounter4mhpmcounter5mhpmcounter6mhpmcounter7mhpmcounter8mhpmcounter9mhpmcounter10mhpmcounter11mhpmcounter12mhpmcounter13mhpmcounter14mhpmcounter15mhpmcounter16mhpmcounter17mhpmcounter18mhpmcounter19mhpmcounter20mhpmcounter21mhpmcounter22mhpmcounter23mhpmcounter24mhpmcounter25mhpmcounter26mhpmcounter27mhpmcounter28mhpmcounter29mhpmcounter30mhpmcounter31mhpmevent3mhpmevent4mhpmevent5mhpmevent6mhpmevent7mhpmevent8mhpmevent9mhpmevent10mhpmevent11mhpmevent12mhpmevent13mhpmevent14mhpmevent15mhpmevent16mhpmevent17mhpmevent18mhpmevent19mhpmevent20mhpmevent21mhpmevent22mhpmevent23mhpmevent24mhpmevent25mhpmevent26mhpmevent27mhpmevent28mhpmevent29mhpmevent30mhpmevent31mvendoridmarchidmimpidmhartidcyclehtimehinstrethhpmcounter3hhpmcounter4hhpmcounter5hhpmcounter6hhpmcounter7hhpmcounter8hhpmcounter9hhpmcounter10hhpmcounter11hhpmcounter12hhpmcounter13hhpmcounter14hhpmcounter15hhpmcounter16hhpmcounter17hhpmcounter18hhpmcounter19hhpmcounter20hhpmcounter21hhpmcounter22hhpmcounter23hhpmcounter24hhpmcounter25hhpmcounter26hhpmcounter27hhpmcounter28hhpmcounter29hhpmcounter30hhpmcounter31hmcyclehminstrethmhpmcounter3hmhpmcounter4hmhpmcounter5hmhpmcounter6hmhpmcounter7hmhpmcounter8hmhpmcounter9hmhpmcounter10hmhpmcounter11hmhpmcounter12hmhpmcounter13hmhpmcounter14hmhpmcounter15hmhpmcounter16hmhpmcounter17hmhpmcounter18hmhpmcounter19hmhpmcounter20hmhpmcounter21hmhpmcounter22hmhpmcounter23hmhpmcounter24hmhpmcounter25hmhpmcounter26hmhpmcounter27hmhpmcounter28hmhpmcounter29hmhpmcounter30hmhpmcounter31hunknown_%03lx0xpc 0xunknownlblbulhlhulwlwuldsbshswsdamoadd_wamoswap_wamoand_wamoor_wamoxor_wamomin_wamomax_wamominu_wamomaxu_wamoadd_damoswap_damoand_damoor_damoxor_damomin_damomax_damominu_damomaxu_dlr_wsc_wlr_dsc_dflwfldflqfswfsdfsqjjalbeqzbnezbltzbgezbeqbnebltbgebltubgeuluiauipcretjrjalrnop - limvaddisllisltiseqzsltiunotxorisrlisraioriandisext.waddiwslliwsrliwsraiwaddsubsllsltsnezsltuxorsrlsraorandmulmulhmulhumulhsudivdivuremremuaddwsubwsllwsrlwsrawmulwdivwdivuwremwremuwecallebreakuretsretmretfencefence_icsrrcsrwcsrscsrccsrwicsrsicsrcicsrrwcsrrscsrrccsrrwicsrrsicsrrcifadd_sfsub_sfmul_sfdiv_sfsqrt_sfmin_sfmax_sfmadd_sfmsub_sfnmadd_sfnmsub_sfsgnj_sfsgnjn_sfsgnjx_sfcvt_s_dfcvt_s_qfcvt_s_lfcvt_s_lufcvt_s_wfcvt_s_wufmv_w_xfcvt_l_sfcvt_lu_sfcvt_w_sfcvt_wu_sfclass_sfmv_x_wfeq_sflt_sfle_sfadd_dfsub_dfmul_dfdiv_dfsqrt_dfmin_dfmax_dfmadd_dfmsub_dfnmadd_dfnmsub_dfsgnj_dfsgnjn_dfsgnjx_dfcvt_d_sfcvt_d_qfcvt_d_lfcvt_d_lufcvt_d_wfcvt_d_wufmv_d_xfcvt_l_dfcvt_lu_dfcvt_w_dfcvt_wu_dfclass_dfmv_x_dfeq_dflt_dfle_dfadd_qfsub_qfmul_qfdiv_qfsqrt_qfmin_qfmax_qfmadd_qfmsub_qfnmadd_qfnmsub_qfsgnj_qfsgnjn_qfsgnjx_qfcvt_q_sfcvt_q_dfcvt_q_lfcvt_q_lufcvt_q_wfcvt_q_wufmv_q_xfcvt_l_qfcvt_lu_qfcvt_w_qfcvt_wu_qfclass_qfmv_x_qfeq_qflt_qfle_qbeq (args unknown)bne (args unknown)blt (args unknown)bge (args unknown)bltu (args unknown)bgeu (args unknown)jalr (args unknown)jal (args unknown)lui (args unknown)auipc (args unknown)addi (args unknown)slli (args unknown)slti (args unknown)sltiu (args unknown)xori (args unknown)srli (args unknown)srai (args unknown)ori (args unknown)andi (args unknown)add (args unknown)sub (args unknown)sll (args unknown)slt (args unknown)sltu (args unknown)xor (args unknown)srl (args unknown)sra (args unknown)or (args unknown)and (args unknown)addiw (args unknown)slliw (args unknown)srliw (args unknown)sraiw (args unknown)addw (args unknown)subw (args unknown)sllw (args unknown)srlw (args unknown)sraw (args unknown)lb (args unknown)lh (args unknown)lw (args unknown)ld (args unknown)lbu (args unknown)lhu (args unknown)lwu (args unknown)sb (args unknown)sh (args unknown)sw (args unknown)sd (args unknown)fence (args unknown)fence_i (args unknown)mul (args unknown)mulh (args unknown)mulhsu (args unknown)mulhu (args unknown)div (args unknown)divu (args unknown)rem (args unknown)remu (args unknown)mulw (args unknown)divw (args unknown)divuw (args unknown)remw (args unknown)remuw (args unknown)amoadd_w (args unknown)amoxor_w (args unknown)amoor_w (args unknown)amoand_w (args unknown)amomin_w (args unknown)amomax_w (args unknown)amominu_w (args unknown)amomaxu_w (args unknown)amoswap_w (args unknown)lr_w (args unknown)sc_w (args unknown)amoadd_d (args unknown)amoxor_d (args unknown)amoor_d (args unknown)amoand_d (args unknown)amomin_d (args unknown)amomax_d (args unknown)amominu_d (args unknown)amomaxu_d (args unknown)amoswap_d (args unknown)lr_d (args unknown)sc_d (args unknown)ecall (args unknown)ebreak (args unknown)uret (args unknown)sret (args unknown)mret (args unknown)dret (args unknown)sfence_vma (args unknown)wfi (args unknown)csrrw (args unknown)csrrs (args unknown)csrrc (args unknown)csrrwi (args unknown)csrrsi (args unknown)csrrci (args unknown)fadd_s (args unknown)fsub_s (args unknown)fmul_s (args unknown)fdiv_s (args unknown)fsgnj_s (args unknown)fsgnjn_s (args unknown)fsgnjx_s (args unknown)fmin_s (args unknown)fmax_s (args unknown)fsqrt_s (args unknown)fadd_d (args unknown)fsub_d (args unknown)fmul_d (args unknown)fdiv_d (args unknown)fsgnj_d (args unknown)fsgnjn_d (args unknown)fsgnjx_d (args unknown)fmin_d (args unknown)fmax_d (args unknown)fcvt_s_d (args unknown)fcvt_d_s (args unknown)fsqrt_d (args unknown)fadd_q (args unknown)fsub_q (args unknown)fmul_q (args unknown)fdiv_q (args unknown)fsgnj_q (args unknown)fsgnjn_q (args unknown)fsgnjx_q (args unknown)fmin_q (args unknown)fmax_q (args unknown)fcvt_s_q (args unknown)fcvt_q_s (args unknown)fcvt_d_q (args unknown)fcvt_q_d (args unknown)fsqrt_q (args unknown)fle_s (args unknown)flt_s (args unknown)feq_s (args unknown)fle_d (args unknown)flt_d (args unknown)feq_d (args unknown)fle_q (args unknown)flt_q (args unknown)feq_q (args unknown)fcvt_w_s (args unknown)fcvt_wu_s (args unknown)fcvt_l_s (args unknown)fcvt_lu_s (args unknown)fmv_x_w (args unknown)fclass_s (args unknown)fcvt_w_d (args unknown)fcvt_wu_d (args unknown)fcvt_l_d (args unknown)fcvt_lu_d (args unknown)fmv_x_d (args unknown)fclass_d (args unknown)fcvt_w_q (args unknown)fcvt_wu_q (args unknown)fcvt_l_q (args unknown)fcvt_lu_q (args unknown)fmv_x_q (args unknown)fclass_q (args unknown)fcvt_s_w (args unknown)fcvt_s_wu (args unknown)fcvt_s_l (args unknown)fcvt_s_lu (args unknown)fmv_w_x (args unknown)fcvt_d_w (args unknown)fcvt_d_wu (args unknown)fcvt_d_l (args unknown)fcvt_d_lu (args unknown)fmv_d_x (args unknown)fcvt_q_w (args unknown)fcvt_q_wu (args unknown)fcvt_q_l (args unknown)fcvt_q_lu (args unknown)fmv_q_x (args unknown)flw (args unknown)fld (args unknown)flq (args unknown)fsw (args unknown)fsd (args unknown)fsq (args unknown)fmadd_s (args unknown)fmsub_s (args unknown)fnmsub_s (args unknown)fnmadd_s (args unknown)fmadd_d (args unknown)fmsub_d (args unknown)fnmsub_d (args unknown)fnmadd_d (args unknown)fmadd_q (args unknown)fmsub_q (args unknown)fnmsub_q (args unknown)fnmadd_q (args unknown)c_nop (args unknown)c_addi16sp (args unknown)c_jr (args unknown)c_jalr (args unknown)c_ebreak (args unknown)c_ld (args unknown)c_sd (args unknown)c_addiw (args unknown)c_ldsp (args unknown)c_sdsp (args unknown)c_addi4spn (args unknown)c_fld (args unknown)c_lw (args unknown)c_flw (args unknown)c_fsd (args unknown)c_sw (args unknown)c_fsw (args unknown)c_addi (args unknown)c_jal (args unknown)c_li (args unknown)c_lui (args unknown)c_srli (args unknown)c_srai (args unknown)c_andi (args unknown)c_sub (args unknown)c_xor (args unknown)c_or (args unknown)c_and (args unknown)c_subw (args unknown)c_addw (args unknown)c_j (args unknown)c_beqz (args unknown)c_bnez (args unknown)c_slli (args unknown)c_fldsp (args unknown)c_lwsp (args unknown)c_flwsp (args unknown)c_mv (args unknown)c_add (args unknown)c_fsdsp (args unknown)c_swsp (args unknown)c_fswsp (args unknown)custom0 (args unknown)custom0_rs1 (args unknown)custom0_rs1_rs2 (args unknown)custom0_rd (args unknown)custom0_rd_rs1 (args unknown)custom0_rd_rs1_rs2 (args unknown)custom1 (args unknown)custom1_rs1 (args unknown)custom1_rs1_rs2 (args unknown)custom1_rd (args unknown)custom1_rd_rs1 (args unknown)custom1_rd_rs1_rs2 (args unknown)custom2 (args unknown)custom2_rs1 (args unknown)custom2_rs1_rs2 (args unknown)custom2_rd (args unknown)custom2_rd_rs1 (args unknown)custom2_rd_rs1_rs2 (args unknown)custom3 (args unknown)custom3_rs1 (args unknown)custom3_rs1_rs2 (args unknown)custom3_rd (args unknown)custom3_rd_rs1 (args unknown)custom3_rd_rs1_rs2 (args unknown)vector::_M_realloc_insertbasic_string::_S_construct null not valid*5._125*5._124*5._123*5._122*5._121*5._120*5._119*5._118*5._117*5._116*5._115*5._114*5._113*5._112*5._111*5._110*5._109*5._108*5._107*5._106*5._105*5._104*5._103*5._102*5._101*5._100*4._99*4._98*4._97*4._96*4._95*4._94*4._93*4._92*4._915arg_t trap #%uinterrupt #%u6trap_tŝtNSt6thread6_StateENSt3_V214error_categoryEsystemgenericbasic_string::_M_construct null not valid*N12_GLOBAL__N_121system_error_categoryE*N12_GLOBAL__N_122generic_error_categoryEbasic_string::at: __n (which is %zu) >= this->size() (which is %zu)basic_string::copybasic_string::comparebasic_string::_M_replacebasic_string::_M_replace_auxbasic_string::appendbasic_string::assignbasic_string::insertbasic_string::replacebasic_string::_M_createbasic_string::basic_stringstring::stringSt20bad_array_new_lengthstd::bad_array_new_length0123456789not enough space for format expansion (Please submit full bug report at https://gcc.gnu.org/bugs/): NSt8ios_base7failureB5cxx11Eiostreamiostream errorUnknown error*N12_GLOBAL__N_117io_error_categoryE;$y#OsSxsṢsSsS<tS>d>d?d@dIdDT8etc8ef8ePq9er~e0u~ex8e̙0ee eleTe fT f` f X f`8Rf @RfRfSfPfȘfLpf$hfxHfPf ff$%g\%g&gx'g`lghlgmgLngggdgXgpgX xg g g ?h @h, @h Ahh h h Hh @h h! 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Ȳ г"`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }} E t(tH(p,p,|,p,p,t,x(, H(Dld }|C  DH4lh \DD  HD4 E4L}}B  xLQ24 24 23342444|256528482x0,x00(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($(7<h                                              7<L h      8Pd  p!p(Xx! t(h! p!L==>>,?0?0@0@0@0A0A8܍B ԍB(̍B0čC0C0D0D0D0E<EFHH$H(II$I(JJKKLLLMMMMNNN܉O؉OԉOЉP̉PȉPRRSSSTTTUU؈UЈVȈVVVWWWXXXYYYZZ]0^__``Pa,bLЄb`Ȅct؄ddf0gh<ij܂lmnp܁qr ؁r ԁrЁśttȁtātuvvvvẁxy{|`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}4 t(tH(p,p,|,p,p,t,x(,((Dl DH4lh \DD  HD4 E4L}}X2  xL $4HL /1/1/00/111/344/51x0,x00((((( l l pE8     }%L$(4((pXt|D$(4($(XX$,$($($(7<h}t      H                                                  7<L h      8Pd !p p(Xx! t(h!D==j>>$j?(j?(j?0j@0j@0jA0gA8gB gB(gB0fC0fC0fC0fD0fD0fE8fEfEdHH dH(jIjI iI$iIiJhKKhKhKhLhLhLhMhMgMnNnNnNnNnOnOnOnPiRRiRmRmSnSnSnTnToToUoUoUoUoVoVoVoWoWnWnXnXnXnYnYmYl]]\l^Ll^(l_Hl_\l`lakbkc`# LH!@LH!@H8xl0/   /   4  `, L %P,%P,LTq^X            }}X$ t(tH(p,p,|,p,p,t,x(, H(Dl DH4lh \DD  HD4 E4L}}"  xL %'(('*++'x0,x00((((( p,(,(E8     }%L$(4((p|LD$(4($(XX$,$($($($    7<h                                                        7<L h      8Pd !p p(Xx! t(h!T==j>>$j?0j?(j?0j@0j@0jA0gA8gB gB(gB0fC0fC0fC0fD0fD0fE8fEfFdHH dH(jIjI iI$iJiJhKKhKhLhLhLhLhMhMgMnNnNnNnOnOnOnPnPiRRiRmSmSnSnSnTnToToUoUoUoVoVoVoWoWoWnWnXnXnXnYnYmYl]]\l^Ll^(l_Ll`\l`lbkbkc`# LH!@LH!@H8xl0/   /   4  `, L %P,%P,LT `iXX   H     }}4 t(tH(p,p,|,p,p,t,x(, H(DlYG   D          }}  YG   D          }}h  YG  D}} $$ `  DH4lh \DD i;=;#<$;%<&=';<<;<<=;=>>;@=@<A|; HD4 E4L}}  xLx0,x00(((((,(,(,,E8     }%L$(4((|LD$(4($(XX$,$($($(  7<h                                                        7<L h      8Pd  p!p(Xx!!p!L==z>>,܈?0؈?(Ј@(Ȉ@(@0A0A$A B(B0B0C0C0D0D0E,E؇EHH H H܅H ԅI$̅IąI܄JK؄KԄKЄL̄LȄLĄLMMMNNNOOOORRRR܃SԃS̃SăSTTTUUUVVVWWW܂WԂX̂XĂXYY\]0__a~b~c~e~f}h}i}kk}k}k}l}mm}m}m}n}oo}o}o|p|q|r{t{uTv{w{{`# LH!@LH!@H8xl0) ) )  `, L %P,%P,LTq^X            }} t(tH(p,p,|,p,p,t,x(,((DlXBBBBBBBAA A A A A A A A A A A A A A A B B B B B'B088@99?@@@@@@}  DH4lh \DD  HD4 E4L}}  xLP)0HpT|%Dd}{:@:<0:#<%:%@&:;;@:<<<:>?>:@<@@@:A@A:x0x0,0(((((,(,(,,E8     }%L=3}$(4((p|LD$(4($(XX$,$($($(hh7<h)p      ) PdA94L       H    -"Xl             X 1'`      }                                              7<L h      p8Pd  p!p(Xx!!p!L==z>>,܈?0؈?(Ј@(Ȉ@(@0A0A$A B(B0B0C0C0D0D0E,E؇EHH H H܅H ԅI$̅IąI܄JK؄KԄKЄL̄LȄLĄLMMMNNNOOOORRRR܃SԃS̃SăSTTTUUUVVVWWW܂WԂX̂XĂXYY\]0__a~b~c~e~f}h}i}kk}k}k}l}mm}m}m}n}oo}o}o|p|q|r{t{uTv{w{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }} t(tH(p,p,|,p,p,t,x(, H(Dl DH4lh \DD  HD4 E4L}}d  xLL1010100111333150541x0x0,0(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($( `7<h                                              7<L h      %<p})@t}%<p}%<p}%0p8Pd  p- L}- L}- L}- L}- L}%<p}%<p}%4%4P%4P%4!p(Xx!!p!L==z>?,?0?(؈@(Ј@(Ȉ@0A0A$B B(B0C0C0C0D0D0E,EEHH H HI ܅I$ԅI̅JKKK܄K؄LԄLЄL̄MȄMĄMMNNNOOOPRRRRS܃SԃS̃TăTTTUUUVVVWWWX܂XԂX̂YĂYY\]0_`a~b~c~e~f}h}i}kk}k}l}l}mm}m}n}n}oo}o}o}p|q|r{t{uTv{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,@,,,,,++++ + + + + + + * **))--------,*+,,,LT `iXX   H     }} t(tH(p,p,|,p,p,t,x(, H(DlM:TD}}D ,Ll      M:TD}} 8 \!\\#X  ! !!!"""""#"###$%$$%&%%%&} M:TD}} Tdd|\   \}}  <M:TD}} \/04  ,    M:TD}} -`<    t  eU T}T eW,t   X    } I9T h X       } M:TD}}L XTM:TD}}  ud   80TX}T  L}oT h P }  DH4lh \DD  HD4 E4L}}  xL,HpDX|(Q24 24 23342444|256528482x0x0,0(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($(*       PH7<heZpH                                                         7<L h      %L}h   %T}+        8Pd  p%<p}- L}- L}%<p}!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}L t(tH(p,p,|,p,p,t,x(,((Dld   }} L4 (((4''''')))()))'& & & % % % & # ########"#))#)#)#)#)#)#)#)#)#)#)#)#)#)#)#+#+#+#+#+#*#*#*#+#+#+#+#+#+#+" #"#&&&&&&&)*** DH4lh \DD  HD4 E4L}}l  xL$&'(&*++x&x0x0,0((((( l l pE8     }%L$(4(h(Xt|D$(4($(XX$,$($($(tH 7<h   D                                               7<L h      %L}6D p    D)8l}%<p}%<p})@t}4)    }/ %4H9. }(44-8P8@TD38t-Ld0&h  `8Pd  p%<p}%T}%<p}%X}%<p}T            !p(Xx!!!p\<={>>,?0܉?(ԉ@(̉@(ĉ@0A(A$A B(B0B0C0C0D0D0D,E܈EHH H HH ؆I$ІIȆIKK܅K؅KԅLЅL̅LȅLąMMMNNNOOOORRRRS؄SЄSȄTTTTUUUVVVWWWX؃XЃXȃXYY\0]̀_`acdf~gh~h~h~h~jj~j~j~k~ll~l~l~m}n}o}q}rTs|u|vw|x{{`   hD< `| !4 ,       # @ LH!@LH!@H8xl03       3       4      `, L %P,%P,LT `iXX   H     }}  tHtH(p,p,|,p,p,t, xH,<THDlYG   D          }}H  X   T  YG   D          }} @T`YG   D          }}< YG   D          }} YG   D          }} 4 hHDDYG   D          }} t P$t P$UD$$P$}` E5|P    } \ud    T T   } <$ `  DH4lh \DD  HD4 E4L}}  xL$&'(&*++x&x0x0,0((((( l l pE8     }%L$(4((LXt|D$(4($(XX$,$($($(        $` d d 7<h)l   4hD t$`                                              7<L h      %<p}%<p}%<p}%<p}%<p}%<p}%<p}H    G      0   (  D tDX  |\4z d l S          0    )pd    |   8Pd  p!p(Xx!!!p\<={>>,?0?(@(؉@(Љ@0ȉA(A$A B(B0B0C0C0D0D0D,EEHH H HH I$؆IІIKKK܅K؅LԅLЅL̅LȅMąMMNNNOOOORRRRS܄SԄS̄TĄTTTUUUVVVWWWX܃XԃX̃XăYY\0]Ѐ_`acdf~gh~h~h~h~jj~j~j~k~ll~l~l~m}n}o}q}rs|tTu|w{x{{`# LH!@LH!@H8xl0/   3       4  `, L %P,%P,LTq^X            }}`  tHtH(p,p,|,p,p,t, xH,<THDl DH4lh \DD  HD4 E4L}}  xLQ24 24 23342444|256528482x0x0,0(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($(*7<h                                                        7<L h      8Pd  p!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}` t(tH(p,p,|,p,p,t,x(, H(Dl DH4lh \DD  HD4 E4L}}~  xLDL1010100111333150541x0x0,0(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($(   P< \(    7<h=5     Pd        #     "x     L                                               7<L h      .44(\"    R       LT8Pd  p!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}pm t(tH(p,p,|,p,p,t,x(, H(Dl DH4lh \DD  HD4 E4L}}k  xL0 %'(('*++'x0x0,0((((( p,(,(E8     }%L$(4((p|LD$(4($(XX$,$($($( 7<hI?                                               7<L h      8Pd  p!8} (htt!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`#!,!x   } LH!@LH!@H8xl0/   /   4  `, L %P,%P,LT `iXX   H     }}\ t(tH(p,p,|,p,p,t,x(, H(DlYG   D          }}Z  x DH4lh \DD  HD4 E4L}}Y  xL#&''&***x&Xt,Xt,t, H H H H Hx0,x00E8     }%L`l,XtH(,$(4(4($(XX$,$($($( 7<h< 0                                              7<L h      %<p}-%Lx- L}E9l  }8Pd  p!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{$ @  P\ `# LH!@LH!@H8xl03       3       4      `, L %P,%P,LTUE}8J <H tHHp,p,|,p,p,t,<L,<THDl DH4lh \DD  HD4 E4L}}H  xLL1010100111333150541,x0x00((((( p,(,(E8     }%L$(4((p|LD$(4($(XX$,$($($().  7<h                                              7<L h      8Pd  p!p(Xx!!!p\<={>>,?0܉?(ԉ@(̉@(ĉ@0A(A$A B(B0B0C0C0D0D0D,E܈EHH H HH ؆I$ІIȆIKK܅K؅KԅLЅL̅LȅLąMMMNNNOOOORRRRS؄SЄSȄTTTTUUUVVVWWWX؃XЃXȃXYY\0]̀_`acdf~gh~h~h~h~jj~j~j~k~ll~l~l~m}n}o}q}rXs|u|vw|x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}9 t(tH(p,p,|,p,p,t,x(, H(Dl DH4lh \DD  HD4 E4L}}88  xLL1010100111333150541x0x0,0(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($( d7<h2`                                                    7<L h      8Pd  p!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}) t(tH(p,p,|,p,p,t,x(, H(DlYH      }X(  DH4lh \DD  HD4 E4L}}'  xLL /1/1/00/111/344/51x0,x00((((( p,(,(E8     }%L-%$T|$(4((p|LD$(4($(XX$,$($($(7<hE0                                                        7<L h      8Pd  p!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }} t(tH(p,p,|,p,p,t,x(, H(Dl DH4lh \DD  HD4 E4L}}4  xLQ24 24 23342444|256528482,x0x00(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($(7<h!x                                              7<L h      %L}%<p}8Pd  p%<p}Hx                       .L.\.\l!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EHH H H܆H ԆI$̆IĆI܅KK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄTTTTUUUVVVWWW܃XԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~jj~j~j~k~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LT `iXX   H     }} t(tH(p,p,|,p,p,t,x(, H(DlYG   D          }}d eV 0    } aR  }8  DH4lh \DD  HD4 E4L}}  xLL /1/1/00/111/344/51x0,x00((((( l l pE8     }%L$(4((pXt|D$(4($(XX$,$($($(  7<hT 9/(%4}H$`                                              7<L h      %L}*Ld8Pd  p)@t};    Ld!lT%<p}%L}P                          !p(Xx!!!p\<={>>,?0?(@(܉@(ԉ@0̉A(ĉA$A B(B0B0C0C0D0D0D,EEGH H HH I$܆IԆIJKKK܅L؅LԅLЅL̅MȅMąMNNNOOOORRRRSS؄SЄSȄTTTUUUVVVWWWWX؃XЃXȃYY\0]Ԁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q}rs|tTu|w{x{{/0YT   X h`# LH!@LH!@H8xl0/   /   4  `, L %P,%P,LTq^X            }} t(tH(p,p,|,p,p,t, xH, H(Dl DH4lh \DD  HD4 E4L}}  xL) XQ24 24 23342444|256528482x0x0,0(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($( -"$  7<h                                              7<L h      8Pd  p#     !p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }} t(tH(p,p,|,p,p,t,x(, H(Dl DH4lh \DD  HD4 E4L}}\  xL) X %'(('*++'x0x0,0((((( l l pE8     }%L$(4((pXt|D$(4($(XX$,$($($(   7<h                                              7<L h       ;X )  8Pd  p!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0/   /   4  `, L %P,%P,LTq^X            }}8 t(tH(p,p,|,p,p,t,x(, H(Dl DH4lh \DD  HD4 E4L}}  xLL1010100111333150541x0,x00(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($(7<h1)                                                  7<L h      %L} 8Pd  p.  %<p}Hp                     !p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}Ծ t(tH(p,p,|,p,p,t,x(, H(Dl}l 4   D}L ykX$ }м eU  }h  DH4lh \DD  HD4 E4L}}  xLL /1/1/00/111/344/51x0,x00((((( l l pE8     }%L$(4((pXt|D$(4($(XX$,$($($(M7<h(  $d                                               7<L h      d - L}8Pd  p`     t%<p}%Ht]U!p(Xx!!!p\<={>>,?0?(@(؉@(Љ@0ȉA(A$A B(B0B0C0C0D0D0D,EEHH H HH I$܆IԆIKKKKL܅L؅LԅLЅM̅MȅMąNNNOOOORRRRSS܄SԄT̄TĄTTUUUVVVWWWXX܃XԃX̃YY\0]؀_`acdfgh~h~h~h~jj~j~j~k~ll~l~l~m}n}o}q}rds|u|vw|x{{`# LH!@LH!@H8xl0/   /   4  `, L %P,%P,LT `iXX   H     }}@ t(tH(p,p,|,p,p,t,x(, H(DlA1       } YG   D          }} QB }L QC } -"L   DH4lh \DD i;=;#<$;%<&=';<<;<<=;=>>;@=@<A|; HD4 E4L}}  xLx0x0,0(((((,(,(,,E8     }%L$(4((|LD$(4($(XX$,$($($( ` 4t7<h                                               7<L h      %L}h`x8Pd  p<\3LH        D`dp5  p  4 4   D\`li( 8             D!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EHH H H܆H ԆI$̆IĆI܅KK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄTTTTUUUVVVWWW܃XԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~jj~j~j~k~ll~l~l~m}n}o}q}rXs|u|vw|x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}ė t(tH(p,p,|,p,p,t,x(,((Dl   }     DH4lh \DD  HD4 E4L}}H  xL %'(('*++'x0,x00((((( l l pE8     }%L$(4((pXt|D$(4($(XX$,$($($(  D7<h                                              7<L h      - L}%4/  @l     - L}!I>}aW   `8Pd  p%<p}!p(Xx!!!p\<={>>,܉?0؉?(Љ@(ȉ@(@0A(A$A B(B0B0C0C0D0D0D,E؈EGH H H܆H ԆI$̆IĆI܅JK؅KԅKЅL̅LȅLąLMMMNNNOOOORRRR܄SԄS̄SĄSTTTUUUVVVWWW܃WԃX̃XăXYY\0]Ȁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q|rXs|u|uw{x{{`|E8}$L|# LH!@LH!@H8xl0/   /   4  `, L %P,%P,LTq^X            }} t(tH(p,p,|,p,p,t, xH, H(Dl DH4lh \DD  HD4 E4L}}܂  xL"%&&%)))x%Xt,Xt,t, xd xd X d H H H H HE8     }%L`l,XtH( X$(4(4($(X X $,$($($(7<h                                              7<L h      %<p}9.L8Pd  p!p(Xx!L==_>>$h?(h?0h?0h@0h@0hA0hA4hB hB(hB0hC0hC0hC0gD0gD0gE8gEgEeHH eH$eHeI$eI$eIeJdKKdKdKdLdLdLdMdMdMdNdNdNdNdOdOdOdPcRRcRcRcScScScTcTcTcUcUcUcUcVcVbVbWbWbWbXbXbXbYbY`Y_\0]__E=|`# LH!@LH!@H8xl03       3       4      `, L %P,%P,LT `M?D}u <H<HHp,p, |Xp,p,t,<L X<THDlYG   D          }}|t  YG   D          }}t YG   D          }}s YG   D          }}Xs P  YG   D          }}r  YG   D          }}Xr QA }}r ub T T     }}q i\                   }yt                           }I@            ,I>\      d$ ` DH4lh \DD  HD4 E4L}}n  xLL1010100111333150541x0,x00(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($(7<h X                                                        7<L h      %<p}8Pd  p%<p}0\h    !p(Xx!!!p\<={>>,?0?(@(܉@(ԉ@0̉A(ĉA$A B(B0B0C0C0D0D0D,EEGH H HH I$܆IԆIJKKK܅L؅LԅLЅL̅MȅMąMNNNOOOORRRRSS؄SЄSȄTTTUUUVVVWWWWX؃XЃXȃYY\0]Ԁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q}rs|tTu|w{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LT `iXX   H     }}_ t(tH(p,p,|,p,p,t,x(, H(DlYG   D          }}H^ E3<T   }}^ I;    T      }] YG   D          }}X] QA  T      }] YG   D          }}\ ,tYG   D          }},\ t x 4}x[ aR  4 P         }[  DH4lh \DD  HD4 E4L}}`Z  xLQ24 24 23342444|256528482,x0x00(((((,(,(,,E8     }%L$(4((p|LD$(4($(XX$,$($($(7<h                                              7<L h      8Pd  p!p(Xx!!!p\<={>>,?0?(@(܉@(ԉ@0̉A(ĉA$A B(B0B0C0C0D0D0D,EEGH H HH I$܆IԆIJKKK܅L؅LԅLЅL̅MȅMąMNNNOOOORRRRSS؄SЄSȄTTTUUUVVVWWWWX؃XЃXȃYY\0]Ԁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q}rs|tTu|w{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LT `iXX   H     }}4L t(tH(p,p,|,p,p,t,x(, H(DlYG D}}J 3T      DH4lh \DD Q2424 23442445X2666x27472 HD4 E4L}}I  xL%Dd}x0x0,0(((((,(,(,,E8     }%L=3}$(4((p|LD$(4($(XX$,$($($(D@7<h) Pd(pX9.p                                                      7<L h      p8Pd  p!p(Xx!!!p\<={>>,?0?(@(܉@(ԉ@0̉A(ĉA$A B(B0B0C0C0D0D0D,EEGH H HH I$܆IԆIJKKK܅L؅LԅLЅL̅MȅMąMNNNOOOORRRRSS؄SЄSȄTTTUUUVVVWWWWX؃XЃXȃYY\0]Ԁ_`acdf~gh~h~h~h~ij~j~j~j~ll~l~l~m}n}o}q}rs|tTu|w{x{{`# LH!@LH!@H8xl0)   )   )  `, L %P,%P,LTq^X            }}p: t(tH(p,p,|,p,p,t,x(,((Dl DH4lh \DD i;=;#<$;%<&=';<<;<<=;=>>;@=@<A|; HD4 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J.~ 5#!1" ../../../libgcc/soft-fp../../../libgcc/../include.addtf3.csoft-fp.hquad.hlonglong.hsfp-machine.h C#{!!!-=-!-=/.< ..J.f<J.. .0 1 JLJLg#7 JJ.t <  .<.!<J.. -J..0.Y X..;!<<.!=I.%<=36.;.Ju <"! 8$J eA xJ<" ) fIJKBXJ.X-<t  ->/f><vJ JYe.Ig<.w   J.X!<f../7 @sB D.;K/wWy.|  f1CdXe.g.uuu!J.J.;!!/;<zJ<.w  .J.XJw.  </!. JEtO.\J^.^^!^^!^/f-t f XX;!<IK./e.hX X.;/NXN;N!F.<</,x. .w. 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P  xl A0P l E F`j l Elh` HǕl \l Fl \l d] @hוl ] i Ppl dl d pl b4j l Dol xo l edj x0h `@Öl zl z l o k h Pl l Ѕ l {k ( Kl l 4 8l \l X 8]l l $ l Xlp pl l ܓ l Hm `l l ̚ l HmH 0l Pl  @ l m` l l খ ( l ɘ nR  pl l ܯ l n8 H0l l ظ xl l X>l >l >l >l >l ?l ?l ?l ?l ?l 0@l LAl Bl Cl `Dl (El El DFl \Gl tHl Hl Hl 0Il PIl Il ,Jl Jl Kl ,Kl Kl Kl Ll Ll l hsl sl tl l ?l ?l ?l 0@l `@l @x k@l A [ k k k kl (Dl LDl pDl D" k= kR kl A ADԤ k k kO Al Dl D d k k k kl tG" k= kR kl ,E ,EDԤ k k kO pEw k k k l" (l= 0lR 8ll G GDԤ B h h l p" = R Ȉl t\ t\DԤ ̈ Ј ؈O \?L    " = R l ` `DԤ $ ( 0O P`?T 8 8 < @" h= pR xl lc lcDԤ |  O c@\    l j" = ȉR Љl df dfDԤ ԉ ؉ O f@f    " = R (l j jDԤ , 0 8O kXAp @ @ D H" p= xR l ,o ,oDԤ   O poAz    " Ȋ= ЊR ؊l s sDԤ ܊  O shB    " = (R 0l v vDԤ 4 8 @O wB H H L P" = R l lz lzDԤ   O zC   ċ ȋ" = R l \} \}DԤ $ ( 0O }D 8 8 < @" h= pR xl 4 4DԤ |  O xD    l " = ȌR Ќl , ,DԤ Ԍ ، O p(E    " = R (l  DԤ , 0 8O \E @ @ D H" p= xR l  DԤ   O 쌞PF    " ȍ= ЍR ؍l h hDԤ ܍  O F    " = (R 0l  DԤ 4 8 @O <PG H H L P" x= R l P PDԤ   O G    " Ў= ؎R l p pDԤ   O PH    " (= 0R 8l H HDԤ < @ HO H P P T X" = R l  DԤ   O ̧PI    " ؏= R l  DԤ   O I    " 0= 8R @l د دDԤ D H PO PJ X X \ `" x= R l 貞 貞DԤ   J     l pl l l жl 趞l l 8l p" = R l , ,DԤ   h  0 H(K ` ` d hl @l d" = R l  DԤ   O ̷hL    l tŞl Ş" = R l  DԤ   O ؾ@M&    l ̞" @= HR Pl ƞ ƞDԤ T X `O Pƞ N0 h h l p" = R l ̞ ̞DԤ   O @͞N<   Ē Ȓ" = R l О ОDԤ   O О`OH    " H= PR Xl tԞ tԞDԤ \ ` hO ԞOT p p t x" = R l מ מDԤ   O @؞pP` ȓ ȓ ̓ Г" = R l ޞ ޞDԤ   O ߞPm   $ (" P= XR `l  DԤ d h pO Qy x x | " = R l  DԤ   ȔO PR Д Д Ԕ ؔ" = R l \ \DԤ   O R ( ( , 0" X= `R hl  DԤ l p xO S    " = R l  DԤ ĕ ȕ ЕO 0S ؕ ؕ ܕ " = R l  DԤ   (O ((T 0 0 4 8" `= hR pl T  T DԤ t x O T    " = R Ȗl L LDԤ ̖ Ж ؖO @U    " = R l D DDԤ $ ( 0O U 8 8 < @" h= pR xl " "DԤ |  O "XV    " = ȗR Зl ) )DԤ ԗ ؗ O )V    " = R (l / /DԤ , 0 8O @0hW @ @ D H" p= xR l 6 6DԤ   O 7W    " Ș= ИR ؘl = =DԤ ܘ  O >xX    " = (R 0l D DDԤ 4 8 @O PDY& H H L P" x= R l TJ TJDԤ   O JY3    " Й= ؙR l P PDԤ   O PZ?    " (= 0R 8l V VDԤ < @ HO 0WZK P P T X" = R l ] ]DԤ   O ^ [X    " ؚ= R l d dDԤ   O d[d    " 0= 8R @l j jDԤ D H PO @k0\p X X \ `" = R l Dq DqDԤ   O q\}    " = R l w wDԤ   O w@]    " 8= @R Hl } }DԤ L P XO 8~] ` ` d h" = R l Ԅ ԄDԤ   O X^    " = R l < <DԤ   O ^    " @= HR Pl  DԤ T X `O 葟h_ h h l p" = R l  DԤ   O Ș_   ĝ ȝ" = R l 잟 잟DԤ   O 0`    " H= PR Xl  DԤ \ ` hO 襟a p p t x" = R l  DԤ   O Ȭa Ȟ Ȟ ̞ О" ؞= R l < <DԤ   O 8b    " = R l l lDԤ $ ( 0O b 8 8 < @" h= pR xl  DԤ |  O (c    " = ȟR Пl  DԤ ԟ ؟ O 躟c     " = R (l $ $DԤ , 0 8O hPd @ @ D H" = R l ş şDԤ   O Xşd    " = R l ɟ ɟDԤ   O ʟpe    " @= HR Pl Ο ΟDԤ T X `O Οf' h h l p" = R l ,ԟ ,ԟDԤ   O pԟf0   ġ ȡ" = R l ٟ ٟDԤ $ ( 0l ݟO `ٟ(g7 8 8 < @" h= pR xl ޟ ޟDԤ |  O ޟg@    " = ȢR Тl p pDԤ Ԣ آ O phI    " = R (l  DԤ , 0 8O 4i @ @ D H" = R l  DԤ   O $iR    l " = R l  DԤ   O (j]    " @= HR Pl  DԤ T X `O jh h h l p" = R l 4 4DԤ   O xks   Ĥ Ȥ" = R l T TDԤ   O (l}    l " H= PR Xl  DԤ \ ` hO l p p t x" = R l ! !DԤ   O d!pm ȥ ȥ ̥ Х" = R l , ,DԤ   O ,n   $ (" P= XR `l 8 8DԤ d h pO T8n x x | " = R l E EDԤ   ȦO TE o Ц Ц Ԧ ئ" = R l P PDԤ   O Po ( ( , 0l (_" X= `R hl W WDԤ l p xO XHp    " = R l _ _DԤ ħ ȧ ЧO _q ا ا ܧ " = R l f fDԤ   (O fq 0 0 4 8" `= hR pl hm hmDԤ t x O m@r    " = R Ȩl Ht HtDԤ ̨ Ш بO tr    " = R l { {DԤ $ ( 0O D{hs 8 8 < @" h= pR xl  DԤ |  O Ds    " = ȩR Щl h hDԤ ԩ ة O xt    " = R (l x xDԤ , 0 8O u @ @ D H" p= xR l  DԤ   O <u&    " Ȫ= ЪR تl @ @DԤ ܪ  O  v2    " = (R 0l  DԤ 4 8 @O v> H H L P" x= R l  DԤ   O 4`wJ    " Ы= ثR l ( (DԤ   O lwV    " (= 0R 8l  DԤ < @ HO ԰x P P T Xl x" = R l  DԤ   O 8yb Ȭ Ȭ ̬ Ь" = R l  DԤ   O ym   $ (l `Š" P= XR `l  DԤ d h pO xzx x x | " = R l Ơ ƠDԤ   ȭO DƠ0{ Э Э ԭ ح" = R l ʠ ʠDԤ   O ˠ{ ( ( , 0" X= `R hl Ϡ ϠDԤ l p xO ϠP|    " = R l Ԡ ԠDԤ Į Ȯ ЮO Ԡ| خ خ ܮ " = R l `٠ `٠DԤ   (O ٠p} 0 0 4 8" `= hR pl ޠ ޠDԤ t x O ޠ~    " = R ȯl p pDԤ ̯ Я دO ~    " 0= 8R @l  DԤ D H Pl hO 0 X X \ `" = R l  DԤ   O D    " = R l P PDԤ   O h    " 8= @R Hl  DԤ L P XO  ` ` d h" = R l  DԤ   O 4x    " = R l  DԤ   O     " @= HR Pl  DԤ T X `O  h h l p" = R Ȳl @ @DԤ ̲ в زO 0    l H" = R (l  DԤ , 0 8O < @ @ D H" x= R l  DԤ   O `    " = R l  DԤ ij ȳ гl O  س س ܳ " = R l ! !DԤ   O !    " `= hR pl # #DԤ t x O ,$(F    " = R ȴl & &DԤ ̴ д شl (O &X    " = R l + +DԤ $ ( 0O D+p 8 8 < @" = R l @- @-DԤ   O -&    " = R l (1 (1DԤ   O l13 ( ( , 0" 8= @R Hl 4 4DԤ L P XO 4 < ` ` d h" = R l 6 6DԤ   O d6.    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