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G9kS? R{G R ՠG*~@C R k`T 7w@4GG:G?@nl4GG/ G B
Ga + G { + {< O < cF E9[u? ` @ S~T < E9? G / 6 Gҷ@% 4U)< |S Qc Q~ `B|cl!l S !|~K @TS C A~ycC9RC9g ҡOC9E ҃ 3c9cAB 3[Ayy!pb 39@Ay R3@
3yAy ҿ ' !F ZF/ ; G T` B B @ Tvjtb B @A6~V@ ` _ T@9`` 9@G@ T` B B @ T s 6FFa@ ` TsB џAT GA 6 G R G> G G RG ͱ G ҢAIȱcA x qcAWz T G @ d?} R һ G@ A 5B9*[Ay@O@SP T F5Fa@ ` a TsB AT@t Nw@@ K F@ @ ʠ SA[BC@'@/@+@{֨_ ! "_C Q#5_ qT2 G ҢAIU) Q hS"<|ӡ| l S |~C A@5K 7 c7@ G@@ Tb "_C Q# ;@
_! 4 W ! "_C Q#5_ qTjض4 GM G G B
Gͳ ʶ4 G? G G B
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Gy ծ 4 G# Gq G B
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3yAy z ҿ ' !F ZF/ ; G T` B B @ Tvjtb B @A6~:@ ` _ T@9`` 9@G@ T` B B @ T s 6FFa@ ` TsB џAT GA 6 G R G" G G RG ұ G ҢAIcA x qcAWz T G @ d?} R ҟ G@A 5B9*[Ay@O@SP T F5Fa@ ` a TsB AT@t 2w@@ / F@ @ ʠ SA[BC@'@/@+@{֨_ ! "_C Q#5_ qT G ҢAItU) Q hS"<|ӡ| l S |~C A@5K 7 G7@ G@@ Tb "_C Q# ;@
_! 4 W ! "_C Q#5_ qTj4 G1 G G B
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G + GPV { + {< O < cF Р E9[u? ` @ S~T < E9? G Ё/ 6 G@% 4U)< |S Qc Q~ `B|cl!l S !|~K @TS C AycC9RC9g ҡOC9E ҃ 3c9cAB 3[Ayy!pb 39@Ay R3@
3yAy ̲ ҿ ; Т к' !F ZF/ ; G T` B B @ Tvjtb B @A6~@ ` _ T@9`` 9@G@ T` B B @ T С дs 6FFa@ ` TsB џAT GA 6 G RH Gt G G RG G ҢAIcA x qcAWz T G @ d?} R G@BA 5B9*[Ay@O@~SP T С F5Fa@ ` a TsB AT@t w@@ F@ @ ʠ SA[BC@'@/@+@{֨_ ! "_C Q#5_ qTh G ҢAIƬU) Q hS"<|ӡ| l S |~C A@5K 7 7@ G@@ Tb "_C Q# ;@
_! 4 W ! "_C Q#5_ qT4j4 G GѬ G B
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3yAy ҿ Т к' !F ZF/ ; G T` B B @ Tvjtb B @A6~p@ ` _ T@9`` 9@G@ T` B B @ T С дs 6FFa@ ` TsB џAT GA 6 G R, GX Gȭ G RG G ҢAIcA x qcAWz T G @ d?} R ժ G@&A 5B9*[Ay@O@bSP T С F5Fa@ ` a TsB AT@t hw@@ e F@ @ ʠ SA[BC@'@/@+@{֨_ ! "_C Q#5_ qTL G ҢAIU) Q hS"<|ӡ| l S |~C A@5K 7 }7@ G@@ Tb "_C Q# ;@
_! 4 W ! "_C Q#5_ qTj4 Gg G G B
G 4 GY G G B
G٬ ֯4 GK G G B
Gˬy ȯ 4 G= G G B
G պ4 G/ G} G B
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G9kS R? R{G ՠG**C Rs qk`T 7@4GXGG?@ګخ4GMG G B
Gͫ@ + G { + {< O < cF E9[u? ` @ S~T < E9? G / 6 G<@& 4U)< |S Q# Q `ӡ~B|cl !l SBTS!|~!"C ~ӠK AycC9RC9g ҡOC9E ҃ 3c9cAB 3[Ayy!pb 39@Ay R3@
3yAy ҿ n ' !F ZF/ ; G T` B B @ Tvjtb B @A6~@ ` _ T@9`` 9@G@ T` B B @ T s 6FFa@ ` TsB џAT GA 6 G Rz G G G RG 5 G ҢAI0cA x qcAWz T G @ d?} R # G@tA 5B9*[Ay@O@ȧSP T F5Fa@ ` a TsB AT@t w@@ F@ @ ʠ SA[BC@'@/@+@{֨_ ! "_C Q#5_ qT G ҢAI U) Q hSAl S
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G9kS R? R{G ՠG**C Rs k`T 71@4GGG?@(&4GG G B
G@ + GҦث { + {< O < cF E9[u? ` @ S~T < E9? G / 6 G@& 4U)< |S Q# Q `ӡ~B|cl !l SBTS!|~!"C ~ӠK A5ycC9&RC9g ҡOC9E ҃ 3c9cAB 3[Ayy!pb 39@Ay R3@
3yAy M ҿ ' !F ZF/ ; G T` B B @ Tvjtb B @A6~ @ ` _ T@9`` 9@G@ T` B B @ T s 6FFa@ ` TsB џAT GA 6 G Rȧ G Gd G RG ҃ G ҢAI~cA x qcAWz T G @ d?} R q G@§A 5B9*[Ay@O@BSP T F5Fa@ ` a TsB AT@t w@@ F@ @ ʠ SA[BC@'@/@+@{֨_ ! "_C Q#5_ qT G ҢAIF U) Q hSAl S
|Bl SB|~C !K 7 7@ G@@ Tb "_C Q# ;@
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G Հ4 G GC G B
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GY V4 Gˤ G G B
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Gc @G+@@ !ä+@ ' A R{ S [< bF RC @' q T G@ L B;Հ F 4` ?!GUh`6 @ **#@ : *ȀRc@.B`= R RH #@!F@` A T@ G 6G>@sF'@`@ SC[D{B_֢@4GGe G B
G Ձ !F B A_# QC5? qT@ A_# QC G =C#@ ` a= R{ S [< bF RC @' s q T G@ У B;Հ F 4` ?!GUh`6 @j **#@ : @ *ȀRc@.B`= R R̝ #@!F@` A T@ G 6G>@sF'@`@ SC[D{B_&@4GG G B
G Ձ !F B A_# QC5? qT2@ A_# QC e G ǣ#@ ` R{ S [ bF RC @' q T G@ T B;Հ F 4` ?!GUh`6 @ **#@ : *$ɀRc@.B`= R RP #@!F@` A T@ G 6G!sF'@`@ SC[D{B_֪@4G Gm G B
G Ձ !F B A_# QC5? qT@ A_# QC G EK#@ ` iE{C S G 6G R Rx q TSB{A@_ր G@ Ѣ B;Հ F 4` ?!GTh`5 @k ! :!@O *̀R R R Т c@.B`>Ԝ@SB{A_B 4GG ЁG B
G7 G R{ S [ bF RC @/ / q T з G@ B;Հ F 4` ?!GUh`6 @& *@y x " Ab ШC GB ٜ+@ : Т *ɀRc@.B`= R R Т+@!F@` T@ Ж@yG A 6C6 xFG+@KsF/@`@ SC[D{B_Ԣ4GIG ЁG B
Gɟ Ձ !F B A_# QC5? q,T@ A_# QC G ou+@ ` ѓo{ k @@ F q" @w Ҡ T q` T qA T RE R b@9 @aB@9`@( T ~g @y qf @94 } Ҕ |<@yd@y pG yf @9 } @#P9" c| B| c B K Rct SBTSS )$ RfsF7@`@ SE[FcG{DC@_ Հ G@ Н B;Հ F 4` ?!GZh`; @j ! :# b ! B` * # + R3 R; c@.B R˗D{S [ `F c X @7 C Ry 3 q T**֚ | @#P9" c| B| c B K Rcx SBXSS ) RsF7@`@ SE[FcG{DC@_ Հ G@ h B;Հ F 4` ?!GZh`; @ ! :# b !@
B * # + R3 R; c@.B RcD3{S [ `F c X @7 C Ry ˗ q T**n | @#P9" c| B| c % RB K cx SBTSS )*sF7@`@ ` SE[FcG{DC@_ Հ G@ B;Հ F 4` ?!GZh`; @ ! :$
c ! c b # B`+ *3 ; R Rc@.B RDɖ{( RD Rf R I@yK @y A9@ygB@9Ay#1 3 3G @y y 39 0 3@y @ I@yH(@93G,@9a13 y#|S cls@F!hyK@w ҡs !\Pө y90Hӧ9 3Ayh ң9' ҡ99E ҡ@y Ay!h y!|S!J@yI@y3B @y9D1 3Ay#1 3f@y0HA0 3 yyc0H!0HӤ99 9O G
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@a@NSJ T ־FFa@ ` A TsB ATS@t ٘G@@ ֘Fw@@ ʠ CD@@ @@@{Ϩ_ W ! "_C Q#5_ q T"_C Q# 4G GW G B
G Z ! "_C Q#5_ qlT"_C Q# ؕ k + G@@ 6 G+qG@ A g@ ` B_@ ` ? C{S ? `Fs ;< C9[ c
k < s Z< @o y< < AyAy RB q T#c9; yyy y#yK9O9+y/y6@ RAy+AyAyKB9! OB9/Ayc R Rc ! ?@;@!|) sFo@`@ SH[IcJkKsL{GC_ Հ G@ i B;Հ F 4` ?!GEh`& @ F Фs@! :#`c !b B# * R+ 3 ; ˀRC c@.K BS R[ ]/C{S ? `Fs ;< C9[ c
k < s Z< @o y< < AyAy R q T#c9; yyy y#yK9O9+y/y@ RZAy+AyAyKB9! OB9/Ayc R Rc ! ?@;@!|) !sFo@`@ SH[IcJkKsL{GC_ Հ G@ B;Հ F 4` ?!GEh`& @ F s@! :# c !B B# * R+ 3 ; ˀRC c@.K BS R[ ۔C{S ? `Fs ;< C9[ c
k < s Z< @o y< < AyAy R> q T#c9; yyy y#yK9O9+y/y2@ RAy+AyAyKB9! OB9/Ayc Rc ! ?@;@!|)) sFo@`@ SH[IcJkKsL{GC_ Հ G@ g B;Հ F 4` ?!GEh`& @ F s@! :#c !@B B# * R+ 3 ; ˀRC c@.K BS R[ [-C{S ? `Fs ;< C9[ c
k < s Z< @o y< < AyAy R q T#c9; yyy y#yK9O9+y/y@ RXAy+AyAyKB9! OB9/Ayc Rc ! ?@;@!|)) !sFo@`@ SH[IcJkKsL{GC_ Հ G@ B;Հ F 4` ?!GEh`& @ F s@! :#c ! B B # * R+ 3 ; ˀRC c@.K BS R[ ۓ{S k
`FY< [ c < [ x < < @G RB q@ T y9C R yb R yy 9 sFG@`@ SG[HcIkJ{F[@_ր / G@ B;Հ F 4` ?!G\h`& @7 3 7@ ! :C $`c ! B` ; * RC K S dR[ c@.B@ R{/@/ K{S k
`FY< [ c < [ x < < @G R q@ T y9C R y R yy 9sFG@`@ SG[HcIkJ{F[@_ր / G@ $ B;Հ F 4` ?!G\h`& @7 3 7@ ! :C $`c ! B` ; * RC K S R[ c@.B@ R/@/ {S k
`FY< [ c < [ x < < @G R~ q@ T y9C R yb R yy 9sFG@`@ SG[HcIkJ{F[@_ր / G@ B;Հ F 4` ?!G\h`& @7 [3 7@ ! :C $`c! B` ; * RC K S dR[ c@.B@ R/@/ {S k
`FY< [ c < [ x < < @G R q@ T y9C R y R yy 9sFG@`@ SG[HcIkJ{F[@_ր / G@ ` B;Հ F 4` ?!G\h`& @7 3 7@ ! :C $`c! B` ; * RC K S R[ c@.B@ RU/@/ %{S k
`FY< [ c < [ x < < @G R q@ T y9C R yb R yy 9TsFG@`@ SG[HcIkJ{F[@_ր / G@ B;Հ F 4` ?!G\h`& @7 3 7@ ! :C $`c! B` ; * RC K S dR[ c@.B@ R/@/ Ñ{S k
`FY< [ c < [ x < < @G RX q@ T y9C R y R yy 9sFG@`@ SG[HcIkJ{F[@_ր / G@ B;Հ F 4` ?!G\h`& @7 53 7@ ! :C $`c! B` ; * RC K S R[ c@.B@ R/@/ a{S k
`FY< [ c < [ x < < @G R q@ T y9C R yb R yy 9tsFG@`@ SG[HcIkJ{F[@_ր / G@ : B;Հ F 4` ?!G\h`& @7 ӓ3 7@ ! :C $`c! B` ; * RC K S dR[ c@.B@ R//@/ {S k
`FY< [ c < [ x < < @G R q@ T y9C R y R yy 9sFG@`@ SG[HcIkJ{F[@_` / G@ ؖa B;` F 4` ?!G\h`& @7 q3 7@ ! :C $`c! B` ; * RC K S R[ c@.B@ R͐/@/ {Ss k
`FY< [ c < [ x < < @G R2 q@ T y9C R yb R yy 9sFG@`@ SG[HcIkJ{F[@_` / G@ va B;` F 4` ?!G\h`& @7 3 7@ ! :C $`c`! B` ; * RC K S dR[ c@.B@ Rk/@/ ;{Ss k
`FY< [ c < [ x < < @G RА q@ T y9C R y R yy 9sFG@`@ SG[HcIkJ{F[@_` / G@ a B;` F 4` ?!G\h`& @7 3 7@ ! :C $`c`! B` ; * RC K S R[ c@.B@ R /@/ ُ{Ss k
`FY< [ c < [ x < < @G Rn q@ T y9C R yb R yy 9 sFG@`@ SG[HcIkJ{F[@_` / G@ a B;` F 4` ?!G\h`& @7 K3 7@ ! :C $`c ! B` ; * RC K S dR[ c@.B@ R/@/ w{Ss k
`FY< [ c < [ x < < @G R q@ T y9C R y R yy 9sFG@`@ SG[HcIkJ{F[@_` / G@ Pa B;` F 4` ?!G\h`& @7 3 7@ ! :C $` c ! B` ; * RC K S R[ c@.B@ RE/@/ {Ss k
`FY< [ c < [ x < < @G R q@ T y9C R yb R yy 9$sFG@`@ SG[HcIkJ{F[@_` / G@ a B;` F 4` ?!G\h`& @7 3 7@ ! :C $` c! B` ; * RC K S dR[ c@.B@ R/@/ {Ss k
`FY< [ c < [ x < < @G RH q@ T y9C R y R yy 9sFG@`@ SG[HcIkJ{F[@_` / G@ a B;` F 4` ?!G\h`& @7 %3 7@ ! :C $` c! B` ; * RC K S R[ c@.B@ R/@/ Q{C s s `F[ < c
@G k < Z< y R q TCB9 9 y9C R yb R9 y9fsFG@`@ @ [IcJkKsL{GC@_` G@ (a B;` F 4` ?!GTh`& @7 3 @ 7@! :$` G ! c C Т c B` ; *C K S DR[ c@.B R R@ {C s s `F[ < c
@G k < Z< y R~ q TCB9 9 y9C R y R9 y9sFG@`@ @ [IcJkKsL{GC@_` G@ a B;` F 4` ?!GTh`& @7 Y3 @ 7@! :$ G ! c C Т c B` ; *C K S dR[ c@.B R R@ {Ss k
`FY< [*c < [ x < @G R q T y9 R yb R9 y99sFG@`@ SG[HcIkJ{F[@_ ` / G@ Xa B;` F 4` ?!G\h`& @7 3 7@ ! : $` [ ! C c ; B` C * K RS Rc@.B RL/@/ {Ss k
`FY< [*c < [ x < @G R q T y9 R y R9 y991sFG@`@ SG[HcIkJ{F[@_ ` м/ G@ a B;` F 4` ?!G\h`& @7 3 7@a ! : $ [ ! !C c ; B` C * K RS Ђ ĉRc@.B R/@/ {Ss k
`FY< [*c < [ x < @G RJ q T y9 R yB R9 y99ˍsFG@`@ SG[HcIkJ{F[@_ ` м/ G@ a B;` F 4` ?!G\h`& @7 %3 7@a ! : $`![ !!C c ; B` C * K RS Ђ 䉀Rc@.B R/@/ P {C s s `F[ < c
@G k < Z< y R q TCB9 9 y9C R yb R9 y9sFG@`@ @ [IcJkKsL{GC@_` д G@ &a B;` F 4` ?!GTh`& @7 3 @a 7@! :$!G ! "c C cB` ; *C K S DR[ c@.B R R@ {C s s `F[ < c
@G k < Z< y R| q TCB9 9 y9C R y R9 y9sFG@`@ @ [IcJkKsL{GC@_` д G@ a B;` F 4` ?!GTh`& @7 W3 @a 7@! :$`"G !"c C cB` ; *C K S dR[ c@.B R R@ {Ss k
`FY< [*c < [ x < @G R q T y9 R yb R9 y99IsFG@`@ SG[HcIkJ{F[@_ ` м/ G@ Va B;` F 4` ?!G\h`& @7 3 7@a ! : $"[ ! #C c ; B` C * K RS Ђ 𤉀Rc@.B RJ/@/ {Ss k
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@/ |v { {_ GetVcopyExtent copy_gm_to_cbuf_multi_nd2nz_b16 copy_gm_to_cbuf_multi_nd2nz_b16 copy_gm_to_cbuf_multi_nd2nz_b16 copy_gm_to_cbuf_multi_nd2nz_b16 copy_gm_to_cbuf_multi_nd2nz_b16 copy_gm_to_cbuf_multi_nd2nz_b16 copy_gm_to_cbuf_multi_nd2nz_b16 copy_gm_to_cbuf_multi_nd2nz_b16 copy_gm_to_cbuf_multi_nd2nz_b32s copy_gm_to_cbuf_multi_nd2nz_b32s copy_gm_to_cbuf_multi_nd2nz_b32s copy_gm_to_cbuf_multi_nd2nz_b32s copy_gm_to_cbuf_multi_nd2nz_b32s copy_gm_to_cbuf_multi_nd2nz_b32s copy_gm_to_cbuf_multi_nd2nz_b8 copy_gm_to_cbuf_multi_nd2nz_b8 copy_gm_to_cbuf_multi_nd2nz_b8 copy_gm_to_cbuf_multi_nd2nz_b8 copy_cbuf_to_fbuf copy_cbuf_to_fbuf r afczo vcopy vcopy vcopy vcopy vcopy vcopy vcopy vcopy copy_cbuf_to_ubuf copy_cbuf_to_ubuf copy_gm_to_cbuf copy_gm_to_cbuf copy_gm_to_ubuf copy_gm_to_ubuf copy_ubuf_to_cbuf copy_ubuf_to_cbuf copy_ubuf_to_gm copy_ubuf_to_gm copy_ubuf_to_ubuf copy_ubuf_to_ubuf copy_cbuf_to_gm copy_cbuf_to_gm copy_cbuf_to_bt copy_cbuf_to_bt copy_depthwise_cc_to_ubuf copy_depthwise_cc_to_ubuf copy_depthwise_cc_to_ubuf copy_depthwise_cc_to_ubuf copy_depthwise_cc_to_ubuf copy_depthwise_cc_to_ubuf copy_depthwise_cc_to_ubuf copy_depthwise_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_cc_to_ubuf copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_matrix_ubuf_to_cc copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_cc_to_ubuf copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_vector_ubuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc copy_matrix_cbuf_to_cc MASK0 MASK1 L0C16 OUT L0C32 L1 BT FB L0CV16 L0CV32 L0CSC32 L0CDPf16 L0CDPf32 vexp vrsqrt vrelu vrec vln vabs vnot vsqrt s32 f16 fmix f32 b16 bf16 b32 s8 vadds vmuls vmaxs vmins vshr vshl vlrelu vadd vsub vmul vdiv vmax vmin vand vor vaddrelu vmadd vsubrelu vaddreluconv vsubreluconv s162s8 f162s8 f322f16 vdeqs162b8 s64 s16 u8 s4 deq deqs162b8h deqs162b8l vdeqs162b8h vdeqs162b8l s42f16 none basic_string::append basic_string::insert %s: __pos (which is %zu) > this->size() (which is %zu) basic_string::_S_construct null not valid basic_string::_S_create kernel_operator_data_copy_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: maskLow_=%lu, maskHigh_=%lu, blkNumLastRep=%hu, eleNumLastBlk=%hu, maxOffset=%lu
DEQSCALE LRELU_ALPHA MOV_PAD_VAL [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cbuf__ %s*)dst, (__gm__ %s*)src, sid=%hhu, ndNum=%hu, nValue=%hu, dValue=%hu, srcNdMatrixStride=%hu, srcDValue=%hu, dstNzC0Stride=%hu, dstNzNStride=%hu, dstNzMatrixStride=%hu);
half int16_t uint16_t bfloat16_t float int32_t uint32_t int8_t uint8_t map::at %u L1FB [%s:%d] block_idx: %d, core_type: %s %d %s: (__fbuf__ %s*)dst, (__cbuf__ %s*)src, nBurst=%hu, lenBurst=%hu, sourceGap=%hu, dstGap=%hu);
void [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, repeat=%hhu, dstStride=%hu, srcStride=%hu, dstRepeatSize=%hu, srcRepeatSize=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__cbuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cbuf__ %s*)dst, (__gm__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu, padMode=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__gm__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cbuf__ %s*)dst, (__ubuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ %s*)dst, (__ubuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ %s*)dst, (__cbuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s(%s)dst, (__cbuf__ %s*)src, convControl=%hu, nBurst=%hu, lenBurst=%hu, sourceGap=%hu, dstGap=%hu);
uint64_t [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__cc__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu, crMode=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)dst, (__ubuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu, crMode=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)dst, (__ubuf__ %s*)src, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu);
V SC DP L0A L0B L0C L0C16UB L0C32UB UBL0C16 UBL0C32 L1L0C16 L1L0C32 L0CV16UB L0CV32UB UBL0CV16 UBL0CV32 L0CSC32UB UBL0CSC32 L0CDPf16UB L0CDPf32UB L1BT r afczo set_atomic_none set_atomic_none set_atomic_f32 set_atomic_f32 set_atomic_f16 set_atomic_f16 set_atomic_s16 set_atomic_s16 set_atomic_bf16 set_atomic_bf16 set_atomic_s8 set_atomic_s8 set_atomic_s32 set_atomic_s32 basic_string::basic_string basic_string::substr kernel_operator_set_atomic_add_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s();
set_atomic_none set_atomic_f32 set_atomic_f16 set_atomic_s16 set_atomic_bf16 set_atomic_s8 set_atomic_s32 G 3_p0 TensorWriteFile set_fmatrix set_deqscale set_deqscale set_lrelu_alpha set_lrelu_alpha set_fmatrix_b set_quant_pre set_fpc set_nd_para set_vector_mask set_mask_count set_mask_norm get_cond get_condition_flag get_ctrl set_ctrl get_vms4_sr get_rsvd_cnt get_ar get_acc_val get_st_atomic_cfg get_max_min_cnt get_cmpmask set_cmpmask set_l1_3d_size dsb trap pipe_barrier set_core_type get_arch_ver get_pc dc_preload dc_preload preload preload preload preload set_data_exp_0 set_data_exp_1 set_data_exp_2 set_data_exp_3 std::string AscendC::FormatEvent(int32_t) wait_flag set_flag hwait_flag hset_flag set_flag wait_flag G set_cond set_condition_flag set_st_atomic_cfg wait_flag_dev ffts_cross_core_sync %d %f %ld %lu kernel_utils.cpp [%s:%d] block_idx: %d, core_type: %s %d %s:%serror: file name is empty
[%s:%d] block_idx: %d, core_type: %s %d %s: warn: realpath return nullptr
[%s:%d] block_idx: %d, core_type: %s %d %s: WriteFile(): file name = '%s', size = %d
[%s:%d] block_idx: %d, core_type: %s %d %s:%serror: buffer is nullptr
[%s:%d] block_idx: %d, core_type: %s %d %s:%serror: can't open file: %s
[%s:%d] block_idx: %d, core_type: %s %d %s:%serror: write size %d
[%s:%d] block_idx: %d, core_type: %s %d %s: set_fmatrix(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_deqscale((half)%f);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_deqscale(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_lrelu_alpha(%f);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_fmatrix_b(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_quant_pre(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_fpc(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_nd_para(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_vector_mask(%lu, %lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_mask_count();
[%s:%d] block_idx: %d, core_type: %s %d %s: set_mask_norm();
COND [%s:%d] block_idx: %d, core_type: %s %d %s: set_cond();
CONDITION_FLAG [%s:%d] block_idx: %d, core_type: %s %d %s: get_condition_flag();
[%s:%d] block_idx: %d, core_type: %s %d %s: get_ctrl();
[%s:%d] block_idx: %d, core_type: %s %d %s: set_ctrl(%lu);
VMS4_SR [%s:%d] block_idx: %d, core_type: %s %d %s: get_vms4_sr();
RSVD_CNT [%s:%d] block_idx: %d, core_type: %s %d %s: get_rsvd_cnt();
AR [%s:%d] block_idx: %d, core_type: %s %d %s: get_ar();
ACC_VAL [%s:%d] block_idx: %d, core_type: %s %d %s: get_acc_val();
ST_ATOMIC_CFG [%s:%d] block_idx: %d, core_type: %s %d %s: get_st_atomic_cfg();
MAX_MIN_CNT [%s:%d] block_idx: %d, core_type: %s %d %s: get_max_min_cnt();
[%s:%d] block_idx: %d, core_type: %s %d %s: get_cmpmask((__ubuf__ void* )dst=%p); [maskLow=%lu, maskHigh=%lu]
[%s:%d] block_idx: %d, core_type: %s %d %s: set_cmpmask((__ubuf__ void* )src=%p); [maskLow=%lu, maskHigh=%lu]
[%s:%d] block_idx: %d, core_type: %s %d %s: set_l1_3d_size(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: dsb(%u);
[%s:%d] block_idx: %d, core_type: %s %d %s: trap(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_V);
[%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_ALL);
[%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_S);
[%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_M);
[%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_MTE1);
[%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_MTE2);
[%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_MTE3);
[%s:%d] block_idx: %d, core_type: %s %d %s:%serror: g_taskRation %d
ARCH_VER [%s:%d] block_idx: %d, core_type: %s %d %s: get_arch_ver();
PC [%s:%d] block_idx: %d, core_type: %s %d %s: get_pc();
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ uint64_t*)address, offset=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ void*)addr, prefetchLen=%I64d);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ void*)addr);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_data_exp_0(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_data_exp_1(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_data_exp_2(%lu);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_data_exp_3(%lu);
PIPE_V PIPE_M PIPE_MTE1 PIPE_MTE2 PIPE_MTE3 PIPE_S PIPE_FIX [%s:%d] block_idx: %d, core_type: %s %d %s: wait_flag(%s, %s, %d);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_flag(%s, %s, %d);
[%s:%d] block_idx: %d, core_type: %s %d %s: hwait_flag(%s, %s, %d, %d, %d);
[%s:%d] block_idx: %d, core_type: %s %d %s: hset_flag(%s, %s, %d, %d, %d);
STATUS [%s:%d] block_idx: %d, core_type: %s %d %s: set_condition_flag();
[%s:%d] block_idx: %d, core_type: %s %d %s: set_st_atomic_cfg();
AIC_ AIV_ MIX_ Block_ [ERROR][%s][%s][%s:%d][%s][%u] error:ffts flagID %ld exceeds number of ffts flags %d!
[ERROR][%s][%s][%s:%d][%s][%u] error:ffts INTER_SUBBLOCK_MODE can only run with MIX_MODE!
[ERROR][%s][%s][%s:%d][%s][%u] error:ffts INTER_SUBBLOCK_MODE can't run on AIC
[ERROR][%s][%s][%s:%d][%s][%u] error:ffts INTRA_GROUP_MODE can only run with MIX_MODE!
uint64_t AscendC::check::CalculateVectorMaxOffset(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t) bool AscendC::check::TikcppBaseCheck::CheckTensorOverflowLow(std::vector&, uint64_t, uint32_t, std::vector&, const string&) const bool AscendC::check::CheckOverlapSingleMany(std::vector&, std::vector&, std::vector&, const string&) [ERROR]%s: mask value is not in range [%lu, %lu]
tikcpp_base_check.cpp [%s:%d]%s: mask value is not in range [%lu, %lu]
[ERROR]%s: dst/src bit length is 32, mask_h must be 0
[%s:%d]%s: dst/src bit length is 32, mask_h must be 0
[ERROR]%s: dst/src bit length is 64, mask_h must be 0
[%s:%d]%s: dst/src bit length is 64, mask_h must be 0
vector::_M_realloc_insert [ERROR]%s
[%s:%d]%s
[ERROR]%s, addr0: %lu, addr1: %lu, needSize: %lu
[%s:%d]%s, addr0: %lu, addr1: %lu, needSize: %lu
[ERROR]%s, src hardware address: %lu, dst hardware address: %lu
[%s:%d]%s, src hardware address: %lu, dst hardware address: %lu
[ERROR]%s, src hardware address: %lu, dst hardware address: %lu, needSize: %lu
[%s:%d]%s, src hardware address: %lu, dst hardware address: %lu, needSize: %lu
[ERROR]%s, Need size: %lu, while tensor size is %lu
[%s:%d]%s, Need size: %lu, while tensor size is %lu
[ERROR]%s, Allocated buffer size overflow, allocate buffer size is %lu, the limit size is %lu.
[%s:%d]%s, Allocated buffer size overflow, allocate buffer size is %lu, the limit size is %lu.
blockLen != 0 dtypeBytes != 0 dtypeBytes[0] != 0 dtypeBytes[1] != 0 GM BIAS FIXBUF [ERROR]the tensorPos/expectPos hardware pos not found,tensorPos index is %hhu, expectedPos is %hhu.
[%s:%d]the tensorPos/expectPos hardware pos not found,tensorPos index is %hhu, expectedPos is %hhu.
[ERROR]%s, the tensor hardware pos is %s, the expect pos is %s.
[%s:%d]%s, the tensor hardware pos is %s, the expect pos is %s.
N7AscendC5check15TikcppBaseCheckE [ERROR]intriName is null. tikcpp_check_util.cpp [%s:%d]intriName is null.
N7AscendC5check15TikcppCopyCheckE [ERROR]maskArray size is zero. tikcpp_copy_check.cpp [%s:%d]maskArray size is zero.
check dst tensor position failed check src tensor position failed check dst tensor buffersize failed check src tensor buffersize failed dst and src address overlapping dst calculate size overflow src calculate size overflow N7AscendC5check19TikcppDataCopyCheckE
GetHardwareBaseAddr tikcpp_data_copy_check.cpp [ERROR][%s][%s][%s:%d][%s][%u] illegal hardPos %d
[ERROR]instr %s src addr is %lu, which should be %u B Aligned
[%s:%d]instr %s src addr is %lu, which should be %u B Aligned
[ERROR]instr %s dst addr is %lu, which should be %u B Aligned
[%s:%d]instr %s dst addr is %lu, which should be %u B Aligned
N7AscendC5check22TikcppDataCopyPadCheckE [ERROR]%s, size of leftPadding or rightpadding should be less than 32 Bytes
tikcpp_data_copy_pad_check.cpp [%s:%d]%s, size of leftPadding or rightpadding should be less than 32 Bytes
check dataCopyPad paramters N7AscendC5check24TikcppDataCopySliceCheckE
GetHardwareBaseAddr [ERROR]%s, dstSliceInfo[%u]'s busrt len (%u) should be equal to SliceInfo[%u]'s busrt len (%u)
tikcpp_data_copy_slice_check.cpp [%s:%d]%s, dstSliceInfo[%u]'s busrt len (%u) should be equal to SliceInfo[%u]'s busrt len (%u)
[ERROR]%s, dim[%u]'s dstSliceInfo's busrt len should be equal to 1, but get (%u)
[%s:%d]%s, dim[%u]'s dstSliceInfo's busrt len should be equal to 1, but get (%u)
[ERROR]%s, dstSliceInfo[%u]'s start index (%u) should be lee than dstSliceInfo[%u]'s end index (%u)
[%s:%d]%s, dstSliceInfo[%u]'s start index (%u) should be lee than dstSliceInfo[%u]'s end index (%u)
[ERROR]%s, dstSliceInfo[%u]'s end index (%u) should be less than dstSliceInfo[%u]'s shape (%u)
[%s:%d]%s, dstSliceInfo[%u]'s end index (%u) should be less than dstSliceInfo[%u]'s shape (%u)
[ERROR]%s, srcSliceInfo[%u]'s start index (%u) should be lee than srcSliceInfo[%u]'s end index (%u)
[%s:%d]%s, srcSliceInfo[%u]'s start index (%u) should be lee than srcSliceInfo[%u]'s end index (%u)
[ERROR]%s, srcSliceInfo[%u]'s end index (%u) should be less than dst tensor dim[%u]'s shape (%u)
[%s:%d]%s, srcSliceInfo[%u]'s end index (%u) should be less than dst tensor dim[%u]'s shape (%u)
[ERROR]%s, construct datacopy intrs paramters block count failed, please check srcSliceInfo[0].burstLen(%u), srcSliceInfo[0].startIndex(%u), srcSliceInfo[0].endIndex(%u), srcSliceInfo[0].stride(%u)
[%s:%d]%s, construct datacopy intrs paramters block count failed, please check srcSliceInfo[0].burstLen(%u), srcSliceInfo[0].startIndex(%u), srcSliceInfo[0].endIndex(%u), srcSliceInfo[0].stride(%u)
[ERROR]%s, one dst stride len (%lu) should be multiple of block size (%lu), dstSliceInfo[0].stride(%u), dstDtypeBytes(%u)
[%s:%d]%s, one dst stride len (%lu) should be multiple of block size (%lu), dstSliceInfo[0].stride(%u), dstDtypeBytes(%u)
[ERROR]%s, one src stride len (%lu) should be multiple of block size (%lu), srcSliceInfo[0].stride(%u), srcDtypeBytes(%u)
[%s:%d]%s, one src stride len (%lu) should be multiple of block size (%lu), srcSliceInfo[0].stride(%u), srcDtypeBytes(%u)
[ERROR]%s, srcIntrsNum(%u) != dstIntrsNum(%u)
[%s:%d]%s, srcIntrsNum(%u) != dstIntrsNum(%u)
[ERROR]%s, srcIntrsNum(%u) is bigger than MAX_SLICE_SIZE(%u), please reset the sliceInfo parameter
[%s:%d]%s, srcIntrsNum(%u) is bigger than MAX_SLICE_SIZE(%u), please reset the sliceInfo parameter
check dst tensor position failed, it should be UB check total number of instructions mov or mov_align failed check src tensor position failed, it should be UB check ub tensor buffersize failed check sliceInfo paramters check data copy instr paramters N7AscendC5check21TikcppLoaddata2dCheckE N7AscendC5check23TikcppLoaddata3dv1CheckE N7AscendC5check23TikcppLoaddata3dv2CheckE N7AscendC5check26TikcppLoaddata3dv2ProCheckE N7AscendC5check24TikcppLoadImageToL1CheckE [ERROR]unsupport Loaddata3dv1 tikcpp_loaddata_check.cpp [%s:%d]unsupport Loaddata3dv1
[ERROR]check dst tensor position failed,the dst hardware pos support L1. [%s:%d]check dst tensor position failed,the dst hardware pos support L1.
[ERROR]dst dtype bytes is zeros [%s:%d]dst dtype bytes is zeros
[ERROR]check dst tensor position failed,the src hardware pos is L1, the dst hardware pos support L0A or L0B. [%s:%d]check dst tensor position failed,the src hardware pos is L1, the dst hardware pos support L0A or L0B.
[ERROR]check src tensor position failed,the src hardware pos support L1. [%s:%d]check src tensor position failed,the src hardware pos support L1.
[ERROR]check dst tensor position failed,the src hardware pos is GM, the dst hardware pos support L1 or L0A or L0B. [%s:%d]check dst tensor position failed,the src hardware pos is GM, the dst hardware pos support L1 or L0A or L0B.
[ERROR]src/dst dtype bytes is zeros [%s:%d]src/dst dtype bytes is zeros
[ERROR]check src tensor position failed,the src hardware pos support L1 or GM. [%s:%d]check src tensor position failed,the src hardware pos support L1 or GM.
N7AscendC5check15TikcppMmadCheckE [ERROR]%s: value(%u) is not in range [%u, %u]
tikcpp_mmad_check.cpp [%s:%d]%s: value(%u) is not in range [%u, %u]
[ERROR]%s: needElementL0c(%u) is bigger than totalL0CSize(%u)
[%s:%d]%s: needElementL0c(%u) is bigger than totalL0CSize(%u)
[ERROR]%s: needElementL0b(%u) + needElementL0a(%u) is bigger than totalL1Size(%u)
[%s:%d]%s: needElementL0b(%u) + needElementL0a(%u) is bigger than totalL1Size(%u)
check src0 tensor position failed check src1 tensor position failed check MmadParams'm range failed check MmadParams'n range failed check MmadParams'k range failed check mmad overflow failed N7AscendC5check20TikcppVecBinaryCheckE
GetHardwareBaseAddr tikcpp_vec_binary_check.cpp check src0 tensor buffersize failed check src1 tensor buffersize failed vcmpv dst and src0 address overlapping dst and src1 address overlapping src0 calculate size overflow src1 calculate size overflow [ERROR]instr %s dst addr is %lu, which should be 32B Aligned
[%s:%d]instr %s dst addr is %lu, which should be 32B Aligned
[ERROR]instr %s src0 addr is %lu, which should be 32B Aligned
[%s:%d]instr %s src0 addr is %lu, which should be 32B Aligned
[ERROR]instr %s src1 addr is %lu, which should be 32B Aligned
[%s:%d]instr %s src1 addr is %lu, which should be 32B Aligned
N7AscendC5check26TikcppVecBinaryScalarCheckE GetHardwareBaseAddr
tikcpp_vec_binary_scalar_check.cpp N7AscendC5check23TikcppVecBroadCastCheckE [ERROR]src dtype bytes is zeros tikcpp_vec_broadcast_check.cpp [%s:%d]src dtype bytes is zeros
N7AscendC5check24TikcppBroadCastToMMCheckE N7AscendC5check27TikcppVecCompareScalarCheckE
GetHardwareBaseAddr tikcpp_vec_compare_scalar_check.cpp N7AscendC5check17TikcppVecDupCheckE tikcpp_vec_dup_check.cpp N7AscendC5check20TikcppVecGatherCheckE [ERROR]offset dtype bytes is zeros tikcpp_vec_gather_check.cpp [%s:%d]offset dtype bytes is zeros
check offset tensor position failed check offset tensor buffersize failed offset calculate size overflow N7AscendC5check21TikcppGatherMaskCheckE tikcpp_vec_gather_mask_check.cpp N7AscendC5check22TikcppVecProposalCheckE src calculate size overflow [ERROR]valid bit number overflow 4. tikcpp_vec_proposal_check.cpp [%s:%d]valid bit number overflow 4.
[ERROR]src index overflow element size. [%s:%d]src index overflow element size.
vbs32 vconcat vextract vbs16 vms4 vms4v2 N7AscendC5check20TikcppVecReduceCheckE [ERROR]byteLen is %u, it shoule be greater than 0
tikcpp_vec_reduce_check.cpp [%s:%d]byteLen is %u, it shoule be greater than 0
[ERROR]%s, Reduce need dst data type (%u),dst src type (%u), dst wokr type (%u) should be same
[%s:%d]%s, Reduce need dst data type (%u),dst src type (%u), dst wokr type (%u) should be same
[ERROR]%s, Worktensor's size should be more than %lu, but get %lu
[%s:%d]%s, Worktensor's size should be more than %lu, but get %lu
[ERROR]dtype bytes is zeros [%s:%d]dtype bytes is zeros
[ERROR]%s, elementNumPerRep can not be 0.
[%s:%d]%s, elementNumPerRep can not be 0.
[ERROR]%s, Need least output size: %lu, while tensor size is %lu
[%s:%d]%s, Need least output size: %lu, while tensor size is %lu
Check Reduce data type Check Reduce dst data size check interface level 0 dst tensor position failed check interface level 0 src tensor position failed check interface level 0 work tensor position failed check work tensor buffersize failed vreduce_sum Check Reduce sum workLocal tensor size vreduce_max Check Reduce max workLocal tensor size Check Reduce min workLocal tensor size check interface level 2 dst tensor position failed check interface level 2 src tensor position failed check interface level 2 work tensor position failed Check Reduce Sum workLocal tensor size N7AscendC5check25TikcppVecReduceOtherCheckE [ERROR]%s, Reduce need dst data type (%u),dst src type (%u), should be same
tikcpp_vec_reduce_other_check.cpp [%s:%d]%s, Reduce need dst data type (%u),dst src type (%u), should be same
[ERROR]%s, srcSize is: %lu, output size: %lu, while dst tensor size should be half of src tensor size
[%s:%d]%s, srcSize is: %lu, output size: %lu, while dst tensor size should be half of src tensor size
vcmax vcmin vcadd vcgadd Check Whole Reduce data type Check Whole Reduce dst data size vcgmax vcgmin vcpadd Check Block Reduce dst data size Check Pair Reduce dst data size N7AscendC5check23TikcppVecTransposeCheckE void AscendC::ModelFactory::SetVARegGmAddr(uint32_t, uint64_t*) void AscendC::ModelFactory::GetVARegGmAddr(uint32_t, uint64_t (&)[8]) void AscendC::ModelFactory::SetVARegUbAddr(uint32_t, uint64_t*) void AscendC::ModelFactory::GetVARegUbAddr(uint32_t, uint64_t (&)[8]) SetGPRRegisters SetInput Run GetOutput uint64_t AscendC::ModelFactory::GetVectorExtent(uint16_t, uint16_t, uint16_t, uint16_t, uint16_t) const GetVectorExtent SetSPRRegisters BLOCKID PARA_BASE DATA_MAIN_BASE DATA_UB_BASE DATA_SIZE LPCNT BLOCKDIM FMATRIX PADDING L2_VADDR_BASE L0_SET_VALUE COREID L2_IN_MAIN RPN_COR_IR SMMU_TAG_VER L1_3D_SIZE AIPP_SPR_0 AIPP_SPR_1 AIPP_SPR_2 AIPP_SPR_3 AIPP_SPR_4 AIPP_SPR_5 AIPP_SPR_6 AIPP_SPR_7 AIPP_SPR_8 AIPP_SPR_9 AIPP_SPR_10 AIPP_SPR_11 AIPP_SPR_12 AIPP_SPR_13 AIPP_SPR_14 AIPP_SPR_15 AIPP_SPR_16 AIPP_SPR_17 AIPP_SPR_18 AIPP_SPR_19 AIPP_SPR_20 AIPP_SPR_21 AIPP_SPR_22 AIPP_SPR_23 AIPP_SPR_24 DATA_EXP_0 DATA_EXP_1 DATA_EXP_2 DATA_EXP_3 LOW_PRE_TBL SMASK_INDEX K_NUM RPN_OFFSET FCOL2IMG L3D_RPT PNT_COE VPIPE FPC QUANT_PRE QUANT_POST SYS_VA_BASE STACK_PHY_BASE VSP SYS_CNT VL SAFETY_CRC_EN SAFETY_CRC_DATA SAFETY_CRC_EXCP AIPP_SPR_25 AIPP_SPR_26 AIPP_SPR_27 AIPP_SPR_28 AIPP_SPR_29 AIPP_SPR_30 AIPP_SPR_31 THREAD_ID THREAD_DIM FIXP_ADDR FMATRIX_DUAL_0 ICACHE_PRL_ST FMATRIX_B PCIE_RD_CTRL PCIE_WR_CTRL SUBBLOCKDIM SUBBLOCKID ND_PARA FMATRIX_DUAL_1 FFTS_BASE_ADDR UNZIP_INDX_BASE UNZIP_INDX_LEN CMPMASK0 CMPMASK1 AIC_ERROR_MASK CUBE_CTRL_0 CUBE_CTRL_1 SMMU_STREAMID SMMU_SUBSTREAMID MEMMAP_0 MEMMAP_1 MEMMAP_2 MEMMAP_3 MEMMAP_4 MEMMAP_5 MEMMAP_6 MEMMAP_7 MEMMAP_8 MEMMAP_9 MEMMAP_10 MEMMAP_11 MEMMAP_12 MEMMAP_13 MEMMAP_14 MEMMAP_15 MEMMAP_16 MEMMAP_17 MEMMAP_18 MEMMAP_19 MEMMAP_20 MEMMAP_21 MEMMAP_22 MEMMAP_23 MEMMAP_24 MEMMAP_25 MEMMAP_26 MEMMAP_27 MEMMAP_28 MEMMAP_29 MEMMAP_30 MEMMAP_31 MEMMAP_32 MEMMAP_33 MEMMAP_34 MEMMAP_35 MEMMAP_36 MEMMAP_37 MEMMAP_38 MEMMAP_39 MEMMAP_40 MEMMAP_41 MEMMAP_42 MEMMAP_43 MEMMAP_44 MEMMAP_45 MEMMAP_46 MEMMAP_47 MEMMAP_48 MEMMAP_49 MEMMAP_50 MEMMAP_51 MEMMAP_52 MEMMAP_53 MEMMAP_54 MEMMAP_55 MEMMAP_56 MEMMAP_57 MEMMAP_58 MEMMAP_59 MEMMAP_60 MEMMAP_61 MEMMAP_62 MEMMAP_63 AIC_ERROR_0 AIC_ERROR_1 AIC_ERROR_2 AIC_ERROR_3 AIC_ERROR_4 AIC_ERROR_5 AIC_ERROR_MASK_0 AIC_ERROR_MASK_1 AIC_ERROR_MASK_2 AIC_ERROR_MASK_3 AIC_ERROR_MASK_4 AIC_ERROR_MASK_5 UNDE k3_pv_factory.cpp vaIndex < VA_REG_NUM [%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_gpr_register X(%ld) error, code: %d
[%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_memory error, mem_addr: %lu, mem_scope: %d, src_addr: %p, src_len: %lu, code: %d
[%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_instr error, %u
[%s:%d] block_idx: %d, core_type: %s %d %s:%spv_step error, instr_value: %u, code: %d
[%s:%d] block_idx: %d, core_type: %s %d %s:%spv_read_memory error, mem_addr: %lu, mem_scope: %u, src_addr: %p, src_len: %lu, code: %d
./simlog/ blockNum != 0 [%s:%d] block_idx: %d, core_type: %s %d %s: maskLow_=%lu, maskHigh_=%lu, maskLen=%hu, blkNumLastRep=%hu, eleNumLastBlk=%hu, maxOffset=%lu
[%s:%d] block_idx: %d, core_type: %s %d %s: maskLow_=%lu, maskHigh_=%lu, counterElements=%hu, inferredRepeatTimes=%hu, blkNumLastRep=%hu, eleNumLastBlk=%hu, maxOffset=%lu
[%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_spr_register %s error, code: %d
dcci dcci dcci dcci copy_matrix_cc_to_cbuf copy_matrix_cc_to_cbuf copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_cbuf copy_matrix_cc_to_cbuf copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_cbuf copy_matrix_cc_to_cbuf copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_cbuf copy_matrix_cc_to_cbuf copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_cbuf copy_matrix_cc_to_cbuf copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_cbuf copy_matrix_cc_to_cbuf copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_cbuf copy_matrix_cc_to_cbuf copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_gm copy_matrix_cc_to_gm kernel_operator_fixpipe_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ void*)dst, entire=%hu, type=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ void*)dst, entire=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cbuf__ %s*)dst, (__cc__ %s*)src, sid=%hhu, nSize=%hu, mSize=%hu, dstStrideDstD=%u, srcStride=%hu, unitFlagMode=%hhu, quantPre=%hhu, reluPre=%hhu, channelSplit=%hhu, nZ2NdEn=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ %s*)dst, (__cc__ %s*)src, sid=%hhu, nSize=%hu, mSize=%hu, dstStrideDstD=%u, srcStride=%hu, unitFlagMode=%hhu, quantPre=%hhu, reluPre=%hhu, channelSplit=%hhu, nZ2NdEn=%hhu);
void AscendC::CheckLoad2dParam(const AscendC::LoadData2DParams&) void AscendC::CheckLoadImageToL1Params(const AscendC::LoadImageToL1Params&) void AscendC::CheckBroadCastParam(uint8_t, uint8_t) mad_s4 mad_s4 mad_sp mad_sp set_padding set_padding set_padding set_padding set_padding set_padding set_l3d_rpt set_padding set_padding void AscendC::Load2dv1PvImpl(void*, void*, const AscendC::UnaryPvParams&, const AscendC::LoadData2DParams&) void AscendC::Load2dv1PvTransposeImpl(void*, void*, const AscendC::UnaryPvParams&, const AscendC::LoadData2dTransposeParams&) load_cbuf_to_cb_transpose_s4 load_cbuf_to_cb_transpose_s4 broadcast_ub_to_cc broadcast_ub_to_cc broadcast_ub_to_cc broadcast_ub_to_cc broadcast_ub_to_cc broadcast_ub_to_cc broadcast_ub_to_cc broadcast_ub_to_cc load_image_to_cbuf load_image_to_cbuf load_image_to_cbuf load_image_to_cbuf load_image_to_cbuf load_image_to_cbuf load_image_to_cbuf load_image_to_cbuf load_cbuf_to_ca_transpose load_cbuf_to_ca_transpose load_cbuf_to_cb_transpose load_cbuf_to_cb_transpose load_cbuf_to_ca_transpose load_cbuf_to_ca_transpose load_cbuf_to_cb_transpose load_cbuf_to_cb_transpose load_cbuf_to_ca_transpose load_cbuf_to_ca_transpose load_cbuf_to_cb_transpose load_cbuf_to_cb_transpose load_cbuf_to_ca_transpose load_cbuf_to_ca_transpose load_cbuf_to_cb_transpose load_cbuf_to_cb_transpose load_cbuf_to_ca_transpose load_cbuf_to_ca_transpose load_cbuf_to_cb_transpose load_cbuf_to_cb_transpose load_cbuf_to_ca_transpose load_cbuf_to_ca_transpose load_cbuf_to_cb_transpose load_cbuf_to_cb_transpose load_cbuf_to_ca_transpose load_cbuf_to_ca_transpose load_cbuf_to_cb_transpose load_cbuf_to_cb_transpose load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf load_cbuf_to_ca load_cbuf_to_ca load_cbuf_to_cb load_cbuf_to_cb load_gm_to_ca load_gm_to_ca load_gm_to_cb load_gm_to_cb load_gm_to_cbuf load_gm_to_cbuf mad mad mad mad mad mad mad mad mad mad mad mad mad mad mad mad mad mad mad mad load_cbuf_to_ca_s4 load_cbuf_to_ca_s4 load_cbuf_to_cb_s4 load_cbuf_to_cb_s4 void AscendC::CreateCaCbL1MatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = float16::Fp16T; S_T = float16::Fp16T; int64_t = long int] create_ca_matrix create_ca_matrix create_cb_matrix create_cb_matrix create_cbuf_matrix create_cbuf_matrix void AscendC::CreateCaCbL1MatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = short int; S_T = float16::Fp16T; int64_t = long int] create_ca_matrix create_ca_matrix create_cb_matrix create_cb_matrix create_cbuf_matrix create_cbuf_matrix void AscendC::CreateCaCbL1MatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = short unsigned int; S_T = float16::Fp16T; int64_t = long int] create_ca_matrix create_ca_matrix create_cb_matrix create_cb_matrix create_cbuf_matrix create_cbuf_matrix void AscendC::CreateCaCbL1MatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = int; S_T = unsigned int; int64_t = long int] create_ca_matrix create_ca_matrix create_cb_matrix create_cb_matrix create_cbuf_matrix create_cbuf_matrix void AscendC::CreateCaCbL1MatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = unsigned int; S_T = unsigned int; int64_t = long int] create_ca_matrix create_ca_matrix create_cb_matrix create_cb_matrix create_cbuf_matrix create_cbuf_matrix void AscendC::CreateCaCbL1MatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = float; S_T = unsigned int; int64_t = long int] create_ca_matrix create_ca_matrix create_cb_matrix create_cb_matrix create_cbuf_matrix create_cbuf_matrix void AscendC::CreateCaCbL1MatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = bfloat16::Bf16T; S_T = bfloat16::Bf16T; int64_t = long int] create_ca_matrix_bf16 create_ca_matrix_bf16 create_cb_matrix_bf16 create_cb_matrix_bf16 create_cbuf_matrix_bf16 create_cbuf_matrix_bf16 void AscendC::CheckLoad3dV1Param(const AscendC::LoadData3DParamsV1&) [with T = unsigned char] img2col_cbuf_to_ca img2col_cbuf_to_ca img2col_cbuf_to_cb img2col_cbuf_to_cb img2col_cbuf_to_ub img2col_cbuf_to_ub void AscendC::CheckLoad3dV1Param(const AscendC::LoadData3DParamsV1&) [with T = signed char] img2col_cbuf_to_ca img2col_cbuf_to_ca img2col_cbuf_to_cb img2col_cbuf_to_cb img2col_cbuf_to_ub img2col_cbuf_to_ub void AscendC::CheckLoad3dV1Param(const AscendC::LoadData3DParamsV1&) [with T = float16::Fp16T] img2col_cbuf_to_ca img2col_cbuf_to_ca img2col_cbuf_to_cb img2col_cbuf_to_cb img2col_cbuf_to_ub img2col_cbuf_to_ub void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = bfloat16::Bf16T] void AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = bfloat16::Bf16T] void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = bfloat16::Bf16T] img2colv2_cbuf_to_ca img2colv2_cbuf_to_ca img2colv2_cbuf_to_cb img2colv2_cbuf_to_cb void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = float16::Fp16T] void AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = float16::Fp16T] void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = float16::Fp16T] img2colv2_cbuf_to_ca img2colv2_cbuf_to_ca img2colv2_cbuf_to_cb img2colv2_cbuf_to_cb void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = float] void AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = float] void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = float] img2colv2_cbuf_to_ca img2colv2_cbuf_to_ca img2colv2_cbuf_to_cb img2colv2_cbuf_to_cb void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = unsigned int] void AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = unsigned int] void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = unsigned int] img2colv2_cbuf_to_ca img2colv2_cbuf_to_ca img2colv2_cbuf_to_cb img2colv2_cbuf_to_cb void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = int] void AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = int] void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = int] img2colv2_cbuf_to_ca img2colv2_cbuf_to_ca img2colv2_cbuf_to_cb img2colv2_cbuf_to_cb void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = unsigned char] void AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = unsigned char] void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = unsigned char] img2colv2_cbuf_to_ca img2colv2_cbuf_to_ca void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = signed char] void AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = signed char] void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = signed char] img2colv2_cbuf_to_ca img2colv2_cbuf_to_ca void AscendC::CheckMmadDtype() [with DstT = unsigned int; Src0T = unsigned char; Src1T = unsigned char] mad mad mad mad void AscendC::CheckMmadDtype() [with DstT = int; Src0T = unsigned char; Src1T = unsigned char] mad mad mad mad void AscendC::CheckMmadDtype() [with DstT = int; Src0T = unsigned char; Src1T = signed char] mad mad mad mad void AscendC::CheckMmadDtype() [with DstT = float16::Fp16T; Src0T = float16::Fp16T; Src1T = float16::Fp16T] mad mad mad mad void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = AscendC::IntegerSubType<4, true>] void AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = AscendC::IntegerSubType<4, true>] void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = AscendC::IntegerSubType<4, true>] img2colv2_cbuf_to_ca_s4 img2colv2_cbuf_to_ca_s4 false && "dst scope unsupported this data type" l1W > 0 l1H > 0 res && "data type unsupported" MAX_LOAD3D_L1 >= intriParams.l1H intriParams.l1H >= MIN_LOAD3D_L1 MAX_LOAD3D_L1 >= intriParams.l1W intriParams.l1W >= MIN_LOAD3D_L1 MAX_LOAD3D_C1_IDX >= intriParams.c1Index intriParams.leftTopW >= MIN_LOAD3D_LEFT_TOP intriParams.leftTopH >= MIN_LOAD3D_LEFT_TOP MAX_LOAD3D_STRIDE >= intriParams.strideW intriParams.strideW >= MIN_LOAD3D_STRIDE MAX_LOAD3D_STRIDE >= intriParams.strideH intriParams.strideH >= MIN_LOAD3D_STRIDE intriParams.filterW >= MIN_LOAD3D_FILTER intriParams.filterH >= MIN_LOAD3D_FILTER intriParams.dilationFilterW >= MIN_LOAD3D_DILATION_FILTER intriParams.dilationFilterH >= MIN_LOAD3D_DILATION_FILTER MAX_LOAD3D_JUMP_STRIDE >= intriParams.jumpStride intriParams.jumpStride >= MIN_LOAD3D_JUMP_STRIDE MAX_LOAD3D_REPEAT_MODE >= intriParams.repeatMode intriParams.repeatTime >= MIN_LOAD3D_REPEAT_TIMES MAX_LOAD3D_CSIZE >= intriParams.cSize intriParams.channelSize >= MIN_LOAD3D_CHANNEL_SIZE intriParams.kExtension >= MIN_LOAD3D_EXTENSION intriParams.mExtension >= MIN_LOAD3D_EXTENSION false && "dst pos unsupported." kernel_operator_mm_debug.cpp MAX_LOAD2D_SID >= intriParams.sid MAX_LOADIMANG_L1_HORSIZE >= intriParams.horSize MAX_LOADIMANG_L1_VERSIZE >= intriParams.verSize MAX_LOADIMANG_L1_HWSTART >= intriParams.horStartP MAX_LOADIMANG_L1_HWSTART >= intriParams.verStartP MAX_LOADIMANG_L1_TBPADSIZE >= intriParams.topPadSize MAX_LOADIMANG_L1_TBPADSIZE >= intriParams.botPadSize MAX_LOADIMANG_L1_LRPADSIZE >= intriParams.lPadSize MAX_LOADIMANG_L1_LRPADSIZE >= intriParams.rPadSize blockCount >= MIN_BLOCK_COUNT blockLen >= MIN_BLOCK_LEN [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ int32_t*)c, (__ca__ void*)a, (__cb__ void*)b, m=%hu, k=%hu, n=%hu, unitFlag=%hhu, kDirectionAlign=%hhu, cmatrixSource=%hhu, cmatrixInitVal=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ int32_t*)c, (__ca__ int8_t*)a, (__cb__ int8_t*)b, m=%hu, k=%hu, n=%hu, unitFlagMode=%hhu, cmatrixSource=%hhu, cmatrixInitVal=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s(padValue=%s);
[%s:%d] block_idx: %d, core_type: %s %d %s: set_l3d_rpt(%lu);
false && "dst scope unsupported." false && "dst scope only support l0a/l0b." [%s:%d] block_idx: %d, core_type: %s %d %s: %s(__cb__ void *dst, __cbuf__ void *src, indexId=%hu, repeat=%huu, srcStride=%hu, dstGap=%hu, addr_cal_mode_t=%huu, dstFracGap=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)dst, (__ubuf__ %s*)src, nBurst=%hhu, lenBurst=%hhu, srcGap=%hhu, dstGap=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cbuf__ %s*)dst, horSize=%hu, verSize=%hu, horStartP=%hu, verStartP=%hu, sHorRes=%hu, topPadSize=%Hhu, botPadSize=%hhu, lPadSize=%hu, rPadSize=%hhu, sid=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s %s*)dst, (%s %s*)src, indexId=%hu, repeat=%huu, srcStride=%hu, dstGap=%hu, addr_cal_mode_t=%huu, dstFracGap=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s %s*)dst, (%s %s*)src, baseIdx=%hu, repeat=%huu, srcStride=%hu, dstStride=%hu, sid=%huu, transpose=%hhu, addr_cal_mode_t=%huu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s %s*)dst, (%s %s*)src, baseIdx=%hu, repeat=%huu, srcStride=%hu, dstStride=%hu, sid=%huu, addr_cal_mode_t=%huu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)c, (__ca__ %s*)a, (__cb__ %s*)b=, m=%hu, k=%hu, n=%hu, init_val_controlC=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)c, (__ca__ %s*)a, (__cb__ %s*)b, m=%hu, k=%hu, n=%hu, unitFlag=%hhu, kDirectionAlign=%hhu, cmatrixSource=%hhu, cmatrixInitVal=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)c, (__ca__ %s*)a, (__cb__ %s*)b, bias=%llu, m=%hu, k=%hu, n=%hu, unitFlag=%hhu, kDirectionAlign=%hhu, cmatrixSource=%hhu, cmatrixInitVal=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s(__ca__ void *dst, __cbuf__ void *src, baseIdx=%hu, repeat=%huu, srcStride=%hu, dstStride=%hu, sid=%huu, transpose=%hhu, addr_cal_mode_t=%huu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s(__cb__ void *dst, __cbuf__ void *src, baseIdx=%hu, repeat=%huu, srcStride=%hu, dstStride=%hu, sid=%huu, transpose=%hhu, addr_cal_mode_t=%huu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__%s__ %s*)dst, repeat=%I64d, value=%s);
ca cb cbuf [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ca__ %s*)dst, (__cbuf__ %s*)src, posWk=%hhu, posHk=%hhu, firstWi=%hu, firstHi=%hu, idxChannel=%hu, strideW=%hhu, strideH=%hhu, Wk=%hhu, Hk=%hhu, dilationW=%hhu, dilationH=%hhu, dstJmpOffset=%hhu, enRepeat=%hhu, nRepeat=%hhu, c=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cb__ %s*)dst, (__cbuf__ %s*)src, posWk=%hhu, posHk=%hhu, firstWi=%hu, firstHi=%hu, idxChannel=%hu, strideW=%hhu, strideH=%hhu, Wk=%hhu, Hk=%hhu, dilationW=%hhu, dilationH=%hhu, dstJmpOffset=%hhu, enRepeat=%hhu, nRepeat=%hhu, c=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__cbuf__ %s*)src, posWk=%hhu, posHk=%hhu, firstWi=%hu, firstHi=%hu, idxChannel=%hu, strideW=%hhu, strideH=%hhu, Wk=%hhu, Hk=%hhu, dilationW=%hhu, dilationH=%hhu, dstJmpOffset=%hhu, enRepeat=%hhu, nRepeat=%hhu, c=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ca__ %s*)dst, (__cbuf__ %s*)src, kExtension=%hu, mExtension=%hu, kStartPt=%hu, mStartPt=%hu, strideW=%hhu, strideH=%hhu, Wk=%hu, Hk=%hu, dilationFilterW=%hhu, dilationFilterH=%hhu, filterSizeW=%hhu, filterSizeH=%hhu, transpose=%hhu, fMatrixCtrl=%hhu, sizeChannel=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cb__ %s*)dst, (__cbuf__ %s*)src, kExtension=%hu, mExtension=%hu, kStartPt=%hu, mStartPt=%hu, strideW=%hhu, strideH=%hhu, Wk=%hu, Hk=%hu, dilationFilterW=%hhu, dilationFilterH=%hhu, filterSizeW=%hhu, filterSizeH=%hhu, transpose=%hhu, fMatrixCtrl=%hhu, sizeChannel=%hu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ca__ void*)dst, (__cbuf__ void*)src, kExtension=%hu, mExtension=%hu, kStartPt=%hu, mStartPt=%hu, strideW=%hhu, strideH=%hhu, Wk=%hu, Hk=%hu, dilationFilterW=%hhu, dilationFilterH=%hhu, filterSizeW=%hhu, filterSizeH=%hhu, transpose=%hhu, fMatrixCtrl=%hhu, sizeChannel=%hu);
void {anonymous}::CheckRpSort16Param(int32_t) void {anonymous}::CheckMrgSort4Param(const AscendC::MrgSort4Info&) ProposalCompute ProposalCompute ProposalComputeVBS32 ProposalComputeVBS32 MrgSort4ModelProcess MrgSort4Compute MrgSort4ModelProcess MrgSort4Compute MrgSortModelProcess MrgSortCompute MrgSortModelProcess MrgSortCompute AscendC::MAX_SORT_ELE_LEN >= intriParams.elementLengths[i] [%s:%d] block_idx: %d, core_type: %s %d %s: vmrgsort4, dataType=%d, repeat=%hhu, params.elementLengths[0]=%hu, params.elementLengths[1]=%hu, params.elementLengths[2]=%hu, params.elementLengths[3]=%hu, params.ifExhaustedSuspension=%hu, params.validBit=%hu
SORT_VALID_BIT.find(intriParams.validBit) != SORT_VALID_BIT.end() AscendC::MAX_REPEAT_TIMES >= repeat vbitsort [%s:%d] block_idx: %d, core_type: %s %d %s: %s, dstLen=%d, srcLen=%d, dataType=%d, xmInstr=0x%X, repeat=%hhu, modeNumber=%hu
[%s:%d] block_idx: %d, core_type: %s %d %s: dstLen=%d, readMemAddr=0x%X, writeMemAddr0=0x%X, writeMemAddr1=0x%X, writeMemAddr2=0x%X, writeMemAddr3=0x%X
[%s:%d] block_idx: %d, core_type: %s %d %s: repeat mode is not valid
[%s:%d] block_idx: %d, core_type: %s %d %s: %s, dstLen=%d, src0Len=%d, src1Len=%d, dataType=%d, readMemAddr=0x%X, writeMemAddr1=0x%X, writeMemAddr2=0x%X, repeat=%hhu
kernel_operator_proposal_debug.cpp repeat >= AscendC::MIN_REPEAT_TIMES intriParams.repeatTimes >= AscendC::MIN_SORT_REPEAT_TIMES r afczo vmla vmla vmla vmla vmaddrelu vmaddrelu vmla vmla vmaddrelu vmaddrelu vadd vadd vsub vsub vmul vmul vdiv vdiv vmax vmax vmin vmin vmadd vmadd vaddrelu vaddrelu vsubrelu vsubrelu vadd vadd vsub vsub vmul vmul vdiv vdiv vmax vmax vmin vmin vmadd vmadd vaddrelu vaddrelu vsubrelu vsubrelu vadd vadd vsub vsub vmul vmul vmax vmax vmin vmin vand vand vor vor vadd vadd vsub vsub vmul vmul vmax vmax vmin vmin vaddrelu vaddrelu vsubrelu vsubrelu vand vand vor vor vmaddrelu kernel_operator_vec_binary_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src0, (__ubuf__ %s*)src1, repeat=%hhu, dstBlockStride=%hhu, src0BlockStride=%hhu, src1BlockStride=%hhu, dstRepeatStride=%hhu, src0RepeatStride=%hhu, src1RepeatStride=%hhu);
vmla r afczo vadds vadds vmuls vmuls vmaxs vmaxs vmins vmins vlrelu vlrelu vadds vadds vmuls vmuls vmaxs vmaxs vmins vmins vlrelu vlrelu vadds vadds vmuls vmuls vmaxs vmaxs vmins vmins vadds vadds vmuls vmuls vmaxs vmaxs vmins vmins vshr vshr vshr vshr vshl vshl vshl vshl vshl vshl vshl vshl vshr vshr vshr vshr kernel_operator_vec_binary_scalar_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, scalar=%s, repeat=%hu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, scalar=%s, repeat=%hu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu, repeatStrideMode=%hhu, strideSizeMode=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, scalar=%s, repeat=%hu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu, round=%hhu);
r afczo vbrcb vbrcb vbrcb vbrcb kernel_operator_vec_brcb_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src0, repeat=%hhu, dstBlockStride=%hhu, dstRepeatStride=%hhu)
vbrcb void AscendC::VcmpvComputeCCE(std::string, std::string, void*, void*, void*, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint32_t, uint32_t) vcmpv_eq vcmpv_eq vcmpv_eq vcmpv_eq vcmpv_ge vcmpv_ge vcmpv_ge vcmpv_ge vcmpv_gt vcmpv_gt vcmpv_gt vcmpv_gt vcmpv_le vcmpv_le vcmpv_le vcmpv_le vcmpv_lt vcmpv_lt vcmpv_lt vcmpv_lt vcmpv_ne vcmpv_ne vcmpv_ne vcmpv_ne vcmpv_eq vcmpv_eq vcmpvs_eq vcmpvs_eq void AscendC::VcmpvsComputeCCE(std::string, std::string, void*, void*, T, uint8_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, uint32_t) [with T = float16::Fp16T; std::string = std::basic_string; uint8_t = unsigned char; uint16_t = short unsigned int; uint32_t = unsigned int] vcmpvs_eq vcmpvs_eq vcmpvs_ge vcmpvs_ge vcmpvs_gt vcmpvs_gt vcmpvs_le vcmpvs_le vcmpvs_lt vcmpvs_lt vcmpvs_ne vcmpvs_ne void AscendC::VcmpvsComputeCCE(std::string, std::string, void*, void*, T, uint8_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, uint32_t) [with T = float; std::string = std::basic_string; uint8_t = unsigned char; uint16_t = short unsigned int; uint32_t = unsigned int] vcmpvs_eq vcmpvs_eq vcmpvs_ge vcmpvs_ge vcmpvs_gt vcmpvs_gt vcmpvs_le vcmpvs_le vcmpvs_lt vcmpvs_lt vcmpvs_ne vcmpvs_ne GetC0Count vsel vsel vsel vsel vsel vsel vsel vsel r afczo void AscendC::VcmpComputeCCE(std::string, std::string, void*, void*, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint32_t) vcmp_eq vcmp_eq vcmp_eq vcmp_eq vcmp_ge vcmp_ge vcmp_ge vcmp_ge vcmp_gt vcmp_gt vcmp_gt vcmp_gt vcmp_le vcmp_le vcmp_le vcmp_le vcmp_lt vcmp_lt vcmp_lt vcmp_lt vcmp_ne vcmp_ne vcmp_ne vcmp_ne kernel_operator_vec_cmpsel_debug.cpp (srcTypeSize > 0) && "Invalid src datatype size!" [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ uint8_t*)dst, (__ubuf__ %s*)src0, (__ubuf__ %s*)src1, repeat=%hhu, dstBlockStride=%hhu, src0BlockStride=%hhu, src1BlockStride=%hhu, dstRepeatStride=%hhu, src0RepeatStride=%hhu, src1RepeatStride=%hhu)
eq ge gt le lt ne [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ uint8_t*)dst, (__ubuf__ %s*)src0, (__ubuf__ %s*)src1, repeat=%hhu, dstBlockStride=%hhu, srcBlockStride=%hhu, dstRepeatStride=%hhu, srcRepeatStride=%hhu)
[ERROR][%s][%s][%s:%d][%s][%u] dtypeSize can not be 0
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src0, (__ubuf__ %s*)src1, repeat=%hhu, dstBlockStride=%hhu, src0BlockStride=%hhu, src1BlockStride=%hhu, dstRepeatStride=%hhu, src0RepeatStride=%hhu, src1RepeatStride=%hhu, selectMode=%hhu, repeatStrideMode=%hhu, strideSizeMode=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)src0, (__ubuf__ %s*)src1, repeat=%hhu, dstBlockStride=%hhu, src0BlockStride=%hhu, src1BlockStride=%hhu, dstRepeatStride=%hhu, src0RepeatStride=%hhu, src1RepeatStride=%hhu)
r afczo vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup vector_dup kernel_operator_vec_duplicate_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, scalar=%s, repeat=%hhu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu);
vgatherb vgatherb vgatherb vgatherb vgather vgather vgather vgather kernel_operator_vec_gather_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ int32_t*)offset, repeat=%hhu, dstBlockStride=%hhu, dstRepeatStride=%hhu)
vgatherb [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ int32_t*)offset, repeat=%hhu, dstRepeatStride=%hhu)
vgather vreducev2 vreducev2 vreducev2 vreducev2 kernel_operator_vec_gather_mask_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src0, (__ubuf__ %s*)src1, repeat=%hu, src0Blockstride=%hhu, src1Patten=%hhu, src0RepeatStride=%hu, src1RepeatStride=%hhu);
r afczo vmulconv_f162s8 vmulconv_f162s8 vmulconv_f162u8 vmulconv_f162u8 kernel_operator_vec_mulconv_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src0, (__ubuf__ half*)src1, repeat=%hu, dstBlockStride=%hu, src0BlockStride=%hu, src1BlockStride=%hu, dstRepeatStride=%hu, src0RepeatStride=%hu, src1RepeatStride=%hu)
vmulconv_f162s8 vmulconv_f162u8 ReduceComputeCCE WholeReduceComputeCCE BlockReduceSeries BlockReduceSeries WholeReduceSeries WholeReduceSeries WholeReduceSeriesC220 WholeReduceSeriesC220 [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, repeat=%hhu, dstRepStride=%hu, srcBlkStride=%hu, srcRepStride=%hu);
kernel_operator_vec_reduce_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: dst, src, dstLen=%d, srcLen=%d, dstScope=%d, srcScope=%d,dataType=%u, iMASK0=0x%llX, iMASK1=0x%llX, readMemAddr=0x%llX, riteMemAddr=0x%llX, xmInstr=0x%llX, repeat=%hhu,dstRepStride=%hu, srcBlkStride=%hu, srcRepStride=%hu
[%s:%d] block_idx: %d, core_type: %s %d %s: dst, src, dstLen=%d, srcLen=%d, dstScope=%d, srcScope=%d, dataType=%d, iMASK0=0x%llX, iMASK1=0x%llX, readMemAddr=0x%llX, writeMemAddr=0x%llX, xmInstr=0x%llX, repeat=%hhu, dstRepStride=%hu, srcBlkStride=%hu, srcRepStride=%hu, repeatStrideMode=%hu, strideSizeMode=%hu, order=%hu
r afczo vaxpy vaxpy vaxpy vaxpy vaxpy vaxpy kernel_operator_vec_ternary_scalar_debug.cpp r afczo GetC0Count vrelu vrelu vrelu vrelu vrelu vrelu vrelu vrelu vrelu vrelu vrelu vrelu vrec vrec vrec vrec vrec vrec vrec vrec vexp vexp vexp vexp vexp vexp vexp vexp vln vln vln vln vln vln vln vln vabs vabs vabs vabs vabs vabs vabs vabs vabs vabs vabs vabs vsqrt vsqrt vsqrt vsqrt vsqrt vsqrt vsqrt vsqrt vrsqrt vrsqrt vrsqrt vrsqrt vrsqrt vrsqrt vrsqrt vrsqrt vnot vnot vnot vnot vnot vnot vnot vnot vabs vabs vabs vabs kernel_operator_vec_unary_debug.cpp [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, repeat=%hhu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu);
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, repeat=%hhu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu, repeatStrideMode=%hhu, strideSizeMode=%hhu);
uint32_t AscendC::encoding::VconvEncoding::SplitTypeStr(std::string) const GetC0Count r afczo char AscendC::encoding::VconvEncoding::GetRndType(std::string) const std::string AscendC::encoding::VconvEncoding::GetDstType(std::string) const std::string AscendC::encoding::VconvEncoding::GetSrcType(std::string) const vconv_deq vconv_deq vconv_f162f32 vconv_f162f32 vconv_f162s32a vconv_f162s32a vconv_f162s32c vconv_f162s32c vconv_f162s32f vconv_f162s32f vconv_f162s32r vconv_f162s32r vconv_f162s32z vconv_f162s32z vconv_f162s8 vconv_f162s8 vconv_f162s8a vconv_f162s8a vconv_f162s8c vconv_f162s8c vconv_f162s8f vconv_f162s8f vconv_f162s8z vconv_f162s8z vconv_f162u8 vconv_f162u8 vconv_f162u8a vconv_f162u8a vconv_f162u8c vconv_f162u8c vconv_f162u8f vconv_f162u8f vconv_f162u8z vconv_f162u8z vconv_f322f16 vconv_f322f16 vconv_f322f16o vconv_f322f16o vconv_f322s16r vconv_f322s16r vconv_f322s16z vconv_f322s16z vconv_f322s32a vconv_f322s32a vconv_f322s32c vconv_f322s32c vconv_f322s32f vconv_f322s32f vconv_f322s32r vconv_f322s32r vconv_f322s32z vconv_f322s32z vconv_s162f32 vconv_s162f32 vconv_s322f32 vconv_s322f32 vconv_s322f32a vconv_s322f32a vconv_s322f32c vconv_s322f32c vconv_s322f32f vconv_s322f32f vconv_s322f32r vconv_s322f32r vconv_s322f32z vconv_s322f32z vconv_s82f16 vconv_s82f16 vconv_u82f16 vconv_u82f16 vconv_deqs162b8h vconv_deqs162b8h vconv_deqs162b8h vconv_deqs162b8h vconv_deqs162b8l vconv_deqs162b8l vconv_deqs162b8l vconv_deqs162b8l vconv_vdeqs162b8h vconv_vdeqs162b8h vconv_vdeqs162b8h vconv_vdeqs162b8h vconv_vdeqs162b8l vconv_vdeqs162b8l vconv_vdeqs162b8l vconv_vdeqs162b8l vconv_f162s8r vconv_f162s8r vconv_f162u8r vconv_f162u8r vconv_f322f16a vconv_f322f16a vconv_f322f16c vconv_f322f16c vconv_f322f16f vconv_f322f16f vconv_f322f16r vconv_f322f16r vconv_f322f16z vconv_f322f16z vconv_f322s16a vconv_f322s16a vconv_f322s16c vconv_f322s16c vconv_f322s16f vconv_f322s16f vconv_f322s16r vconv_f322s16r vconv_f322s16z vconv_f322s16z vconv_f322s32a vconv_f322s32a vconv_f322s32c vconv_f322s32c vconv_f322s32f vconv_f322s32f vconv_f322s32r vconv_f322s32r vconv_f322s32z vconv_f322s32z vconv_s162f16 vconv_s162f16 vconv_s162f16a vconv_s162f16a vconv_s162f16c vconv_s162f16c vconv_s162f16f vconv_s162f16f vconv_s162f16r vconv_s162f16r vconv_s162f16z vconv_s162f16z vconv_s162f32 vconv_s162f32 vconv_s322f32 vconv_s322f32 vconv_s322f32a vconv_s322f32a vconv_s322f32c vconv_s322f32c vconv_s322f32f vconv_s322f32f vconv_s322f32r vconv_s322f32r vconv_s322f32z vconv_s322f32z vconv_s82f16 vconv_s82f16 vconv_u82f16 vconv_u82f16 vconv_f322f32a vconv_f322f32a vconv_f322f32c vconv_f322f32c vconv_f322f32f vconv_f322f32f vconv_f322f32r vconv_f322f32r vconv_f322f32z vconv_f322f32z vconv_f322bf16a vconv_f322bf16a vconv_f322bf16c vconv_f322bf16c vconv_f322bf16f vconv_f322bf16f vconv_f322bf16r vconv_f322bf16r vconv_f322bf16z vconv_f322bf16z vconv_f322s64a vconv_f322s64a vconv_f322s64c vconv_f322s64c vconv_f322s64f vconv_f322s64f vconv_f322s64r vconv_f322s64r vconv_f322s64z vconv_f322s64z vconv_bf162f32 vconv_bf162f32 vconv_bf162s32a vconv_bf162s32a vconv_bf162s32c vconv_bf162s32c vconv_bf162s32f vconv_bf162s32f vconv_bf162s32r vconv_bf162s32r vconv_bf162s32z vconv_bf162s32z vconv_f162s16a vconv_f162s16a vconv_f162s16c vconv_f162s16c vconv_f162s16f vconv_f162s16f vconv_f162s16r vconv_f162s16r vconv_f162s16z vconv_f162s16z vconv_s322s16 vconv_s322s16 vconv_s322s64 vconv_s322s64 vconv_s642f32a vconv_s642f32a vconv_s642f32c vconv_s642f32c vconv_s642f32f vconv_s642f32f vconv_s642f32r vconv_s642f32r vconv_s642f32z vconv_s642f32z vconv_s642s32 vconv_s642s32 vconv_s42f16 vconv_s42f16 vconv_f162s4 vconv_f162s4 vconv_f162s4a vconv_f162s4a vconv_f162s4c vconv_f162s4c vconv_f162s4f vconv_f162s4f vconv_f162s4r vconv_f162s4r vconv_f162s4z vconv_f162s4z vaddreluconv_f162s8 vaddreluconv_f162s8 vsubreluconv_f162s8 vsubreluconv_f162s8 vaddreluconv_s162s8 vaddreluconv_s162s8 vsubreluconv_s162s8 vsubreluconv_s162s8 vaddreluconv_f322f16 vaddreluconv_f322f16 vsubreluconv_f322f16 vsubreluconv_f322f16 kernel_operator_vec_vconv_debug.cpp convType.size() != 0 [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, repeat=%hhu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu)
f162f32 f162s32a f162s32c f162s32f f162s32r f162s32z f162s8a f162s8c f162s8f f162s8z f162u8 f162u8a f162u8c f162u8f f162u8z f322f16o f322s16r f322s16z f322s32a f322s32c f322s32f f322s32r f322s32z s162f32 s322f32 s322f32a s322f32c s322f32f s322f32r s322f32z s82f16 u82f16 f162s8r f162u8r f322f16a f322f16c f322f16f f322f16r f322f16z f322s16a f322s16c f322s16f s162f16 s162f16a s162f16c s162f16f s162f16r s162f16z f322f32a f322f32c f322f32f f322f32r f322f32z f322bf16a f322bf16c f322bf16f f322bf16r f322bf16z int64_t f322s64a f322s64c f322s64f f322s64r f322s64z bf162f32 bf162s32a bf162s32c bf162s32f bf162s32r bf162s32z f162s16a f162s16c f162s16f f162s16r f162s16z s322s16 s322s64 s642f32a s642f32c s642f32f s642f32r s642f32z s642s32 [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ half*)dst, (__ubuf__ void*)src, repeat=%hhu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu)
[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ void*)dst, (__ubuf__ half*)src, repeat=%hhu, dstBlockStride=%hu, srcBlockStride=%hu, dstRepeatStride=%hhu, srcRepeatStride=%hhu)
f162s4 f162s4a f162s4c f162s4f f162s4r f162s4z [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src0, (__ubuf__ %s*)src1, repeat=%hhu, dstBlockStride=%hhu, src0BlockStride=%hhu, src1BlockStride=%hhu, dstRepeatStride=%hhu, src0RepeatStride=%hhu, src1RepeatStride=%hhu, h=%hhu);
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_ZZN7AscendC20copy_matrix_cc_to_gmEPhPihttjth11QuantMode_thbbE12__FUNCTION__ _ZZN7AscendC20copy_matrix_cc_to_gmEPfS0_httjth11QuantMode_thbbE8__func__ _ZZN7AscendC20copy_matrix_cc_to_gmEPfS0_httjth11QuantMode_thbbE12__FUNCTION__ _ZZN7AscendC20copy_matrix_cc_to_gmEPiS0_httjth11QuantMode_thbbE8__func__ _ZZN7AscendC20copy_matrix_cc_to_gmEPiS0_httjth11QuantMode_thbbE12__FUNCTION__ _ZN7AscendCL11DST_POS_MAPE _ZN7AscendCL12GetPvMemTypeENS_8HardwareE _ZNSs4_Rep9_S_createEmmRKSaIcE.isra.59 _ZNSt6vectorISt4pairISsmESaIS1_EEC2ESt16initializer_listIS1_ERKS2_.constprop.124 _GLOBAL__sub_I_kernel_operator_mm_debug.cpp _ZZN7AscendC16CheckLoad2dParamERKNS_16LoadData2DParamsEE19__PRETTY_FUNCTION__ _ZZN7AscendC24CheckLoadImageToL1ParamsERKNS_19LoadImageToL1ParamsEE19__PRETTY_FUNCTION__ _ZZN7AscendC19CheckBroadCastParamEhhE19__PRETTY_FUNCTION__ _ZZN7AscendC6mad_s4EPiPvS1_ttthbbbE8__func__ _ZZN7AscendC6mad_s4EPiPvS1_ttthbbbE12__FUNCTION__ _ZZN7AscendC6mad_spEPiPaS1_ttthbbE8__func__ _ZZN7AscendC6mad_spEPiPaS1_ttthbbE12__FUNCTION__ _ZZN7AscendC11set_paddingEtE8__func__ _ZZN7AscendC11set_paddingEtE12__FUNCTION__ _ZZN7AscendC11set_paddingEsE8__func__ _ZZN7AscendC11set_paddingEsE12__FUNCTION__ _ZZN7AscendC11set_paddingEmE8__func__ _ZZN7AscendC11set_paddingEmE12__FUNCTION__ _ZZN7AscendC11set_l3d_rptEmE12__FUNCTION__ _ZZN7AscendC11set_paddingEN7float165Fp16TEE8__func__ _ZZN7AscendC11set_paddingEN7float165Fp16TEE12__FUNCTION__ _ZZN7AscendC14Load2dv1PvImplEPvS0_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_16LoadData2DParamsEE19__PRETTY_FUNCTION__ _ZZN7AscendC23Load2dv1PvTransposeImplEPvS0_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_25LoadData2dTransposeParamsEE19__PRETTY_FUNCTION__ _ZZN7AscendC28load_cbuf_to_cb_transpose_s4EPvS0_thttbtE8__func__ _ZZN7AscendC28load_cbuf_to_cb_transpose_s4EPvS0_thttbtE12__FUNCTION__ _ZZN7AscendC18broadcast_ub_to_ccEPiS0_hhhhE8__func__ _ZZN7AscendC18broadcast_ub_to_ccEPiS0_hhhhE12__FUNCTION__ _ZZN7AscendC18broadcast_ub_to_ccEPfS0_hhhhE8__func__ _ZZN7AscendC18broadcast_ub_to_ccEPfS0_hhhhE12__FUNCTION__ _ZZN7AscendC18broadcast_ub_to_ccEPN7float165Fp16TES2_hhhhE8__func__ _ZZN7AscendC18broadcast_ub_to_ccEPN7float165Fp16TES2_hhhhE12__FUNCTION__ _ZZN7AscendC18broadcast_ub_to_ccEPfPN7float165Fp16TEhhhhE8__func__ _ZZN7AscendC18broadcast_ub_to_ccEPfPN7float165Fp16TEhhhhE12__FUNCTION__ _ZZN7AscendC18load_image_to_cbufEPN7float165Fp16TEttttthhtthE8__func__ _ZZN7AscendC18load_image_to_cbufEPN7float165Fp16TEttttthhtthE12__FUNCTION__ _ZZN7AscendC18load_image_to_cbufEPsttttthhtthE8__func__ _ZZN7AscendC18load_image_to_cbufEPsttttthhtthE12__FUNCTION__ _ZZN7AscendC18load_image_to_cbufEPattttthhtthE8__func__ _ZZN7AscendC18load_image_to_cbufEPattttthhtthE12__FUNCTION__ _ZZN7AscendC18load_image_to_cbufEPhttttthhtthE8__func__ _ZZN7AscendC18load_image_to_cbufEPhttttthhtthE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPhS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPhS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPhS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPhS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPaS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPaS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPaS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPaS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPjS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPjS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPjS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPjS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPiS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPiS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPiS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPiS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPfS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPfS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPfS0_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPfS0_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPN8bfloat165Bf16TES2_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPN8bfloat165Bf16TES2_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPN8bfloat165Bf16TES2_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPN8bfloat165Bf16TES2_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPN7float165Fp16TES2_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_ca_transposeEPN7float165Fp16TES2_thttbtE12__FUNCTION__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPN7float165Fp16TES2_thttbtE8__func__ _ZZN7AscendC25load_cbuf_to_cb_transposeEPN7float165Fp16TES2_thttbtE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPhS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPhS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPhS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPhS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPhS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPhS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPhS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPhS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPhS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPhS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPaS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPaS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPaS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPaS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPaS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPaS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPaS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPaS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPaS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPaS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPtS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPtS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPtS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPtS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPtS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPtS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPtS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPtS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPtS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPtS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPsS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPsS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPsS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPsS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPsS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPsS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPsS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPsS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPsS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPsS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPN7float165Fp16TES2_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPN7float165Fp16TES2_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPN7float165Fp16TES2_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPN7float165Fp16TES2_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPN7float165Fp16TES2_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPN7float165Fp16TES2_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPN7float165Fp16TES2_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPN7float165Fp16TES2_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPN7float165Fp16TES2_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPN7float165Fp16TES2_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPjS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPjS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPjS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPjS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPjS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPjS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPjS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPjS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPjS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPjS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPiS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPiS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPiS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPiS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPiS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPiS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPiS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPiS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPiS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPiS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPfS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPfS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPfS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPfS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPfS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPfS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPfS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPfS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPfS0_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPfS0_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_caEPN8bfloat165Bf16TES2_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_caEPN8bfloat165Bf16TES2_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_cbuf_to_cbEPN8bfloat165Bf16TES2_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_cbuf_to_cbEPN8bfloat165Bf16TES2_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_caEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_caEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC13load_gm_to_cbEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC13load_gm_to_cbEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC15load_gm_to_cbufEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_tE8__func__ _ZZN7AscendC15load_gm_to_cbufEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC3madEPiPaS1_tttbE8__func__ _ZZN7AscendC3madEPiPaS1_tttbE12__FUNCTION__ _ZZN7AscendC3madEPiPaS1_ttthbbbE8__func__ _ZZN7AscendC3madEPiPaS1_ttthbbbE12__FUNCTION__ _ZZN7AscendC3madEPiPaS1_mttthbbbE8__func__ _ZZN7AscendC3madEPiPaS1_mttthbbbE12__FUNCTION__ _ZZN7AscendC3madEPfPN7float165Fp16TES3_tttbE8__func__ _ZZN7AscendC3madEPfPN7float165Fp16TES3_tttbE12__FUNCTION__ _ZZN7AscendC3madEPfPN7float165Fp16TES3_ttthbbbE8__func__ _ZZN7AscendC3madEPfPN7float165Fp16TES3_ttthbbbE12__FUNCTION__ _ZZN7AscendC3madEPfPN7float165Fp16TES3_mttthbbbE8__func__ _ZZN7AscendC3madEPfPN7float165Fp16TES3_mttthbbbE12__FUNCTION__ _ZZN7AscendC3madEPfS0_S0_ttthbbbE8__func__ _ZZN7AscendC3madEPfS0_S0_ttthbbbE12__FUNCTION__ _ZZN7AscendC3madEPfS0_S0_mttthbbbE8__func__ _ZZN7AscendC3madEPfS0_S0_mttthbbbE12__FUNCTION__ _ZZN7AscendC3madEPfPN8bfloat165Bf16TES3_ttthbbbE8__func__ _ZZN7AscendC3madEPfPN8bfloat165Bf16TES3_ttthbbbE12__FUNCTION__ _ZZN7AscendC3madEPfPN8bfloat165Bf16TES3_mttthbbbE8__func__ _ZZN7AscendC3madEPfPN8bfloat165Bf16TES3_mttthbbbE12__FUNCTION__ _ZZN7AscendC18load_cbuf_to_ca_s4EPvS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC18load_cbuf_to_ca_s4EPvS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC18load_cbuf_to_cb_s4EPvS0_thtthb15addr_cal_mode_tE8__func__ _ZZN7AscendC18load_cbuf_to_cb_s4EPvS0_thtthb15addr_cal_mode_tE12__FUNCTION__ _ZZN7AscendC20CreateCaCbL1MatrixPvIN7float165Fp16TES2_EEvNS_8HardwareEPT_lT0_E19__PRETTY_FUNCTION__ _ZZN7AscendC16create_ca_matrixEPN7float165Fp16TElS1_E8__func__ _ZZN7AscendC16create_ca_matrixEPN7float165Fp16TElS1_E12__FUNCTION__ _ZZN7AscendC16create_cb_matrixEPN7float165Fp16TElS1_E8__func__ _ZZN7AscendC16create_cb_matrixEPN7float165Fp16TElS1_E12__FUNCTION__ _ZZN7AscendC18create_cbuf_matrixEPN7float165Fp16TElS1_E8__func__ _ZZN7AscendC18create_cbuf_matrixEPN7float165Fp16TElS1_E12__FUNCTION__ _ZZN7AscendC20CreateCaCbL1MatrixPvIsN7float165Fp16TEEEvNS_8HardwareEPT_lT0_E19__PRETTY_FUNCTION__ _ZZN7AscendC16create_ca_matrixEPslN7float165Fp16TEE8__func__ _ZZN7AscendC16create_ca_matrixEPslN7float165Fp16TEE12__FUNCTION__ _ZZN7AscendC16create_cb_matrixEPslN7float165Fp16TEE8__func__ _ZZN7AscendC16create_cb_matrixEPslN7float165Fp16TEE12__FUNCTION__ _ZZN7AscendC18create_cbuf_matrixEPslN7float165Fp16TEE8__func__ _ZZN7AscendC18create_cbuf_matrixEPslN7float165Fp16TEE12__FUNCTION__ _ZZN7AscendC20CreateCaCbL1MatrixPvItN7float165Fp16TEEEvNS_8HardwareEPT_lT0_E19__PRETTY_FUNCTION__ _ZZN7AscendC16create_ca_matrixEPtlN7float165Fp16TEE8__func__ _ZZN7AscendC16create_ca_matrixEPtlN7float165Fp16TEE12__FUNCTION__ _ZZN7AscendC16create_cb_matrixEPtlN7float165Fp16TEE8__func__ _ZZN7AscendC16create_cb_matrixEPtlN7float165Fp16TEE12__FUNCTION__ _ZZN7AscendC18create_cbuf_matrixEPtlN7float165Fp16TEE8__func__ _ZZN7AscendC18create_cbuf_matrixEPtlN7float165Fp16TEE12__FUNCTION__ _ZZN7AscendC20CreateCaCbL1MatrixPvIijEEvNS_8HardwareEPT_lT0_E19__PRETTY_FUNCTION__ _ZZN7AscendC16create_ca_matrixEPiljE8__func__ _ZZN7AscendC16create_ca_matrixEPiljE12__FUNCTION__ _ZZN7AscendC16create_cb_matrixEPiljE8__func__ _ZZN7AscendC16create_cb_matrixEPiljE12__FUNCTION__ _ZZN7AscendC18create_cbuf_matrixEPiljE8__func__ _ZZN7AscendC18create_cbuf_matrixEPiljE12__FUNCTION__ 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_ZZN7AscendC21create_cb_matrix_bf16EPN8bfloat165Bf16TElS1_E8__func__ _ZZN7AscendC21create_cb_matrix_bf16EPN8bfloat165Bf16TElS1_E12__FUNCTION__ _ZZN7AscendC23create_cbuf_matrix_bf16EPN8bfloat165Bf16TElS1_E8__func__ _ZZN7AscendC23create_cbuf_matrix_bf16EPN8bfloat165Bf16TElS1_E12__FUNCTION__ _ZZN7AscendC18CheckLoad3dV1ParamIhEEvRKNS_18LoadData3DParamsV1IT_EEE19__PRETTY_FUNCTION__ _ZZN7AscendC18img2col_cbuf_to_caEPhS0_hhssthhhhhhhhh7csize_tE8__func__ _ZZN7AscendC18img2col_cbuf_to_caEPhS0_hhssthhhhhhhhh7csize_tE12__FUNCTION__ _ZZN7AscendC18img2col_cbuf_to_cbEPhS0_hhssthhhhhhhhh7csize_tE8__func__ _ZZN7AscendC18img2col_cbuf_to_cbEPhS0_hhssthhhhhhhhh7csize_tE12__FUNCTION__ _ZZN7AscendC18img2col_cbuf_to_ubEPhS0_hhssthhhhhhhhh7csize_tE8__func__ _ZZN7AscendC18img2col_cbuf_to_ubEPhS0_hhssthhhhhhhhh7csize_tE12__FUNCTION__ _ZZN7AscendC18CheckLoad3dV1ParamIaEEvRKNS_18LoadData3DParamsV1IT_EEE19__PRETTY_FUNCTION__ _ZZN7AscendC18img2col_cbuf_to_caEPaS0_hhssthhhhhhhhh7csize_tE8__func__ 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