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ta2DParamsE_ZN7AscendC15load_cbuf_to_caEPhS0_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPhS0_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPhS0_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPhS0_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPhS0_thtth15addr_cal_mode_t_ZN7AscendC8Load2DPvIaEEvPT_S2_NS_8HardwareES3_RKNS_16LoadData2DParamsE_ZN7AscendC15load_cbuf_to_caEPaS0_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPaS0_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPaS0_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPaS0_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPaS0_thtth15addr_cal_mode_t_ZN7AscendC8Load2DPvItEEvPT_S2_NS_8HardwareES3_RKNS_16LoadData2DParamsE_ZN7AscendC15load_cbuf_to_caEPtS0_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPtS0_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPtS0_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPtS0_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPtS0_thtth15addr_cal_mode_t_ZN7AscendC8Load2DPvIsEEvPT_S2_NS_8HardwareES3_RKNS_16LoadData2DParamsE_ZN7AscendC15load_cbuf_to_caEPsS0_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPsS0_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPsS0_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPsS0_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPsS0_thtth15addr_cal_mode_t_ZN7AscendC8Load2DPvIN7float165Fp16TEEEvPT_S4_NS_8HardwareES5_RKNS_16LoadData2DParamsE_ZN7AscendC15load_cbuf_to_caEPN7float165Fp16TES2_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPN7float165Fp16TES2_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPN7float165Fp16TES2_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPN7float165Fp16TES2_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPN7float165Fp16TES2_thtth15addr_cal_mode_t_ZN7AscendC8Load2DPvIjEEvPT_S2_NS_8HardwareES3_RKNS_16LoadData2DParamsE_ZN7AscendC15load_cbuf_to_caEPjS0_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPjS0_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPjS0_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPjS0_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPjS0_thtth15addr_cal_mode_t_ZN7AscendC8Load2DPvIiEEvPT_S2_NS_8HardwareES3_RKNS_16LoadData2DParamsE_ZN7AscendC15load_cbuf_to_caEPiS0_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPiS0_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPiS0_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPiS0_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPiS0_thtth15addr_cal_mode_t_ZN7AscendC8Load2DPvIfEEvPT_S2_NS_8HardwareES3_RKNS_16LoadData2DParamsE_ZN7AscendC15load_cbuf_to_caEPfS0_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPfS0_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPfS0_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPfS0_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPfS0_thtth15addr_cal_mode_t_ZN7AscendC8Load2DPvIN8bfloat165Bf16TEEEvPT_S4_NS_8HardwareES5_RKNS_16LoadData2DParamsE_ZN7AscendC15load_cbuf_to_caEPN8bfloat165Bf16TES2_thttb15addr_cal_mode_t_ZN7AscendC15load_cbuf_to_cbEPN8bfloat165Bf16TES2_thttb15addr_cal_mode_t_ZN7AscendC13load_gm_to_caEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_t_ZN7AscendC13load_gm_to_cbEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_t_ZN7AscendC15load_gm_to_cbufEPN8bfloat165Bf16TES2_thtth15addr_cal_mode_t_ZN7AscendC6MmadPvIiaaEEvPT_PT0_PT1_ttthbbb_ZN7AscendC3madEPiPaS1_tttb_ZN7AscendC3madEPiPaS1_ttthbbb_ZN7AscendC6MmadPvIfN7float165Fp16TES2_EEvPT_PT0_PT1_ttthbbb_ZN7AscendC3madEPfPN7float165Fp16TES3_tttb_ZN7AscendC3madEPfPN7float165Fp16TES3_ttthbbb_ZN7AscendC18CreateCaCbMatrixPvIN7float165Fp16TES2_EEvNS_8HardwareEPT_lT0__ZN7AscendC16create_ca_matrixEPN7float165Fp16TElS1__ZN7AscendC16create_cb_matrixEPN7float165Fp16TElS1__ZN7AscendC18CreateCaCbMatrixPvIfjEEvNS_8HardwareEPT_lT0__ZN7AscendC16create_ca_matrixEPflj_ZN7AscendC16create_cb_matrixEPflj_ZN7AscendC18CreateCaCbMatrixPvIjjEEvNS_8HardwareEPT_lT0__ZN7AscendC18create_cbuf_matrixEPjlj_ZN7AscendC18CheckLoad3dV2ParamIN8bfloat165Bf16TEEEvRKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC8Load3dv2IN8bfloat165Bf16TEEEvPvS3_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC10Load3DV2PvIN8bfloat165Bf16TEEEvPT_S4_NS_8HardwareES5_RKNS_18LoadData3DParamsV2IS3_EE_ZN7AscendC20img2colv2_cbuf_to_caEPN8bfloat165Bf16TES2_tttthhhhhhbbbbt_ZN7AscendC20img2colv2_cbuf_to_cbEPN8bfloat165Bf16TES2_tttthhhhhhbbbbt_ZN7AscendC18CheckLoad3dV2ParamIN7float165Fp16TEEEvRKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC8Load3dv2IN7float165Fp16TEEEvPvS3_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC10Load3DV2PvIN7float165Fp16TEEEvPT_S4_NS_8HardwareES5_RKNS_18LoadData3DParamsV2IS3_EE_ZN7AscendC20img2colv2_cbuf_to_caEPN7float165Fp16TES2_tttthhhhhhbbbbt_ZN7AscendC20img2colv2_cbuf_to_cbEPN7float165Fp16TES2_tttthhhhhhbbbbt_ZN7AscendC18CheckLoad3dV2ParamIfEEvRKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC8Load3dv2IfEEvPvS1_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC10Load3DV2PvIfEEvPT_S2_NS_8HardwareES3_RKNS_18LoadData3DParamsV2IS1_EE_ZN7AscendC20img2colv2_cbuf_to_caEPfS0_tttthhhhhhbbbbt_ZN7AscendC20img2colv2_cbuf_to_cbEPfS0_tttthhhhhhbbbbt_ZN7AscendC18CheckLoad3dV2ParamIjEEvRKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC8Load3dv2IjEEvPvS1_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC10Load3DV2PvIjEEvPT_S2_NS_8HardwareES3_RKNS_18LoadData3DParamsV2IS1_EE_ZN7AscendC20img2colv2_cbuf_to_caEPjS0_tttthhhhhhbbbbt_ZN7AscendC20img2colv2_cbuf_to_cbEPjS0_tttthhhhhhbbbbt_ZN7AscendC18CheckLoad3dV2ParamIiEEvRKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC8Load3dv2IiEEvPvS1_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC10Load3DV2PvIiEEvPT_S2_NS_8HardwareES3_RKNS_18LoadData3DParamsV2IS1_EE_ZN7AscendC20img2colv2_cbuf_to_caEPiS0_tttthhhhhhbbbbt_ZN7AscendC20img2colv2_cbuf_to_cbEPiS0_tttthhhhhhbbbbt_ZN7AscendC18CheckLoad3dV2ParamIhEEvRKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC8Load3dv2IhEEvPvS1_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC10Load3DV2PvIhEEvPT_S2_NS_8HardwareES3_RKNS_18LoadData3DParamsV2IS1_EE_ZN7AscendC20img2colv2_cbuf_to_caEPhS0_tttthhhhhhbbbbt_ZN7AscendC18CheckLoad3dV2ParamIaEEvRKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC8Load3dv2IaEEvPvS1_RKNS_13UnaryPvParamsINS_8DataTypeEEERKNS_18LoadData3DParamsV2IT_EE_ZN7AscendC10Load3DV2PvIaEEvPT_S2_NS_8HardwareES3_RKNS_18LoadData3DParamsV2IS1_EE_ZN7AscendC20img2colv2_cbuf_to_caEPaS0_tttthhhhhhbbbbt_ZN7AscendC20img2colv2_cbuf_to_cbEPaS0_tttthhhhhhbbbbt_ZN7AscendC14CheckMmadDtypeIjhhEEvv_ZN7AscendC3madEPjPhS1_tttb_ZN7AscendC3madEPjPhS1_ttthbbb_ZN7AscendC14CheckMmadDtypeIihhEEvv_ZN7AscendC3madEPiPhS1_tttb_ZN7AscendC3madEPiPhS1_ttthbbb_ZN7AscendC14CheckMmadDtypeIihaEEvv_ZN7AscendC3madEPiPhPatttb_ZN7AscendC3madEPiPhPattthbbb_ZN7AscendC14CheckMmadDtypeIN7float165Fp16TES2_S2_EEvv_ZN7AscendC3madEPN7float165Fp16TES2_S2_tttb_ZN7AscendC3madEPN7float165Fp16TES2_S2_ttthbbb_ZNSt8_Rb_treeIN7AscendC8HardwareESt4pairIKS1_NS0_10PVMemScopeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE8_M_eraseEPSt13_Rb_tree_nodeIS5_E_ZNSt3mapIN7AscendC8HardwareENS0_10PVMemScopeESt4lessIS1_ESaISt4pairIKS1_S2_EEED2Ev_ZNSt3mapIN7AscendC8HardwareENS0_10PVMemScopeESt4lessIS1_ESaISt4pairIKS1_S2_EEED1Ev_ZNSt8_Rb_treeIN7AscendC10PVMemScopeESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE8_M_eraseEPSt13_Rb_tree_nodeIS4_E_ZNSt3mapIN7AscendC10PVMemScopeEjSt4lessIS1_ESaISt4pairIKS1_jEEED2Ev_ZNSt3mapIN7AscendC10PVMemScopeEjSt4lessIS1_ESaISt4pairIKS1_jEEED1Ev_ZNSt8_Rb_treeIN7AscendC8HardwareESt4pairIKS1_NS0_10PVMemScopeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3__ZNSt8_Rb_treeIN7AscendC8HardwareESt4pairIKS1_NS0_10PVMemScopeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3__ZNSt8_Rb_treeIN7AscendC10PVMemScopeESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE24_M_get_insert_unique_posERS3__ZNSt8_Rb_treeIN7AscendC10PVMemScopeESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS3__ZNSt3mapIN7AscendC10PVMemScopeEjSt4lessIS1_ESaISt4pairIKS1_jEEEC2ESt16initializer_listIS6_ERKS3_RKS7__ZNSt3mapIN7AscendC10PVMemScopeEjSt4lessIS1_ESaISt4pairIKS1_jEEEC1ESt16initializer_listIS6_ERKS3_RKS7__ZN7AscendC8encoding17VecBinaryEncodingC2ESsSshhhh_ZN7AscendC8encoding17VecBinaryEncodingC1ESsSshhhh_ZN7AscendC13BinaryComputeIA128_N7float165Fp16TEhEEvRKSsS5_RT_S6_S6_T0_7Literal_ZN7AscendC4vaddERA128_N7float165Fp16TEPS1_S4_h7Literal_ZN7AscendC4vsubERA128_N7float165Fp16TEPS1_S4_h7Literal_ZN7AscendC4vmaxERA128_N7float165Fp16TEPS1_S4_h7Literal_ZN7AscendC4vminERA128_N7float165Fp16TEPS1_S4_h7Literal_ZN7AscendC4vdivERA128_N7float165Fp16TEPS1_S4_h7Literal_ZN7AscendC4vmulERA128_N7float165Fp16TEPS1_S4_h7Literal_ZN7AscendC13BinaryComputeIA64_fhEEvRKSsS3_RT_S4_S4_T0_7Literal_ZN7AscendC4vaddERA64_fPfS2_h7Literal_ZN7AscendC4vsubERA64_fPfS2_h7Literal_ZN7AscendC4vmaxERA64_fPfS2_h7Literal_ZN7AscendC4vminERA64_fPfS2_h7Literal_ZN7AscendC4vdivERA64_fPfS2_h7Literal_ZN7AscendC4vmulERA64_fPfS2_h7Literal_ZN7AscendC13BinaryComputeIA128_shEEvRKSsS3_RT_S4_S4_T0_7Literal_ZN7AscendC4vaddERA128_sPsS2_h7Literal_ZN7AscendC4vsubERA128_sPsS2_h7Literal_ZN7AscendC4vmaxERA128_sPsS2_h7Literal_ZN7AscendC4vminERA128_sPsS2_h7Literal_ZN7AscendC4vandERA128_sPsS2_h7Literal_ZN7AscendC3vorERA128_sPsS2_h7Literal_ZN7AscendC4vmulERA128_sPsS2_h7Literal_ZN7AscendC13BinaryComputeIA64_ihEEvRKSsS3_RT_S4_S4_T0_7Literal_ZN7AscendC4vaddERA64_iPiS2_h7Literal_ZN7AscendC4vsubERA64_iPiS2_h7Literal_ZN7AscendC4vmaxERA64_iPiS2_h7Literal_ZN7AscendC4vminERA64_iPiS2_h7Literal_ZN7AscendC4vmulERA64_iPiS2_h7Literal_ZN7AscendC13BinaryComputeIA128_thEEvRKSsS3_RT_S4_S4_T0_7Literal_ZN7AscendC4vandERA128_tPtS2_h7Literal_ZN7AscendC3vorERA128_tPtS2_h7Literal_ZN7AscendC8encoding20ScalarBinaryEncodingC2ESsSshhhh_ZN7AscendC8encoding20ScalarBinaryEncodingC1ESsSshhhh_ZN7AscendC19ScalarBinaryComputeIA128_N7float165Fp16TES2_hEEvRKSsS5_RT_S6_T0_T1_7Literal_ZN7AscendC5vmulsERA128_N7float165Fp16TEPS1_S1_h7Literal_ZN7AscendC6vlreluERA128_N7float165Fp16TEPS1_S1_h7Literal_ZN7AscendC5vaddsERA128_N7float165Fp16TEPS1_S1_h7Literal_ZN7AscendC5vmaxsERA128_N7float165Fp16TEPS1_S1_h7Literal_ZN7AscendC5vminsERA128_N7float165Fp16TEPS1_S1_h7Literal_ZN7AscendC19ScalarBinaryComputeIA64_ffhEEvRKSsS3_RT_S4_T0_T1_7Literal_ZN7AscendC5vmulsERA64_fPffh7Literal_ZN7AscendC6vlreluERA64_fPffh7Literal_ZN7AscendC5vaddsERA64_fPffh7Literal_ZN7AscendC5vmaxsERA64_fPffh7Literal_ZN7AscendC5vminsERA64_fPffh7Literal_ZN7AscendC19ScalarBinaryComputeIA128_sshEEvRKSsS3_RT_S4_T0_T1_7Literal_ZN7AscendC5vmulsERA128_sPssh7Literal_ZN7AscendC5vshlsERA128_sPssh7Literal_ZN7AscendC5vshrsERA128_sPssh7Literal_ZN7AscendC5vaddsERA128_sPssh7Literal_ZN7AscendC5vmaxsERA128_sPssh7Literal_ZN7AscendC5vminsERA128_sPssh7Literal_ZN7AscendC19ScalarBinaryComputeIA64_iihEEvRKSsS3_RT_S4_T0_T1_7Literal_ZN7AscendC5vmulsERA64_iPiih7Literal_ZN7AscendC5vaddsERA64_iPiih7Literal_ZN7AscendC5vmaxsERA64_iPiih7Literal_ZN7AscendC5vminsERA64_iPiih7Literal_ZN7AscendC19ScalarBinaryComputeIA64_ishEEvRKSsS3_RT_S4_T0_T1_7Literal_ZN7AscendC5vshlsERA64_iPish7Literal_ZN7AscendC5vshrsERA64_iPish7Literal_ZN7AscendC19ScalarBinaryComputeIA128_tshEEvRKSsS3_RT_S4_T0_T1_7Literal_ZN7AscendC5vshlsERA128_tPtsh7Literal_ZN7AscendC5vshrsERA128_tPtsh7Literal_ZN7AscendC19ScalarBinaryComputeIA64_jshEEvRKSsS3_RT_S4_T0_T1_7Literal_ZN7AscendC5vshlsERA64_jPjsh7Literal_ZN7AscendC5vshrsERA64_jPjsh7Literal_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0__ZNSt6vectorIiSaIiEEC1ESt16initializer_listIiERKS0__ZNSt6vectorIhSaIhEE12emplace_backIJiEEERhDpOT__ZNSt6vectorIhSaIhEE12emplace_backIJhEEERhDpOT__ZN7AscendC10GetTagListEPKhRA128_N7float165Fp16TERSt6vectorIhSaIhEE7Literal_ZN7AscendC10GetTagListEPKaRA128_N7float165Fp16TERSt6vectorIhSaIhEE7Literal_ZN7AscendC10GetTagListEPKN7float165Fp16TERA64_fRSt6vectorIhSaIhEE7Literal_ZN7AscendC10GetTagListEPKN8bfloat165Bf16TERA64_fRSt6vectorIhSaIhEE7Literal_ZN7AscendC10GetTagListEPKsRA64_fRSt6vectorIhSaIhEE7Literal_ZN7AscendC10GetTagListEPKiRA32_lRSt6vectorIhSaIhEE7Literal_ZN7AscendC10GetTagListEPKN7float165Fp16TERA64_iRSt6vectorIhSaIhEE7LiteralSA__ZN7AscendC10GetTagListEPKlRA64_fRSt6vectorIhSaIhEE7LiteralS8__ZN7AscendC10GetTagListEPKN8bfloat165Bf16TERA64_iRSt6vectorIhSaIhEE7LiteralSA_SA__ZN7AscendC10GetTagListEPKfRA32_lRSt6vectorIhSaIhEE7LiteralS8_S8__ZN7AscendC10GetTagListEPKN7float165Fp16TERA256_hRSt6vectorIhSaIhEE7LiteralSA_SA__ZN7AscendC10GetTagListEPKN7float165Fp16TERA256_aRSt6vectorIhSaIhEE7LiteralSA_SA__ZN7AscendC10GetTagListEPKfRA128_N7float165Fp16TERSt6vectorIhSaIhEE7LiteralSA_SA__ZN7AscendC10GetTagListEPKfRA128_N8bfloat165Bf16TERSt6vectorIhSaIhEE7LiteralSA_SA__ZN7AscendC10GetTagListEPKfRA128_sRSt6vectorIhSaIhEE7LiteralS8_S8__ZN7AscendC10GetTagListEPKiRA128_sRSt6vectorIhSaIhEE7LiteralS8__ZN7AscendC10GetTagListEPKlRA64_iRSt6vectorIhSaIhEE7LiteralS8__ZN7AscendC10GetTagListEPKN7float165Fp16TERA128_sRSt6vectorIhSaIhEE7LiteralSA__ZN7AscendC10GetTagListEPKfRA64_iRSt6vectorIhSaIhEE7LiteralS8__ZN7AscendC10GetTagListEPKsRA128_N7float165Fp16TERSt6vectorIhSaIhEE7Literal_ZN7AscendC10GetTagListEPKfRA64_fRSt6vectorIhSaIhEE7Literal_ZN7AscendC10GetTagListEPKiRA64_fRSt6vectorIhSaIhEE7Literal_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EOS6_S7__ZN7AscendC11CastComputeIA128_N7float165Fp16TEA256_hEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA128_N7float165Fp16TEPhh7Literal_ZN7AscendC12GetVcvtInstrERKSsjjjRKSt6vectorIhSaIhEE_ZN7AscendC11CastComputeIA128_N7float165Fp16TEA256_aEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA128_N7float165Fp16TEPah7Literal_ZN7AscendC11CastComputeIA64_fA128_N7float165Fp16TEEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA64_fPN7float165Fp16TEh7Literal_ZN7AscendC11CastComputeIA64_iA128_N7float165Fp16TEEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA64_iPN7float165Fp16TEh7LiteralS5__ZN7AscendC11CastComputeIA64_fA128_N8bfloat165Bf16TEEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA64_fPN8bfloat165Bf16TEh7Literal_ZN7AscendC11CastComputeIA64_iA128_N8bfloat165Bf16TEEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA64_iPN8bfloat165Bf16TEh7LiteralS5_S5__ZN7AscendC11CastComputeIA64_fA128_sEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA64_fPsh7Literal_ZN7AscendC11CastComputeIA32_lA64_fEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA32_lPfh7LiteralS3_S3__ZN7AscendC11CastComputeIA32_lA64_iEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA32_lPih7Literal_ZN7AscendC11CastComputeIA256_hA128_N7float165Fp16TEEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA256_hPN7float165Fp16TEh7LiteralS5_S5__ZN7AscendC11CastComputeIA256_aA128_N7float165Fp16TEEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA256_aPN7float165Fp16TEh7LiteralS5_S5__ZN7AscendC11CastComputeIA128_N7float165Fp16TEA64_fEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA128_N7float165Fp16TEPfh7LiteralS5_S5__ZN7AscendC11CastComputeIA128_N8bfloat165Bf16TEA64_fEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA128_N8bfloat165Bf16TEPfh7LiteralS5_S5__ZN7AscendC11CastComputeIA128_sA64_fEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA128_sPfh7LiteralS3_S3__ZN7AscendC11CastComputeIA128_sA64_iEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA128_sPih7LiteralS3__ZN7AscendC11CastComputeIA64_iA32_lEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA64_iPlh7LiteralS3__ZN7AscendC11CastComputeIA64_fA32_lEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA64_fPlh7LiteralS3__ZN7AscendC11CastComputeIA128_sA128_N7float165Fp16TEEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA128_sPN7float165Fp16TEh7LiteralS5__ZN7AscendC11CastComputeIA128_N7float165Fp16TEA128_sEEvRKSsS6_RT_T0_hRKSt6vectorIhSaIhEEPFjS6_jjjSE_E_ZN7AscendC4vcvtERA128_N7float165Fp16TEPsh7Literal_ZN7AscendC11CastComputeIA64_iA64_fEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA64_iPfh7LiteralS3__ZN7AscendC11CastComputeIA64_fA64_iEEvRKSsS4_RT_T0_hRKSt6vectorIhSaIhEEPFjS4_jjjSC_E_ZN7AscendC4vcvtERA64_fPih7Literal_ZN7AscendC11CastComputeIA64_fS1_EEvRKSsS3_RT_T0_hRKSt6vectorIhSaIhEEPFjS3_jjjSB_E_ZN7AscendC4vtrcERA64_fPf7Literalh_ZN7AscendC12GetVtrcInstrERKSsjjjRKSt6vectorIhSaIhEE_ZNKSt8_Rb_treeISsSt4pairIKSshESt10_Select1stIS2_ESt4lessISsESaIS2_EE4findERS1__ZNKSt3mapISshSt4lessISsESaISt4pairIKSshEEE2atERS3__ZN7AscendC8encoding12GlobalParams8InstanceEv_ZN7AscendC10VbrComputeIA64_ffEEvRKSsS3_RT_T0__ZN7AscendC3vbrERA64_ff_ZN7AscendC10VbrComputeIA128_N7float165Fp16TES2_EEvRKSsS5_RT_T0__ZN7AscendC3vbrERA128_N7float165Fp16TES1__ZN7AscendC10SelComputeIA64_fhEEvRKSsS3_RT_S4_S4_T0__ZN7AscendC4vselERA64_fPfS2_h_ZN7AscendC10SelComputeIA128_N7float165Fp16TEhEEvRKSsS5_RT_S6_S6_T0__ZN7AscendC4vselERA128_N7float165Fp16TEPS1_S4_h_ZN7AscendC10CmpComputeIhA64_fEEvRKSsS3_RT_T0_S6_S4__ZN7AscendC7vcmp_eqERhPfS1_h_ZN7AscendC7vcmp_neERhPfS1_h_ZN7AscendC7vcmp_gtERhPfS1_h_ZN7AscendC7vcmp_geERhPfS1_h_ZN7AscendC7vcmp_ltERhPfS1_h_ZN7AscendC7vcmp_leERhPfS1_h_ZN7AscendC10CmpComputeIhA128_N7float165Fp16TEEEvRKSsS5_RT_T0_S8_S6__ZN7AscendC7vcmp_eqERhPN7float165Fp16TES3_h_ZN7AscendC7vcmp_neERhPN7float165Fp16TES3_h_ZN7AscendC7vcmp_gtERhPN7float165Fp16TES3_h_ZN7AscendC7vcmp_geERhPN7float165Fp16TES3_h_ZN7AscendC7vcmp_ltERhPN7float165Fp16TES3_h_ZN7AscendC7vcmp_leERhPN7float165Fp16TES3_h_ZN7AscendC17DuplicatesComputeIA128_N7float165Fp16TES2_hEEvRKSsS5_RT_T0_T1_7Literal_ZN7AscendC4vdupERA128_N7float165Fp16TES1_h7Literal_ZN7AscendC17DuplicatesComputeIA64_jjhEEvRKSsS3_RT_T0_T1_7Literal_ZN7AscendC4vdupERA64_jjh7Literal_ZN7AscendC17DuplicatesComputeIA64_iihEEvRKSsS3_RT_T0_T1_7Literal_ZN7AscendC4vdupERA64_iih7Literal_ZN7AscendC17DuplicatesComputeIA128_tthEEvRKSsS3_RT_T0_T1_7Literal_ZN7AscendC4vdupERA128_tth7Literal_ZN7AscendC17DuplicatesComputeIA64_ffhEEvRKSsS3_RT_T0_T1_7Literal_ZN7AscendC4vdupERA64_ffh7Literal_ZN7AscendC17DuplicatesComputeIA128_sshEEvRKSsS3_RT_T0_T1_7Literal_ZN7AscendC4vdupERA128_ssh7Literal_ZN7AscendC13SprclrComputeE7Literal_ZN7AscendC6sprclrE7Literal_ZN7AscendC11VsqzComputeIA128_thEEvRKSsS3_RT_S4_T0_7Literal_ZN7AscendC4vsqzERA128_tPth7Literal_ZN7AscendC11VsqzComputeIA64_fhEEvRKSsS3_RT_S4_T0_7Literal_ZN7AscendC4vsqzERA64_fPfh7Literal_ZN7AscendC11VsqzComputeIA128_shEEvRKSsS3_RT_S4_T0_7Literal_ZN7AscendC4vsqzERA128_sPsh7Literal_ZN7AscendC11VsqzComputeIA64_jhEEvRKSsS3_RT_S4_T0_7Literal_ZN7AscendC4vsqzERA64_jPjh7Literal_ZN7AscendC11VsqzComputeIA128_N7float165Fp16TEhEEvRKSsS5_RT_S6_T0_7Literal_ZN7AscendC4vsqzERA128_N7float165Fp16TEPS1_h7Literal_ZN7AscendC11VsqzComputeIA64_ihEEvRKSsS3_RT_S4_T0_7Literal_ZN7AscendC4vsqzERA64_iPih7Literal_ZN7AscendC19GetStoreValidLengthERKSt6vectorIhSaIhEE7Literalj_ZN7AscendC7mem_barE7Literal_ZN7AscendC12ConstDefiner8InstanceEv_ZN7AscendC10PstComputeIhEEvRKSsS2_T_Pji7Literal_ZN7AscendC4pstsEhPji7Literal_ZN7AscendC12VsldbComputeIA256_aaEEvRT_PT0_ih_ZN7AscendC5vsldbERA256_aPaih_ZN7AscendC12VsldbComputeIA256_hhEEvRT_PT0_ih_ZN7AscendC5vsldbERA256_hPhih_ZN7AscendC12VsldbComputeIA128_ssEEvRT_PT0_ih_ZN7AscendC5vsldbERA128_sPsih_ZN7AscendC12VsldbComputeIA128_ttEEvRT_PT0_ih_ZN7AscendC5vsldbERA128_tPtih_ZN7AscendC12VsldbComputeIA64_iiEEvRT_PT0_ih_ZN7AscendC5vsldbERA64_iPiih_ZN7AscendC12VsldbComputeIA64_jjEEvRT_PT0_ih_ZN7AscendC5vsldbERA64_jPjih_ZN7AscendC12VsldbComputeIA32_llEEvRT_PT0_ih_ZN7AscendC5vsldbERA32_lPlih_ZN7AscendC12VsldbComputeIA128_N8bfloat165Bf16TES2_EEvRT_PT0_ih_ZN7AscendC5vsldbERA128_N8bfloat165Bf16TEPS1_ih_ZN7AscendC12VsldbComputeIA128_N7float165Fp16TES2_EEvRT_PT0_ih_ZN7AscendC5vsldbERA128_N7float165Fp16TEPS1_ih_ZN7AscendC12VsldbComputeIA64_ffEEvRT_PT0_ih_ZN7AscendC5vsldbERA64_fPfih_ZN7AscendC12VstusComputeIA128_N7float165Fp16TES2_EEvRKSsRA32_ajT_RPT0_7Literal_ZN7AscendC5vstusERA32_ajPN7float165Fp16TERS4_7Literal_ZN7AscendC12VstusComputeIA64_ffEEvRKSsRA32_ajT_RPT0_7Literal_ZN7AscendC5vstusERA32_ajPfRS2_7Literal_ZN7AscendC12VstasComputeIN7float165Fp16TEEEvRKSsPaRP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[%s:%d] block_idx: %d, core_type: %s %d %s: (__fbuf__ %s*)dst, (__cbuf__ %s*)src, nBurst=%hu, lenBurst=%hu, sourceGap=%hu, dstGap=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__cbuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cbuf__ %s*)dst, (__gm__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu, padMode=%hhu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cbuf__ %s*)dst, (__ubuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__ubuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ %s*)dst, (__cbuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s(%s)dst, (__cbuf__ %s*)src, convControl=%hu, nBurst=%hu, lenBurst=%hu, sourceGap=%hu, dstGap=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__cc__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu, crMode=%hhu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)dst, (__ubuf__ %s*)src, sid=%hhu, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu, crMode=%hhu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)dst, (__ubuf__ %s*)src, nBurst=%hu, lenBurst=%hu, srcStride=%hu, dstStride=%hu); basic_string::appendbasic_string::insert%s: __pos (which is %zu) > this->size() (which is %zu)OUTL1L0CDPf16L0CDPf32vabsvrecvrsqrtvreluvsqrtvlnvexpvnotppackpunpackvintlvvdintlvpintlvpdintlvVCVTFIVCVTFFVCVTIFVCVTIIf322s64f322s32f322s16f162s16f162s8f162u8bf162s32f322f16f322bf16bf162f32u82f16s82f16s162f16s162f32s322f32s642f32s322s64s322s16s642s32f322f32vcmp_eqvcmp_nevcmp_ltvcmp_gtvcmp_gevcmp_levaddvsubvmaxvminvandvorvdivvmulvaddsvmaxsvminsvmulsvlreluvshlsvshrscopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_matrix_cbuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_ubuf_to_cccopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_vector_cc_to_ubufcopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_ubuf_to_cccopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_matrix_cc_to_ubufcopy_depthwise_cc_to_ubufcopy_depthwise_cc_to_ubufcopy_depthwise_cc_to_ubufcopy_depthwise_cc_to_ubufcopy_depthwise_cc_to_ubufcopy_depthwise_cc_to_ubufcopy_depthwise_cc_to_ubufcopy_depthwise_cc_to_ubufcopy_cbuf_to_fbufcopy_cbuf_to_fbufcopy_cbuf_to_btcopy_cbuf_to_btcopy_cbuf_to_gmcopy_cbuf_to_gmcopy_gm_to_cbuf_multi_nd2nz_b8copy_gm_to_cbuf_multi_nd2nz_b8copy_gm_to_cbuf_multi_nd2nz_b8copy_gm_to_cbuf_multi_nd2nz_b8copy_gm_to_cbuf_multi_nd2nz_b32scopy_gm_to_cbuf_multi_nd2nz_b32scopy_gm_to_cbuf_multi_nd2nz_b32scopy_gm_to_cbuf_multi_nd2nz_b32scopy_gm_to_cbuf_multi_nd2nz_b32scopy_gm_to_cbuf_multi_nd2nz_b32scopy_gm_to_cbuf_multi_nd2nz_b16copy_gm_to_cbuf_multi_nd2nz_b16copy_gm_to_cbuf_multi_nd2nz_b16copy_gm_to_cbuf_multi_nd2nz_b16copy_gm_to_cbuf_multi_nd2nz_b16copy_gm_to_cbuf_multi_nd2nz_b16copy_gm_to_cbuf_multi_nd2nz_b16copy_gm_to_cbuf_multi_nd2nz_b16copy_ubuf_to_ubufcopy_ubuf_to_ubufcopy_ubuf_to_cbufcopy_ubuf_to_cbufcopy_gm_to_cbufcopy_gm_to_cbufcopy_cbuf_to_ubufcopy_cbuf_to_ubuf   %&  $!basic_string::substrset_atomic_noneset_atomic_f32set_atomic_f16set_atomic_s16set_atomic_bf16set_atomic_s8set_atomic_s32basic_string::basic_stringkernel_operator_set_atomic_add_debug.cpp[%s:%d] block_idx: %d, core_type: %s %d %s: %s(); set_atomic_s32set_atomic_s32set_atomic_s8set_atomic_s8set_atomic_bf16set_atomic_bf16set_atomic_s16set_atomic_s16set_atomic_f16set_atomic_f16set_atomic_f32set_atomic_f32set_atomic_noneset_atomic_none   %&  $!kernel_utils.cppCONDCONDITION_FLAGVMS4_SRRSVD_CNTARACC_VALST_ATOMIC_CFGMAX_MIN_CNTARCH_VERPIPE_VPIPE_MPIPE_MTE1PIPE_MTE2PIPE_MTE3PIPE_SPIPE_FIXSTATUS[%s:%d] block_idx: %d, core_type: %s %d %s:%serror: file name is empty [%s:%d] block_idx: %d, core_type: %s %d %s: warn: realpath return nullptr [%s:%d] block_idx: %d, core_type: %s %d %s: WriteFile(): file name = '%s', size = %d [%s:%d] block_idx: %d, core_type: %s %d %s:%serror: buffer is nullptr [%s:%d] block_idx: %d, core_type: %s %d %s:%serror: can't open file: %s [%s:%d] block_idx: %d, core_type: %s %d %s:%serror: write size %d [%s:%d] block_idx: %d, core_type: %s %d %s: set_fmatrix(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_deqscale((half)%f); [%s:%d] block_idx: %d, core_type: %s %d %s: set_deqscale(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_fmatrix_b(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_quant_pre(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_fpc(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_nd_para(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_vector_mask(%lu, %lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_mask_count(); [%s:%d] block_idx: %d, core_type: %s %d %s: set_mask_norm(); [%s:%d] block_idx: %d, core_type: %s %d %s: set_cond(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_condition_flag(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_ctrl(); [%s:%d] block_idx: %d, core_type: %s %d %s: set_ctrl(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: get_vms4_sr(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_rsvd_cnt(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_ar(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_acc_val(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_st_atomic_cfg(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_max_min_cnt(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_cmpmask((__ubuf__ void* )dst=%p); [maskLow=%lu, maskHigh=%lu] [%s:%d] block_idx: %d, core_type: %s %d %s: set_cmpmask((__ubuf__ void* )src=%p); [maskLow=%lu, maskHigh=%lu] [%s:%d] block_idx: %d, core_type: %s %d %s: dsb(%u); [%s:%d] block_idx: %d, core_type: %s %d %s: trap(); [%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_V); [%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_ALL); [%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_S); [%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_M); [%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_MTE1); [%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_MTE2); [%s:%d] block_idx: %d, core_type: %s %d %s: pipe_barrier(PIPE_MTE3); [%s:%d] block_idx: %d, core_type: %s %d %s: get_arch_ver(); [%s:%d] block_idx: %d, core_type: %s %d %s: get_pc(); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ uint64_t*)address, offset=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ void*)addr, prefetchLen=%I64d); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ void*)addr); [%s:%d] block_idx: %d, core_type: %s %d %s: set_data_exp_0(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_data_exp_1(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_data_exp_2(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: set_data_exp_3(%lu); [%s:%d] block_idx: %d, core_type: %s %d %s: wait_flag(%s, %s, %d); [%s:%d] block_idx: %d, core_type: %s %d %s: set_flag(%s, %s, %d); [%s:%d] block_idx: %d, core_type: %s %d %s: hwait_flag(%s, %s, %d, %d, %d); [%s:%d] block_idx: %d, core_type: %s %d %s: hset_flag(%s, %s, %d, %d, %d); [%s:%d] block_idx: %d, core_type: %s %d %s: set_condition_flag(); [%s:%d] block_idx: %d, core_type: %s %d %s: set_st_atomic_cfg(); %d%f%ld%luset_data_exp_3set_data_exp_2set_data_exp_1set_data_exp_0preloadpreloadpreloadpreloaddc_preloaddc_preloadget_pcget_arch_verpipe_barrierwait_flagset_flagtraphset_flaghwait_flagdsbset_flagwait_flagstd::string AscendC::FormatEvent(int32_t)set_cmpmaskget_cmpmaskget_max_min_cntset_st_atomic_cfgget_st_atomic_cfgget_acc_valget_arget_rsvd_cntget_vms4_srset_ctrlget_ctrlget_condition_flagset_condition_flagget_condset_condset_mask_normset_mask_countset_vector_maskset_nd_paraset_fpcset_quant_preset_fmatrix_bset_deqscaleset_deqscaleset_fmatrixTensorWriteFileG3?_p0tikcpp_base_check.cppvector::_M_realloc_insert[ERROR]%s [%s:%d]%s blockLen != 0dtypeBytes != 0dtypeBytes[0] != 0dtypeBytes[1] != 0GMBIASFIXBUF[ERROR]%s: mask value is not in range [%lu, %lu] [%s:%d]%s: mask value is not in range [%lu, %lu] [ERROR]%s: dst/src bit length is 32, mask_h must be 0 [%s:%d]%s: dst/src bit length is 32, mask_h must be 0 [ERROR]%s: dst/src bit length is 64, mask_h must be 0 [%s:%d]%s: dst/src bit length is 64, mask_h must be 0 [ERROR]%s, addr0: %lu, addr1: %lu, needSize: %lu [%s:%d]%s, addr0: %lu, addr1: %lu, needSize: %lu [ERROR]%s, src hardware address: %lu, dst hardware address: %lu [%s:%d]%s, src hardware address: %lu, dst hardware address: %lu [ERROR]%s, src hardware address: %lu, dst hardware address: %lu, needSize: %lu [%s:%d]%s, src hardware address: %lu, dst hardware address: %lu, needSize: %lu [ERROR]%s, Need size: %lu, while tensor size is %lu [%s:%d]%s, Need size: %lu, while tensor size is %lu [ERROR]%s, Allocated buffer size overflow, allocate buffer size is %lu, the limit size is %lu. [%s:%d]%s, Allocated buffer size overflow, allocate buffer size is %lu, the limit size is %lu. [ERROR]the tensorPos/expectPos hardware pos not found,tensorPos index is %hhu, expectedPos is %hhu. [%s:%d]the tensorPos/expectPos hardware pos not found,tensorPos index is %hhu, expectedPos is %hhu. [ERROR]%s, the tensor hardware pos is %s, the expect pos is %s. [%s:%d]%s, the tensor hardware pos is %s, the expect pos is %s. bool AscendC::check::TikcppBaseCheck::CheckTensorOverflowLow(std::vector&, uint64_t, uint32_t, std::vector&, const string&) constuint64_t AscendC::check::CalculateVectorMaxOffset(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t)bool AscendC::check::CheckOverlapSingleMany(std::vector&, std::vector&, std::vector&, const string&)[ERROR]intriName is null.tikcpp_check_util.cpp[%s:%d]intriName is null. N7AscendC5check15TikcppBaseCheckEtikcpp_copy_check.cppdst calculate size overflowsrc calculate size overflow[ERROR]maskArray size is zero.[%s:%d]maskArray size is zero. check dst tensor position failedcheck src tensor position failedcheck dst tensor buffersize failedcheck src tensor buffersize faileddst and src address overlappingN7AscendC5check15TikcppCopyCheckEtikcpp_data_copy_check.cpp[ERROR][%s][%s:%d][%s][%u] illegal hardPos %d [ERROR]instr %s src addr is %lu, which should be %u B Aligned [%s:%d]instr %s src addr is %lu, which should be %u B Aligned [ERROR]instr %s dst addr is %lu, which should be %u B Aligned [%s:%d]instr %s dst addr is %lu, which should be %u B Aligned GetHardwareBaseAddr    N7AscendC5check19TikcppDataCopyCheckE[ERROR]%s, size of leftPadding or rightpadding should be less than 32 Bytes tikcpp_data_copy_pad_check.cpp[%s:%d]%s, size of leftPadding or rightpadding should be less than 32 Bytes N7AscendC5check22TikcppDataCopyPadCheckEcheck dataCopyPacheck sliceInfo paramtersCore_[ERROR]%s, dstSliceInfo[%u]'s busrt len (%u) should be equal to SliceInfo[%u]'s busrt len (%u) tikcpp_data_copy_slice_check.cpp[%s:%d]%s, dstSliceInfo[%u]'s busrt len (%u) should be equal to SliceInfo[%u]'s busrt len (%u) [ERROR]%s, dim[%u]'s dstSliceInfo's busrt len should be equal to 1, but get (%u) [%s:%d]%s, dim[%u]'s dstSliceInfo's busrt len should be equal to 1, but get (%u) [ERROR]%s, dstSliceInfo[%u]'s start index (%u) should be lee than dstSliceInfo[%u]'s end index (%u) [%s:%d]%s, dstSliceInfo[%u]'s start index (%u) should be lee than dstSliceInfo[%u]'s end index (%u) [ERROR]%s, dstSliceInfo[%u]'s end index (%u) should be less than dstSliceInfo[%u]'s shape (%u) [%s:%d]%s, dstSliceInfo[%u]'s end index (%u) should be less than dstSliceInfo[%u]'s shape (%u) [ERROR]%s, srcSliceInfo[%u]'s start index (%u) should be lee than srcSliceInfo[%u]'s end index (%u) [%s:%d]%s, srcSliceInfo[%u]'s start index (%u) should be lee than srcSliceInfo[%u]'s end index (%u) [ERROR]%s, srcSliceInfo[%u]'s end index (%u) should be less than dst tensor dim[%u]'s shape (%u) [%s:%d]%s, srcSliceInfo[%u]'s end index (%u) should be less than dst tensor dim[%u]'s shape (%u) [ERROR]%s, construct datacopy intrs paramters block count failed, please check srcSliceInfo[0].burstLen(%u), srcSliceInfo[0].startIndex(%u), srcSliceInfo[0].endIndex(%u), srcSliceInfo[0].stride(%u) [%s:%d]%s, construct datacopy intrs paramters block count failed, please check srcSliceInfo[0].burstLen(%u), srcSliceInfo[0].startIndex(%u), srcSliceInfo[0].endIndex(%u), srcSliceInfo[0].stride(%u) [ERROR]%s, one dst stride len (%lu) should be multiple of block size (%lu), dstSliceInfo[0].stride(%u), dstDtypeBytes(%u) [%s:%d]%s, one dst stride len (%lu) should be multiple of block size (%lu), dstSliceInfo[0].stride(%u), dstDtypeBytes(%u) [ERROR]%s, one src stride len (%lu) should be multiple of block size (%lu), srcSliceInfo[0].stride(%u), srcDtypeBytes(%u) [%s:%d]%s, one src stride len (%lu) should be multiple of block size (%lu), srcSliceInfo[0].stride(%u), srcDtypeBytes(%u) [ERROR]%s, srcIntrsNum(%u) != dstIntrsNum(%u) [%s:%d]%s, srcIntrsNum(%u) != dstIntrsNum(%u) [ERROR]%s, srcIntrsNum(%u) is bigger than MAX_SLICE_SIZE(%u), please reset the sliceInfo parameter [%s:%d]%s, srcIntrsNum(%u) is bigger than MAX_SLICE_SIZE(%u), please reset the sliceInfo parameter check dst tensor position failed, it should be UBcheck total number of instructions mov or mov_align failedcheck src tensor position failed, it should be UBcheck ub tensor buffersize failedcheck data copy instr paramtersGetHardwareBaseAddr    N7AscendC5check24TikcppDataCopySliceCheckE[ERROR]unsupport Loaddata3dv1tikcpp_loaddata_check.cpp[%s:%d]unsupport Loaddata3dv1 [ERROR]check dst tensor position failed,the dst hardware pos support L1.[%s:%d]check dst tensor position failed,the dst hardware pos support L1. [ERROR]dst dtype bytes is zeros[%s:%d]dst dtype bytes is zeros [ERROR]check dst tensor position failed,the src hardware pos is L1, the dst hardware pos support L0A or L0B.[%s:%d]check dst tensor position failed,the src hardware pos is L1, the dst hardware pos support L0A or L0B. [ERROR]check src tensor position failed,the src hardware pos support L1.[%s:%d]check src tensor position failed,the src hardware pos support L1. [ERROR]check dst tensor position failed,the src hardware pos is GM, the dst hardware pos support L1 or L0A or L0B.[%s:%d]check dst tensor position failed,the src hardware pos is GM, the dst hardware pos support L1 or L0A or L0B. [ERROR]src/dst dtype bytes is zeros[%s:%d]src/dst dtype bytes is zeros [ERROR]check src tensor position failed,the src hardware pos support L1 or GM.[%s:%d]check src tensor position failed,the src hardware pos support L1 or GM. N7AscendC5check21TikcppLoaddata2dCheckEN7AscendC5check23TikcppLoaddata3dv1CheckEN7AscendC5check23TikcppLoaddata3dv2CheckEN7AscendC5check26TikcppLoaddata3dv2ProCheckEN7AscendC5check24TikcppLoadImageToL1CheckE[ERROR]%s: value(%u) is not in range [%u, %u] [%s:%d]%s: value(%u) is not in range [%u, %u] [ERROR]%s: needElementL0c(%u) is bigger than totalL0CSize(%u) [%s:%d]%s: needElementL0c(%u) is bigger than totalL0CSize(%u) [ERROR]%s: needElementL0b(%u) + needElementL0a(%u) is bigger than totalL1Size(%u) [%s:%d]%s: needElementL0b(%u) + needElementL0a(%u) is bigger than totalL1Size(%u) check src0 tensor position failedcheck src1 tensor position failedcheck MmadParams'm range failedcheck MmadParams'n range failedcheck MmadParams'k range failedtikcpp_mmad_check.cppcheck mmad overflow failedN7AscendC5check15TikcppMmadCheckEtikcpp_vec_binary_check.cppvcmpvsrc0 calculate size overflowsrc1 calculate size overflowcheck src0 tensor buffersize failedcheck src1 tensor buffersize faileddst and src0 address overlappingdst and src1 address overlapping[ERROR]instr %s dst addr is %lu, which should be 32B Aligned [%s:%d]instr %s dst addr is %lu, which should be 32B Aligned [ERROR]instr %s src0 addr is %lu, which should be 32B Aligned [%s:%d]instr %s src0 addr is %lu, which should be 32B Aligned [ERROR]instr %s src1 addr is %lu, which should be 32B Aligned [%s:%d]instr %s src1 addr is %lu, which should be 32B Aligned GetHardwareBaseAddr    N7AscendC5check20TikcppVecBinaryCheckEtikcpp_vec_binary_scalar_check.cppGetHardwareBaseAddr    N7AscendC5check26TikcppVecBinaryScalarCheckE[ERROR]src dtype bytes is zerostikcpp_vec_broadcast_check.cpp[%s:%d]src dtype bytes is zeros N7AscendC5check23TikcppVecBroadCastCheckEN7AscendC5check24TikcppBroadCastToMMCheckEtikcpp_vec_compare_scalar_check.cppGetHardwareBaseAddr    N7AscendC5check27TikcppVecCompareScalarCheckEtikcpp_vec_dup_check.cppN7AscendC5check17TikcppVecDupCheckEtikcpp_vec_gather_check.cpp[ERROR]offset dtype bytes is zeros[%s:%d]offset dtype bytes is zeros check offset tensor position failedcheck offset tensor buffersize failedoffset calculate size overflowN7AscendC5check20TikcppVecGatherCheckEtikcpp_vec_gather_mask_check.cppN7AscendC5check21TikcppGatherMaskCheckEsrctikcpp_vec_proposal_check.cppvbs32vconcatvextractvbs16vms4vms4v2[ERROR]valid bit number overflow 4.[%s:%d]valid bit number overflow 4. [ERROR]src index overflow element size.[%s:%d]src index overflow element size. N7AscendC5check22TikcppVecProposalCheckEtikcpp_vec_reduce_check.cpp[ERROR]dtype bytes is zeros[%s:%d]dtype bytes is zeros Check Reduce data typeCheck Reduce dst data sizevreduce_sumvreduce_max[ERROR]byteLen is %u, it shoule be greater than 0 [%s:%d]byteLen is %u, it shoule be greater than 0 [ERROR]%s, Reduce need dst data type (%u),dst src type (%u), dst wokr type (%u) should be same [%s:%d]%s, Reduce need dst data type (%u),dst src type (%u), dst wokr type (%u) should be same [ERROR]%s, Worktensor's size should be more than %lu, but get %lu [%s:%d]%s, Worktensor's size should be more than %lu, but get %lu [ERROR]%s, elementNumPerRep can not be 0. [%s:%d]%s, elementNumPerRep can not be 0. [ERROR]%s, Need least output size: %lu, while tensor size is %lu [%s:%d]%s, Need least output size: %lu, while tensor size is %lu check interface level 0 dst tensor position failedcheck interface level 0 src tensor position failedcheck interface level 0 work tensor position failedcheck work tensor buffersize failedCheck Reduce sum workLocal tensor sizeCheck Reduce max workLocal tensor sizeCheck Reduce min workLocal tensor sizecheck interface level 2 dst tensor position failedcheck interface level 2 src tensor position failedcheck interface level 2 work tensor position failedCheck Reduce Sum workLocal tensor sizeN7AscendC5check20TikcppVecReduceCheckEvcmaxvcminvcaddvcgaddCheck Whole Reduce data typevcgmaxvcgminvcpadd[ERROR]%s, Reduce need dst data type (%u),dst src type (%u), should be same tikcpp_vec_reduce_other_check.cpp[%s:%d]%s, Reduce need dst data type (%u),dst src type (%u), should be same [ERROR]%s, srcSize is: %lu, output size: %lu, while dst tensor size should be half of src tensor size [%s:%d]%s, srcSize is: %lu, output size: %lu, while dst tensor size should be half of src tensor size Check Whole Reduce dst data sizeCheck Block Reduce dst data sizeCheck Pair Reduce dst data sizeN7AscendC5check25TikcppVecReduceOtherCheckEN7AscendC5check23TikcppVecTransposeCheckEascend310B1_pv_factory.cppvaIndex < VA_REG_NUM./simlog/[%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_gpr_register X(%ld) error, code: %d [%s:%d] block_idx: %d, core_type: %s %d %s:%spv_read_register %d error, reg type: %d [%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_register %d error, reg type: %d [%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_memory error, mem_addr: %lu, mem_scope: %d, src_addr: %p, src_len: %lu, code: %d [%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_instr error, %u [%s:%d] block_idx: %d, core_type: %s %d %s:%spv_step error, instr_value: %u, code: %d [%s:%d] block_idx: %d, core_type: %s %d %s:%spv_read_memory error, mem_addr: %lu, mem_scope: %u, src_addr: %p, src_len: %lu, code: %d [%s:%d] block_idx: %d, core_type: %s %d %s:%spv_write_spr_register %s error, code: %d PARA_BASEDATA_MAIN_BASEDATA_UB_BASEDATA_SIZELPCNTFMATRIXPADDINGL2_VADDR_BASEL0_SET_VALUECOREIDL2_IN_MAINRPN_COR_IRSMMU_TAG_VERL1_3D_SIZEAIPP_SPR_0AIPP_SPR_1AIPP_SPR_2AIPP_SPR_3AIPP_SPR_4AIPP_SPR_5AIPP_SPR_6AIPP_SPR_7AIPP_SPR_8AIPP_SPR_9AIPP_SPR_10AIPP_SPR_11AIPP_SPR_12AIPP_SPR_13AIPP_SPR_14AIPP_SPR_15AIPP_SPR_16AIPP_SPR_17AIPP_SPR_18AIPP_SPR_19AIPP_SPR_20AIPP_SPR_21AIPP_SPR_22AIPP_SPR_23AIPP_SPR_24DATA_EXP_0DATA_EXP_1DATA_EXP_2DATA_EXP_3LOW_PRE_TBLSMASK_INDEXK_NUMRPN_OFFSETFCOL2IMGL3D_RPTPNT_COEVPIPEFPCQUANT_PREQUANT_POSTSYS_VA_BASESTACK_PHY_BASEVSPSYS_CNTVLSAFETY_CRC_ENSAFETY_CRC_DATASAFETY_CRC_EXCPAIPP_SPR_25AIPP_SPR_26AIPP_SPR_27AIPP_SPR_28AIPP_SPR_29AIPP_SPR_30AIPP_SPR_31THREAD_IDTHREAD_DIMFIXP_ADDRFMATRIX_DUAL_0ICACHE_PRL_STFMATRIX_BPCIE_RD_CTRLPCIE_WR_CTRLSUBBLOCKDIMSUBBLOCKIDND_PARAFMATRIX_DUAL_1FFTS_BASE_ADDRFIX_CLIP_RELULOOP4_PARACHANNEL_PARAELT_ANTIQ_PARAGROUP_CONVUNZIP_INDX_BASEUNZIP_INDX_LENCMPMASK0CMPMASK1AIC_ERROR_MASKCUBE_CTRL_0CUBE_CTRL_1SMMU_STREAMIDSMMU_SUBSTREAMIDTASK_CFG_0MEMMAP_0MEMMAP_1MEMMAP_2MEMMAP_3MEMMAP_4MEMMAP_5MEMMAP_6MEMMAP_7MEMMAP_8MEMMAP_9MEMMAP_10MEMMAP_11MEMMAP_12MEMMAP_13MEMMAP_14MEMMAP_15MEMMAP_16MEMMAP_17MEMMAP_18MEMMAP_19MEMMAP_20MEMMAP_21MEMMAP_22MEMMAP_23MEMMAP_24MEMMAP_25MEMMAP_26MEMMAP_27MEMMAP_28MEMMAP_29MEMMAP_30MEMMAP_31MEMMAP_32MEMMAP_33MEMMAP_34MEMMAP_35MEMMAP_36MEMMAP_37MEMMAP_38MEMMAP_39MEMMAP_40MEMMAP_41MEMMAP_42MEMMAP_43MEMMAP_44MEMMAP_45MEMMAP_46MEMMAP_47MEMMAP_48MEMMAP_49MEMMAP_50MEMMAP_51MEMMAP_52MEMMAP_53MEMMAP_54MEMMAP_55MEMMAP_56MEMMAP_57MEMMAP_58MEMMAP_59MEMMAP_60MEMMAP_61MEMMAP_62MEMMAP_63AIC_ERROR_0AIC_ERROR_1AIC_ERROR_2AIC_ERROR_3AIC_ERROR_4AIC_ERROR_5AIC_ERROR_MASK_0AIC_ERROR_MASK_1AIC_ERROR_MASK_2AIC_ERROR_MASK_3AIC_ERROR_MASK_4AIC_ERROR_MASK_5UNDEGetOutputRunRunSetInputSetArchiRegistersGetArchiRegistersSetSPRRegistersSetGPRRegistersvoid AscendC::ModelFactory::GetVARegUbAddr(uint32_t, uint64_t (&)[8])void AscendC::ModelFactory::SetVARegUbAddr(uint32_t, uint64_t*)void AscendC::ModelFactory::GetVARegGmAddr(uint32_t, uint64_t (&)[8])void AscendC::ModelFactory::SetVARegGmAddr(uint32_t, uint64_t*)kernel_operator_fixpipe_debug.cppfalse && "dst scope unsupported."[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ void*)dst, entire=%hu, type=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ void*)dst, entire=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cbuf__ %s*)dst, (__cc__ %s*)src, sid=%hhu, nSize=%hu, mSize=%hu, dstStrideDstD=%u, srcStride=%hu, unitFlagMode=%hhu, clipReluPre=%hhu, quantPre=%hhu, reluPre=%hhu, channelSplit=%hhu, nZ2NdEn=%hhu, c0PadEn=%hhu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__gm__ %s*)dst, (__cc__ %s*)src, sid=%hhu, nSize=%hu, mSize=%hu, dstStrideDstD=%u, srcStride=%hu, unitFlagMode=%hhu, quantPre=%hhu, reluPre=%hhu, channelSplit=%hhu, nZ2NdEn=%hhu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ubuf__ %s*)dst, (__cc__ %s*)src, sid=%hhu, nSize=%hu, mSize=%hu, dstStrideDstD=%u, srcStride=%hu, unitFlagMode=%hhu, quantPre=%hhu, reluPre=%hhu, channelSplit=%hhu, nZ2NdEn=%hhu); dccidccidccidccicopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_ubcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_gmcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufcopy_matrix_cc_to_cbufuint8_t AscendC::InferDstPos(AscendC::PVMemScope)kernel_operator_mm_debug.cppblockCount >= MIN_BLOCK_COUNTblockLen >= MIN_BLOCK_LENcacbcbufMAX_LOAD2D_SID >= intriParams.sid[%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)c, (__ca__ %s*)a, (__cb__ %s*)b, m=%hu, k=%hu, n=%hu, unitFlag=%hhu, kDirectionAlign=%hhu, cmatrixSource=%hhu, cmatrixInitVal=%hhu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s(padValue=%s); false && "dst scope only support l0a/l0b."[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s %s*)dst, (%s %s*)src, indexId=%hu, repeat=%huu, srcStride=%hu, dstGap=%hu, addr_cal_mode_t=%huu, dstFracGap=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s %s*)dst, (%s %s*)src, baseIdx=%hu, repeat=%huu, srcStride=%hu, dstStride=%hu, sid=%huu, transpose=%hhu, addr_cal_mode_t=%huu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s %s*)dst, (%s %s*)src, baseIdx=%hu, repeat=%huu, srcStride=%hu, dstStride=%hu, sid=%huu, addr_cal_mode_t=%huu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cc__ %s*)c, (__ca__ %s*)a, (__cb__ %s*)b=, m=%hu, k=%hu, n=%hu, init_val_controlC=%hhu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__%s__ %s*)dst, repeat=%I64d, value=%s); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__ca__ %s*)dst, (__cbuf__ %s*)src, kExtension=%hu, mExtension=%hu, kStartPt=%hu, mStartPt=%hu, strideW=%hhu, strideH=%hhu, Wk=%hu, Hk=%hu, dilationFilterW=%hhu, dilationFilterH=%hhu, filterSizeW=%hhu, filterSizeH=%hhu, transpose=%hhu, fMatrixCtrl=%hhu, sizeChannel=%hu); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((__cb__ %s*)dst, (__cbuf__ %s*)src, kExtension=%hu, mExtension=%hu, kStartPt=%hu, mStartPt=%hu, strideW=%hhu, strideH=%hhu, Wk=%hu, Hk=%hu, dilationFilterW=%hhu, dilationFilterH=%hhu, filterSizeW=%hhu, filterSizeH=%hhu, transpose=%hhu, fMatrixCtrl=%hhu, sizeChannel=%hu); false && "dst pos unsupported."MAX_LOAD3D_L1 >= intriParams.l1HintriParams.l1H >= MIN_LOAD3D_L1MAX_LOAD3D_L1 >= intriParams.l1WintriParams.l1W >= MIN_LOAD3D_L1intriParams.channelSize >= MIN_LOAD3D_CHANNEL_SIZEintriParams.kExtension >= MIN_LOAD3D_EXTENSIONintriParams.mExtension >= MIN_LOAD3D_EXTENSIONMAX_LOAD3D_STRIDE >= intriParams.strideWintriParams.strideW >= MIN_LOAD3D_STRIDEMAX_LOAD3D_STRIDE >= intriParams.strideHintriParams.strideH >= MIN_LOAD3D_STRIDEintriParams.filterW >= MIN_LOAD3D_FILTERintriParams.filterH >= MIN_LOAD3D_FILTERintriParams.dilationFilterW >= MIN_LOAD3D_DILATION_FILTERintriParams.dilationFilterH >= MIN_LOAD3D_DILATION_FILTERfalse && "dst scope unsupported this data type"l1W > 0l1H > 0res && "data type unsupported"set_paddingset_paddingset_paddingset_paddingset_paddingset_paddingset_paddingset_paddingvoid AscendC::CreateCaCbMatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = unsigned int; S_T = unsigned int; int64_t = long int]create_cbuf_matrixcreate_cbuf_matrixcreate_cb_matrixcreate_cb_matrixvoid AscendC::CreateCaCbMatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = float; S_T = unsigned int; int64_t = long int]create_ca_matrixcreate_ca_matrixcreate_cb_matrixcreate_cb_matrixvoid AscendC::CreateCaCbMatrixPv(AscendC::Hardware, L0_T*, int64_t, S_T) [with L0_T = float16::Fp16T; S_T = float16::Fp16T; int64_t = long int]create_ca_matrixcreate_ca_matrixmadmadmadmadmadmadmadmadmadmadmadmadmadmadmadmadmadmadvoid AscendC::CheckMmadDtype() [with DstT = float16::Fp16T; Src0T = float16::Fp16T; Src1T = float16::Fp16T]madmadvoid AscendC::CheckMmadDtype() [with DstT = int; Src0T = unsigned char; Src1T = signed char]madmadmadmadvoid AscendC::CheckMmadDtype() [with DstT = int; Src0T = unsigned char; Src1T = unsigned char]madmadvoid AscendC::CheckMmadDtype() [with DstT = unsigned int; Src0T = unsigned char; Src1T = unsigned char]madmadimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbimg2colv2_cbuf_to_cbvoid AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = signed char]void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = signed char]void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = signed char]img2colv2_cbuf_to_caimg2colv2_cbuf_to_cavoid AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = unsigned char]void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = unsigned char]void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = unsigned char]img2colv2_cbuf_to_caimg2colv2_cbuf_to_cavoid AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = int]void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = int]void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = int]img2colv2_cbuf_to_caimg2colv2_cbuf_to_cavoid AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = unsigned int]void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = unsigned int]void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = unsigned int]img2colv2_cbuf_to_caimg2colv2_cbuf_to_cavoid AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = float]void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = float]void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = float]img2colv2_cbuf_to_caimg2colv2_cbuf_to_cavoid AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = float16::Fp16T]void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = float16::Fp16T]void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = float16::Fp16T]img2colv2_cbuf_to_caimg2colv2_cbuf_to_cavoid AscendC::CheckLoad3dV2Dst(AscendC::Hardware) [with T = bfloat16::Bf16T]void AscendC::CheckLoad3dV2Param(const AscendC::LoadData3DParamsV2&) [with T = bfloat16::Bf16T]void AscendC::Load3DV2Pv(T*, T*, AscendC::Hardware, AscendC::Hardware, const AscendC::LoadData3DParamsV2&) [with T = bfloat16::Bf16T]img2colv2_cbuf_to_caimg2colv2_cbuf_to_caload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbufload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_cbload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_gm_to_caload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_cbload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_caload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_cb_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposeload_cbuf_to_ca_transposevoid AscendC::Load2dv1PvTransposeImpl(void*, void*, const AscendC::UnaryPvParams&, const AscendC::LoadData2dTransposeParams&)void AscendC::Load2dv1PvImpl(void*, void*, const AscendC::UnaryPvParams&, const AscendC::LoadData2DParams&)void AscendC::CheckBroadCastParam(uint8_t, uint8_t)void AscendC::CheckLoad2dParam(const AscendC::LoadData2DParams&)vector_boolvector_f16vector_f32vector_s16vector_s32vector_u16kernel_operator_reg_base_vec_binary_debug.cpp[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s)src0, (%s)src1, (%s)preg); vmulvmulvmulvmulvmulvmulvmulvmulvdivvdivvdivvdivvorvorvorvorvandvandvandvandvminvminvminvminvminvminvminvminvmaxvmaxvmaxvmaxvmaxvmaxvmaxvmaxvsubvsubvsubvsubvsubvsubvsubvsubvaddvaddvaddvaddvaddvaddvaddvadd   %&  $!vector_u32kernel_operator_reg_base_vec_binary_scalar_debug.cpp[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s)src0, (%s)scalar, (%s)preg); vminsvminsvminsvminsvminsvminsvminsvminsvmaxsvmaxsvmaxsvmaxsvmaxsvmaxsvmaxsvmaxsvaddsvaddsvaddsvaddsvaddsvaddsvaddsvaddsvshrsvshrsvshrsvshrsvshrsvshrsvshrsvshrsvshlsvshlsvshlsvshlsvshlsvshlsvshlsvshlsvlreluvlreluvlreluvlreluvmulsvmulsvmulsvmulsvmulsvmulsvmulsvmuls   %&  $!vector_u8vector_s8vector_bf16vector_s64kernel_operator_reg_base_vec_cast_debug.cpp[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s)src, (vector_bool)preg); vtrcvtrcvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvtvcvt   %&  $!vbrvselkernel_operator_reg_base_vec_cmpsel_debug.cpp[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s)scalar, (%s)preg); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s)src1, (%s)src2, (%s)preg); vbrvbrvbrvbrvselvselvselvselvcmp_levcmp_levcmp_ltvcmp_ltvcmp_gevcmp_gevcmp_gtvcmp_gtvcmp_nevcmp_nevcmp_eqvcmp_eqvcmp_levcmp_levcmp_ltvcmp_ltvcmp_gevcmp_gevcmp_gtvcmp_gtvcmp_nevcmp_nevcmp_eqvcmp_eq   %&  $!vdupkernel_operator_reg_base_vec_duplicate_debug.cppvdupvdupvdupvdupvdupvdupvdupvdupvdupvdupvdupvdup   %&  $!vsqzkernel_operator_reg_base_vec_gather_mask_debug.cpp[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s)src, (%s)preg); vsqzvsqzvsqzvsqzvsqzvsqzvsqzvsqzvsqzvsqzvsqzvsqz   %&  $!pstspldsmovp_b16movp_b32vector_u64pge_b8pge_b16pge_b32pset_b8pset_b16pset_b32plt_b8plt_b16plt_b32kernel_operator_reg_base_vec_load_store.cpp[%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)src, (uint32_t* )base, int32_t offset); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s*)base, int32_t config, vector_bool preg); [%s:%d] block_idx: %d, core_type: %s %d %s: %s(vector_align& alignData, uint32_t offset, (%s)src, (%s*&)base, Literal post); [%s:%d] block_idx: %d, core_type: %s %d %s: %s(vector_align alignData, (%s*&)base, int32_t offset, Literal post); [%s:%d] block_idx: %d, core_type: %s %d %s: %s(vector_align& alignData, (%s)src, (%s*&)base, Literal post); [%s:%d] block_idx: %d, core_type: %s %d %s: %s(vector_align alignData, (%s*&)base); [%s:%d] block_idx: %d, core_type: %s %d %s: %s(vector_align& alignData, (%s*&)base); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (uint32_t* )base, int32_t offset); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s*)base, int32_t offset, vector_bool preg); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)data, (%s*)base, int32_t config, vector_bool preg); [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst, (%s*)base, int32_t offset); [%s:%d] block_idx: %d, core_type: %s %d %s: (vector_bool)preg = %s((uint32_t& )scalar); vldusvldusvldusvldusvldusvldusvldusvldusvldusvldusvldusvldusvldusvldusvldusvldusvldasvldasvldasvldasvldasvldasvstarvstarvstarvstarvstarvstarvstarvstarvstarvstarvstarvstarvsturvsturvsturvsturvsturvsturvsturvsturvsturvsturvsturvsturvstasvstasvstasvstasvstusvstusvstusvstusvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsstbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvsldbvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvstsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldsvldspstspstspset_b32pset_b32pset_b16pset_b16pset_b8pset_b8pge_b32pge_b32pge_b16pge_b16pge_b8pge_b8movp_b32movp_b32movp_b16movp_b16pldspldsplt_b32plt_b32plt_b16plt_b16plt_b8plt_b8   %&  $!    pmovpintlv_b8pintlv_b16pintlv_b32pdintlv_b8pdintlv_b16pdintlv_b32kernel_operator_reg_base_vec_move_debug.cpp[%s:%d] block_idx: %d, core_type: %s %d %s: %s((vector_bool)dst, (vector_bool)src; [%s:%d] block_idx: %d, core_type: %s %d %s: %s((%s)dst0, (%s)dst1, (%s)src0, (%s)src1; [%s:%d] block_idx: %d, core_type: %s %d %s: %s((vector_bool)dst0, (vector_bool)dst1, (vector_bool)src0, (vector_bool)src1; pmovpmovpdintlv_b32pdintlv_b32pdintlv_b16pdintlv_b16pdintlv_b8pdintlv_b8pintlv_b32pintlv_b32pintlv_b16pintlv_b16pintlv_b8pintlv_b8vdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvdintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvvintlvpunpackpunpackppackppack   %&  $!kernel_operator_reg_base_vec_reduce_debug.cppvcpaddvcpaddvcpaddvcpaddvcgminvcgminvcgminvcgminvcgmaxvcgmaxvcgmaxvcgmaxvcgaddvcgaddvcgaddvcgaddvcminvcminvcminvcminvcmaxvcmaxvcmaxvcmaxvcaddvcaddvcaddvcadd   %&  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